UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
//\r
/**\r
a ASM function to transfer control to OS.\r
- \r
+\r
@param S3WakingVector The S3 waking up vector saved in ACPI Facs table\r
- @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer \r
+ @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer\r
**/\r
typedef\r
VOID\r
}\r
\r
//\r
- // NOTE: Because Debug Timer interrupt and system interrupts will be disabled \r
+ // NOTE: Because Debug Timer interrupt and system interrupts will be disabled\r
// in BootScriptExecuteDxe, the rest code in S3ResumeBootOs() cannot be halted\r
// by soft debugger.\r
//\r
\r
/**\r
Restore S3 page table because we do not trust ACPINvs content.\r
- If BootScriptExector driver will not run in 64-bit mode, this function will do nothing. \r
+ If BootScriptExector driver will not run in 64-bit mode, this function will do nothing.\r
\r
@param S3NvsPageTableAddress PageTableAddress in ACPINvs\r
@param Build4GPageTableOnly If BIOS just build 4G page table only\r
//\r
PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
Page1GSupport = FALSE;\r
if (PcdGetBool(PcdUse1GPageTable)) {\r
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
}\r
}\r
}\r
- \r
+\r
//\r
// Get physical address bits supported.\r
//\r
PhysicalAddressBits = 36;\r
}\r
}\r
- \r
+\r
//\r
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
//\r
NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
NumberOfPdpEntriesNeeded = 512;\r
}\r
- \r
+\r
PageMapLevel4Entry = PageMap;\r
PageAddress = 0;\r
for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
//\r
PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
//\r
// Make a PML4 Entry\r
//\r
\r
if (Page1GSupport) {\r
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;\r
- \r
+\r
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
//\r
// Fill in the Page Directory entries\r
//\r
// Each Directory Pointer entries points to a page of Page Directory entires.\r
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
- // \r
+ //\r
PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
//\r
// Fill in a Page Directory Pointer Entries\r
//\r
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
PageDirectoryPointerEntry->Bits.Present = 1;\r
- \r
+\r
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
//\r
// Fill in the Page Directory entries\r
}\r
return ;\r
} else {\r
- //\r
- // If DXE is running 32-bit mode, no need to establish page table.\r
- //\r
+ //\r
+ // If DXE is running 32-bit mode, no need to establish page table.\r
+ //\r
return ;\r
}\r
}\r
\r
//\r
// Send SMI to APs\r
- // \r
+ //\r
SendSmiIpiAllExcludingSelf ();\r
//\r
// Send SMI to BSP\r
);\r
if (!EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot script\n"));\r
- \r
+\r
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {\r
Status = SmmAccess->Close ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);\r
}\r
\r
DEBUG ((DEBUG_INFO, "Lock all SMRAM regions before executing boot script\n"));\r
- \r
+\r
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {\r
Status = SmmAccess->Lock ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);\r
}\r
if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
//\r
// On some platform, such as ECP, a dispatch node in boot script table may execute a 32-bit PEIM which may need PeiServices\r
- // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)). \r
+ // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)).\r
//\r
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
//\r
// Make sure the newly allocated IDT align with 16-bytes\r
- // \r
+ //\r
IdtBuffer = AllocatePages (EFI_SIZE_TO_PAGES((IdtDescriptor->Limit + 1) + 16));\r
if (IdtBuffer == NULL) {\r
REPORT_STATUS_CODE (\r
//\r
// Additional 16 bytes allocated to save IA32 IDT descriptor and Pei Service Table Pointer\r
// IA32 IDT descriptor will be used to setup IA32 IDT table for 32-bit Framework Boot Script code\r
- // \r
+ //\r
ZeroMem (IdtBuffer, 16);\r
AsmReadIdtr ((IA32_DESCRIPTOR *)IdtBuffer);\r
CopyMem ((VOID*)((UINT8*)IdtBuffer + 16),(VOID*)(IdtDescriptor->Base), (IdtDescriptor->Limit + 1));\r
// Save IDT\r
//\r
AsmReadIdtr (&PeiS3ResumeState->Idtr);\r
- \r
+\r
//\r
// Report Status Code to indicate S3 boot script execution\r
//\r
DEBUG (( DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context));\r
DEBUG (( DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable));\r
- DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); \r
+ DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase));\r
AsmWriteGdtr (&mGdt);\r
//\r
// update segment selectors per the new GDT.\r
- // \r
+ //\r
AsmSetDataSelectors (DATA_SEGEMENT_SELECTOR);\r
//\r
// Restore interrupt state.\r
Main entry for S3 Resume PEIM.\r
\r
This routine is to install EFI_PEI_S3_RESUME2_PPI.\r
- \r
+\r
@param FileHandle Handle of the file being invoked.\r
@param PeiServices Pointer to PEI Services table.\r
\r
projects / mirror_edk2.git / blobdiff