MdeModulePkg/PciBus: Shadow option ROM after BARs are programmed

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1376

Today's implementation reuses the 32bit MMIO resource requested by
all PCI devices MMIO BARs when shadowing the option ROM.
Take a simple example, a system has only one PCI device. It requires
8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation
only requests 8MB (max of 4M and 8M) 32bit MMIO from
PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range
[3GB, 3GB+8MB) is allocated. The 3GB base address is firstly
programmed to the option ROM BAR for option ROM shadow. Then the
option ROM decoding is turned off and 3GB base address is programmed
to the 32bit MMIO BAR.

It doesn't cause issues when the device doesn't request too much
MMIO.
But when the device contains a 64bit MMIO BAR which requests 4GB MMIO
and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is
allocated for the option ROM. When the option ROM is being shadowed,
64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is
given to the 64bit BAR.
The range overlaps with the option ROM range which may cause the
device malfunction (e.g.: option ROM cannot be read out) when the
device has two separate decoders: one for MMIO BAR, the other for
option ROM.

The patch requests dedicated MEM32 resource for Option ROMs and
moves the Option ROM shadow logic after all MMIO BARs are programmed.
The MMIO BAR setting to 0 when shadowing Option ROM is also skipped
because the MMIO BAR already contains the correct value.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index f9eebdd5a87bf9a7290f2ee8561cd445a29e31ab..693880285726d2b3ab9e7b7be2a762246571e88a 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -1,7 +1,7 @@
 /** @file\r
   Header files and data structures needed by PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -67,6 +67,7 @@ typedef enum {
   PciBarTypePMem32,\r
   PciBarTypeMem64,\r
   PciBarTypePMem64,\r
+  PciBarTypeOpRom,\r
   PciBarTypeIo,\r
   PciBarTypeMem,\r
   PciBarTypeMaxType\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index b81f81a1368a028dfb1c5bbd6df4ca714318959a..7255bcfbbcea2d06f95deaeafdc4817386b13ded 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -24,6 +24,7 @@ CHAR16 *mBarTypeStr[] = {
   L"PMem32",\r
   L" Mem64",\r
   L"PMem64",\r
+  L" OpRom",\r
   L"    Io",\r
   L"   Mem",\r
   L"Unknow"\r
@@ -425,15 +426,9 @@ PciHostBridgeResourceAllocator (
   PCI_RESOURCE_NODE                              PMem32Pool;\r
   PCI_RESOURCE_NODE                              Mem64Pool;\r
   PCI_RESOURCE_NODE                              PMem64Pool;\r
-  BOOLEAN                                        ReAllocate;\r
   EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD        HandleExtendedData;\r
   EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD  AllocFailExtendedData;\r
 \r
-  //\r
-  // Reallocate flag\r
-  //\r
-  ReAllocate = FALSE;\r
-\r
   //\r
   // It may try several times if the resource allocation fails\r
   //\r
@@ -514,6 +509,17 @@ PciHostBridgeResourceAllocator (
                        PciResUsageTypical\r
                        );\r
 \r
+      //\r
+      // Get the max ROM size that the root bridge can process\r
+      // Insert to resource map so that there will be dedicate MEM32 resource range for Option ROM.\r
+      // All devices' Option ROM share the same MEM32 resource.\r
+      //\r
+      MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
+      RootBridgeDev->PciBar[0].BarType   = PciBarTypeOpRom;\r
+      RootBridgeDev->PciBar[0].Length    = MaxOptionRomSize;\r
+      RootBridgeDev->PciBar[0].Alignment = MaxOptionRomSize - 1;\r
+      GetResourceFromDevice (RootBridgeDev, IoBridge, Mem32Bridge, PMem32Bridge, Mem64Bridge, PMem64Bridge);\r
+\r
       //\r
       // Create resourcemap by going through all the devices subject to this root bridge\r
       //\r
@@ -526,38 +532,6 @@ PciHostBridgeResourceAllocator (
         PMem64Bridge\r
         );\r
 \r
-      //\r
-      // Get the max ROM size that the root bridge can process\r
-      //\r
-      RootBridgeDev->RomSize = Mem32Bridge->Length;\r
-\r
-      //\r
-      // Skip to enlarge the resource request during realloction\r
-      //\r
-      if (!ReAllocate) {\r
-        //\r
-        // Get Max Option Rom size for current root bridge\r
-        //\r
-        MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-\r
-        //\r
-        // Enlarger the mem32 resource to accomdate the option rom\r
-        // if the mem32 resource is not enough to hold the rom\r
-        //\r
-        if (MaxOptionRomSize > Mem32Bridge->Length) {\r
-\r
-          Mem32Bridge->Length     = MaxOptionRomSize;\r
-          RootBridgeDev->RomSize  = MaxOptionRomSize;\r
-\r
-          //\r
-          // Alignment should be adjusted as well\r
-          //\r
-          if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
-            Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
-          }\r
-        }\r
-      }\r
-\r
       //\r
       // Based on the all the resource tree, construct ACPI resource node to\r
       // submit the resource aperture to pci host bridge protocol\r
@@ -760,8 +734,6 @@ PciHostBridgeResourceAllocator (
       if (EFI_ERROR (Status)) {\r
         return Status;\r
       }\r
-\r
-      ReAllocate = TRUE;\r
     }\r
   }\r
   //\r
@@ -828,11 +800,6 @@ PciHostBridgeResourceAllocator (
       &PMem64Base\r
       );\r
 \r
-    //\r
-    // Process option rom for this root bridge\r
-    //\r
-    ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
-\r
     //\r
     // Create the entire system resource map from the information collected by\r
     // enumerator. Several resource tree was created\r
@@ -889,6 +856,20 @@ PciHostBridgeResourceAllocator (
       PMem64Bridge\r
       );\r
 \r
+    //\r
+    // Process Option ROM for this root bridge after all BARs are programmed.\r
+    // The PPB's MEM32 RANGE BAR is re-programmed to the Option ROM BAR Base in order to\r
+    // shadow the Option ROM of the devices under the PPB.\r
+    // After the shadow, Option ROM BAR decoding is turned off and the PPB's MEM32 RANGE\r
+    // BAR is restored back to the original value.\r
+    // The original value is programmed by ProgramResource() above.\r
+    //\r
+    DEBUG ((\r
+      DEBUG_INFO, "Process Option ROM: BAR Base/Length = %lx/%lx\n",\r
+      RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length\r
+      ));\r
+    ProcessOptionRom (RootBridgeDev, RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length);\r
+\r
     IoBridge    ->PciDev->PciBar[IoBridge    ->Bar].BaseAddress = IoBase;\r
     Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;\r
     PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index c2be85a906af289ce694dc5f2114ce6d6be007a4..aa314474dd7715510af211b2f6b31ae57da1e9c9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -583,23 +583,10 @@ RomDecode (
   )\r
 {\r
   UINT32              Value32;\r
-  UINT32              Offset;\r
-  UINT32              OffsetMax;\r
   EFI_PCI_IO_PROTOCOL *PciIo;\r
 \r
   PciIo = &PciDevice->PciIo;\r
   if (Enable) {\r
-    //\r
-    // Clear all bars\r
-    //\r
-    OffsetMax = 0x24;\r
-    if (IS_PCI_BRIDGE(&PciDevice->Pci)) {\r
-      OffsetMax = 0x14;\r
-    }\r
-\r
-    for (Offset = 0x10; Offset <= OffsetMax; Offset += sizeof (UINT32)) {\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
-    }\r
 \r
     //\r
     // set the Rom base address: now is hardcode\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index f3e51d61508512f4c6e9e309318b0edebfedbfff..d3cbefbadfefe56854a279327dd667ec787a655a 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -446,13 +446,14 @@ GetResourceFromDevice (
     switch ((PciDev->PciBar)[Index].BarType) {\r
 \r
     case PciBarTypeMem32:\r
+    case PciBarTypeOpRom:\r
 \r
       Node = CreateResourceNode (\r
               PciDev,\r
               (PciDev->PciBar)[Index].Length,\r
               (PciDev->PciBar)[Index].Alignment,\r
               Index,\r
-              PciBarTypeMem32,\r
+              (PciDev->PciBar)[Index].BarType,\r
               PciResUsageTypical\r
               );\r
 \r
@@ -1307,7 +1308,13 @@ ProgramBar (
                  1,\r
                  &Address\r
                  );\r
+  //\r
+  // Continue to the case PciBarTypeOpRom to set the BaseAddress.\r
+  // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture\r
+  // the MEM32 resource requirement for Option ROM shadow.\r
+  //\r
 \r
+  case PciBarTypeOpRom:\r
     Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
 \r
     break;\r
@@ -1656,6 +1663,8 @@ ProgrameUpstreamBridgeForRom (
 {\r
   PCI_IO_DEVICE     *Parent;\r
   PCI_RESOURCE_NODE Node;\r
+  UINT64            Base;\r
+  UINT64            Length;\r
   //\r
   // For root bridge, just return.\r
   //\r
@@ -1667,7 +1676,6 @@ ProgrameUpstreamBridgeForRom (
     }\r
 \r
     Node.PciDev     = Parent;\r
-    Node.Length     = PciDevice->RomSize;\r
     Node.Alignment  = 0;\r
     Node.Bar        = PPB_MEM32_RANGE;\r
     Node.ResType    = PciBarTypeMem32;\r
@@ -1677,10 +1685,33 @@ ProgrameUpstreamBridgeForRom (
     // Program PPB to only open a single <= 16MB apperture\r
     //\r
     if (Enable) {\r
+      //\r
+      // Save the original PPB_MEM32_RANGE BAR.\r
+      // The values will be changed by ProgramPpbApperture().\r
+      //\r
+      Base   = Parent->PciBar[Node.Bar].BaseAddress;\r
+      Length = Parent->PciBar[Node.Bar].Length;\r
+\r
+      //\r
+      // Only cover MMIO for Option ROM.\r
+      //\r
+      Node.Length     = PciDevice->RomSize;\r
       ProgramPpbApperture (OptionRomBase, &Node);\r
+\r
+      //\r
+      // Restore the original PPB_MEM32_RANGE BAR.\r
+      // So the MEM32 RANGE BAR register can be restored when disable the decoding.\r
+      //\r
+      Parent->PciBar[Node.Bar].BaseAddress = Base;\r
+      Parent->PciBar[Node.Bar].Length      = Length;\r
+\r
       PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     } else {\r
-      InitializePpb (Parent);\r
+      //\r
+      // Cover 32bit MMIO for devices below the bridge.\r
+      //\r
+      Node.Length     = Parent->PciBar[Node.Bar].Length;\r
+      ProgramPpbApperture (Parent->PciBar[Node.Bar].BaseAddress, &Node);\r
       PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     }\r
 \r