IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed70371555d57fdde66aef9eda8515df3..7dd89c531a264b793d02c48e9b7dc72284c75cc2 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)\r
 ASM_PFX(LoadMicrocodeDefault):\r
    ; Inputs:\r
-   ;   rsp -> LoadMicrocodeParams pointer\r
+   ;   rcx -> LoadMicrocodeParams pointer\r
    ; Register Usage:\r
    ;   rsp  Preserved\r
    ;   All others destroyed\r
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 \r
    cmp    rsp, 0\r
    jz     ParamError\r
-   mov    eax, dword [rsp + 8]    ; Parameter pointer\r
-   cmp    eax, 0\r
+   cmp    rcx, 0\r
    jz     ParamError\r
-   mov    esp, eax\r
+   mov    rsp, rcx\r
 \r
    ; skip loading Microcode if the MicrocodeCodeSize is zero\r
    ; and report error if size is less than 2k\r
@@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
    jne    ParamError\r
 \r
    ; UPD structure is compliant with FSP spec 2.4\r
-   mov    eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
-   cmp    eax, 0\r
+   mov    rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+   cmp    rax, 0\r
    jz     Exit2\r
-   cmp    eax, 0800h\r
+   cmp    rax, 0800h\r
    jl     ParamError\r
 \r
-   mov    esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
-   cmp    esi, 0\r
+   mov    rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+   cmp    rsi, 0\r
    jnz    CheckMainHeader\r
 \r
 ParamError:\r
@@ -256,7 +255,8 @@ CheckAddress:
    ; UPD structure is compliant with FSP spec 2.4\r
    ; Is automatic size detection ?\r
    mov   rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
-   cmp   rax, 0ffffffffffffffffh\r
+   mov   rcx, 0ffffffffffffffffh\r
+   cmp   rax, rcx\r
    jz    LoadMicrocodeDefault4\r
 \r
    ; Address >= microcode region address + microcode region size?\r
@@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
   ;\r
   ; Save parameter pointer in rdx\r
   ;\r
-  mov       rdx, qword [rsp + 8]\r
-\r
+  mov       rdx, rcx\r
   ;\r
   ; Enable FSP STACK\r
   ;\r
@@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
   ;\r
   ENABLE_SSE\r
   ENABLE_AVX\r
-\r
+  ;\r
+  ; Save Input Parameter in YMM10\r
+  ;\r
+  SAVE_RCX\r
   ;\r
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6\r
   ;\r
@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
   ;\r
   ; Check Parameter\r
   ;\r
-  mov       rax, qword [rsp + 8]\r
-  cmp       rax, 0\r
-  mov       rax, 08000000000000002h\r
+  cmp       rcx, 0\r
+  mov       rcx, 08000000000000002h\r
   jz        TempRamInitExit\r
 \r
   ;\r
@@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
   jnz       TempRamInitExit\r
 \r
   ; Load microcode\r
-  LOAD_RSP\r
+  LOAD_RCX\r
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)\r
   SAVE_UCODE_STATUS rax             ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits).\r
   ; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot.\r
 \r
   ; Call Sec CAR Init\r
-  LOAD_RSP\r
+  LOAD_RCX\r
   CALL_YMM  ASM_PFX(SecCarInit)\r
   cmp       rax, 0\r
   jnz       TempRamInitExit\r
 \r
-  LOAD_RSP\r
+  LOAD_RCX\r
   CALL_YMM  ASM_PFX(EstablishStackFsp)\r
   cmp       rax, 0\r
   jnz       TempRamInitExit\r

diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d4924ae32af9a98e04c553c9cd59891..38c807a311cb3a8811cab1f5acfd4ffd731bfd01 100644 (file)
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
             LXMMN   xmm5, %1, 1\r
             %endmacro\r
 \r
+;\r
+; Upper half of YMM10 to save/restore RCX\r
+;\r
+;\r
+; Save RCX to YMM10[128:191]\r
+; Modified: XMM5 and YMM10\r
+;\r
+\r
+%macro SAVE_RCX     0\r
+            LYMMN   ymm10, xmm5, 1\r
+            SXMMN   xmm5, 0, rcx\r
+            SYMMN   ymm10, 1, xmm5\r
+            %endmacro\r
+\r
+;\r
+; Restore RCX from YMM10[128:191]\r
+; Modified: XMM5 and RCX\r
+;\r
+\r
+%macro LOAD_RCX     0\r
+            LYMMN   ymm10, xmm5, 1\r
+            movq    rcx,  xmm5\r
+            %endmacro\r
+\r
 ;\r
 ; YMM7[128:191] for calling stack\r
 ; arg 1:Entry\r
@@ -231,6 +255,7 @@ NextAddress:
             ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
             ; whether the processor supports SSE instruction.\r
             ;\r
+            mov     r10, rcx\r
             mov     rax, 1\r
             cpuid\r
             bt      rdx, 25\r
@@ -241,6 +266,7 @@ NextAddress:
             ;\r
             bt      ecx, 19\r
             jnc     SseError\r
+            mov     rcx,  r10\r
 \r
             ;\r
             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
@@ -258,6 +284,7 @@ NextAddress:
             %endmacro\r
 \r
 %macro ENABLE_AVX   0\r
+            mov     r10, rcx\r
             mov     eax, 1\r
             cpuid\r
             and     ecx, 10000000h\r
@@ -280,5 +307,6 @@ EnableAvx:
             xgetbv                 ; result in edx:eax\r
             or      eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state\r
             xsetbv\r
+            mov     rcx, r10\r
             %endmacro\r
 \r