ArmPlatformPkg/ArmJuno: fix Juno PIO host bridge mapping

The Juno PIO mapping is 8M, so it should be using a 32-bit
PIO address translation. Further, PIO addresses should start
at 0 and be translated to/from the ARM MMIO region.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c
index 06de6d5d9a5b9c7c3d35d4551c97a077c62c9779..d5499033092d19ac1dbebaa98c901b5c934f5792 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c
@@ -72,7 +72,9 @@ HWPciRbInit (
 \r
   PCI_TRACE ("PCIe Setting up Address Translation");\r
 \r
-  PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);\r
+  // The Juno PIO window is 8M, so we need full 32-bit PIO decoding.\r
+  PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 |\r
+                         PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);\r
 \r
   // Setup the PCI Configuration Registers\r
   // Offset 0a: SubClass       04 PCI-PCI Bridge\r
@@ -107,8 +109,9 @@ HWPciRbInit (
   SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF);\r
   TranslationTable += PCI_ATR_ENTRY_SIZE;\r
 \r
-  // PCI IO Support\r
-  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);\r
+  // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0\r
+  // AKA, PIO addresses used by endpoints are generally in the range of 0-64K.\r
+  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);\r
   TranslationTable += PCI_ATR_ENTRY_SIZE;\r
 \r
   // PCI MEM32 Support\r