ArmVirtualizationPkg/PciHostBridgeDxe: IO space is emulated with MMIO

There is no IO space on ARM, and there are no special instructions that
access it. QEMU emulates the IO space for PCI devices with a special MMIO
range. We're ready to use it at this point, we just have to switch the
Io(Read|Write)(8|16|32) primitives to their MMIO counterparts, because in
"MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", the IO primitives
correctly ASSERT (FALSE).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16900 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c
index 85048b2f7417fd399552bb83cf3e47f3a7750dd8..ea895e8d68eb033b521400cd378d28ab5fe152ff 100644 (file)
--- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -1008,13 +1008,13 @@ RootBridgeIoIoRW (
     if (Write) {\r
       switch (OperationWidth) {\r
         case EfiPciWidthUint8:\r
-          IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
+          MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
           break;\r
         case EfiPciWidthUint16:\r
-          IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
+          MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
           break;\r
         case EfiPciWidthUint32:\r
-          IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
+          MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
           break;\r
         default:\r
           //\r
@@ -1027,13 +1027,13 @@ RootBridgeIoIoRW (
     } else {\r
       switch (OperationWidth) {\r
         case EfiPciWidthUint8:\r
-          *Uint8Buffer = IoRead8 ((UINTN)Address);\r
+          *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
           break;\r
         case EfiPciWidthUint16:\r
-          *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);\r
+          *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
           break;\r
         case EfiPciWidthUint32:\r
-          *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);\r
+          *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
           break;\r
         default:\r
           //\r