MdePkg BaseLib: Convert Ia32/EnableCache.asm to NASM

The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/EnableCache.asm to Ia32/EnableCache.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3062b8bbe990bf0ee4bc6f08a770854087161c55..61b49a68c8decc5151f5660a1c2339fed87092f6 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -344,6 +344,7 @@
   Ia32/Thunk16.asm | INTEL\r
   Ia32/EnablePaging64.nasm| INTEL\r
   Ia32/EnablePaging64.asm | INTEL\r
+  Ia32/EnableCache.nasm| INTEL\r
   Ia32/EnableCache.asm | INTEL\r
   Ia32/DisableCache.asm | INTEL\r
   Ia32/RdRand.nasm| INTEL\r
@@ -395,6 +396,7 @@
   Ia32/RShiftU64.S | GCC \r
   Ia32/LShiftU64.nasm| GCC\r
   Ia32/LShiftU64.S | GCC \r
+  Ia32/EnableCache.nasm| GCC\r
   Ia32/EnableCache.S | GCC\r
   Ia32/DisableCache.S | GCC\r
   Ia32/RdRand.nasm| GCC\r

diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm b/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm
new file mode 100644 (file)
index 0000000..de61a05
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm
@@ -0,0 +1,42 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   EnableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear\r
+;  the NW bit of CR0 to 0\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmEnableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmEnableCache)\r
+ASM_PFX(AsmEnableCache):\r
+    wbinvd\r
+    mov     eax, cr0\r
+    btr     eax, 29\r
+    btr     eax, 30\r
+    mov     cr0, eax\r
+    ret\r
+\r