UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST value

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

diff --git a/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
index 00e5f58758603f619534cc73aca64201d0d41562..7e7f405b2efaf7336ad540e6a5f00ec9d737f911 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -37,10 +37,9 @@ ASM_PFX(RendezvousFunnelProc):
 RendezvousFunnelProcStart:\r
 ; At this point CS = 0x(vv00) and ip= 0x0.\r
 ; Save BIST information to ebp firstly\r
-BITS 16\r
 \r
-    mov        eax, 1234h\r
-    mov        ebp, eax                        ; save BIST information\r
+BITS 16\r
+    mov        ebp, eax                        ; Save BIST information\r
 \r
     mov        ax, cs\r
     mov        ds, ax\r