UefiCpuPkg: Replace Opcode with the corresponding instructions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)
Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
index 66f8857fc0c873228f3d5eac1346850cb8b0683b..a894ff53ad3f5bba48988c898097a10685baa98e 100644 (file)
--- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
+++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------\r
 ;*\r
-;*   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+;*   Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ;*   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;*\r
 ;*    CpuAsm.nasm\r
@@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector):
     push    rcx\r
     lea     rax, [setCodeSelectorLongJump]\r
     push    rax\r
-    o64 retf\r
+    retfq\r
 setCodeSelectorLongJump:\r
     ret\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
index 58d53128996e13f954f1590738c20218b217d84c..3fe9aed1e8485e2fc8e9af5a9682d864c3d5c3c6 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -32,12 +32,13 @@ ALIGN   8
 ; exception handler stub table\r
 ;\r
 AsmIdtVectorBegin:\r
+%assign Vector 0\r
 %rep  32\r
-    db      0x6a        ; push  #VectorNum\r
-    db      ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum\r
+    push    byte %[Vector];\r
     push    eax\r
     mov     eax, ASM_PFX(CommonInterruptEntry)\r
     jmp     eax\r
+%assign Vector Vector+1\r
 %endrep\r
 AsmIdtVectorEnd:\r
 \r
@@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack:
     test    edx, BIT24  ; Test for FXSAVE/FXRESTOR support.\r
                         ; edx still contains result from CPUID above\r
     jz      .3\r
-    db      0xf, 0xae, 0x7 ;fxsave [edi]\r
+    fxsave  [edi]\r
 .3:\r
 \r
 ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
@@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack:
                         ; are supported\r
     test    edx, BIT24  ; Test for FXSAVE/FXRESTOR support\r
     jz      .4\r
-    db      0xf, 0xae, 0xe ; fxrstor [esi]\r
+    fxrstor [esi]\r
 .4:\r
     add     esp, 512\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
index dd3f74d2aa8c00323ef07c1404803b7abc0066c1..b63cfeac6d323f65e6acf49b2a18ffe0a7c23870 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -79,8 +79,7 @@ AsmExceptionEntryBegin:
 DoIret%[Vector]:\r
     iretd\r
 ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):\r
-    db      0x6a        ; push  #VectorNum\r
-    db      %[Vector]\r
+    push    byte %[Vector]\r
     mov     eax, ASM_PFX(CommonTaskSwtichEntryPoint)\r
     call    eax\r
     mov     esp, eax    ; Restore stack top\r
@@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
     clts\r
     sub     esp, 512\r
     mov     edi, esp\r
-    db      0xf, 0xae, 0x7 ;fxsave [edi]\r
+    fxsave  [edi]\r
 .3:\r
 \r
 ;; UINT32  ExceptionData;\r
@@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
     test    edx, BIT24      ; Test for FXSAVE/FXRESTOR support\r
     jz      .4\r
     mov     esi, esp\r
-    db      0xf, 0xae, 0xe  ; fxrstor [esi]\r
+    fxrstor [esi]\r
 .4:\r
     add     esp, 512\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 2a5545ecfd41ee9e97893a67ec1c6671978c20ab..9a806d1f8644226a9852152bb9a1e3386fdea216 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -32,12 +32,13 @@ SECTION .text
 ALIGN   8\r
 \r
 AsmIdtVectorBegin:\r
+%assign Vector 0\r
 %rep  32\r
-    db      0x6a        ; push  #VectorNum\r
-    db      ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum\r
+    push    byte %[Vector]\r
     push    rax\r
     mov     rax, ASM_PFX(CommonInterruptEntry)\r
     jmp     rax\r
+%assign Vector Vector+1\r
 %endrep\r
 AsmIdtVectorEnd:\r
 \r
@@ -257,7 +258,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;\r
     sub rsp, 512\r
     mov rdi, rsp\r
-    db 0xf, 0xae, 0x7 ;fxsave [rdi]\r
+    fxsave [rdi]\r
 \r
 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
     cld\r
@@ -284,7 +285,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;\r
 \r
     mov rsi, rsp\r
-    db 0xf, 0xae, 0xE ; fxrstor [rsi]\r
+    fxrstor [rsi]\r
     add rsp, 512\r
 \r
 ;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
@@ -371,8 +372,7 @@ DoReturn:
     push    qword [rax + 0x18]       ; save EFLAGS in new location\r
     mov     rax, [rax]        ; restore rax\r
     popfq                     ; restore EFLAGS\r
-    DB      0x48               ; prefix to composite "retq" with next "retf"\r
-    retf                      ; far return\r
+    retfq\r
 DoIret:\r
     iretq\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
index 84a12ddb88d7dafd02c833c6d81c806b3ff90124..9c72fa5815fed90535d3405bc7df4e500d99ecc6 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -54,12 +54,13 @@ SECTION .text
 ALIGN   8\r
 \r
 AsmIdtVectorBegin:\r
+%assign Vector 0\r
 %rep  32\r
-    db      0x6a        ; push  #VectorNum\r
-    db      ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum\r
+    push    byte %[Vector]\r
     push    rax\r
     mov     rax, strict qword 0 ;    mov     rax, ASM_PFX(CommonInterruptEntry)\r
     jmp     rax\r
+%assign Vector Vector+1\r
 %endrep\r
 AsmIdtVectorEnd:\r
 \r
@@ -280,7 +281,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;\r
     sub rsp, 512\r
     mov rdi, rsp\r
-    db 0xf, 0xae, 0x7 ;fxsave [rdi]\r
+    fxsave [rdi]\r
 \r
 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
     cld\r
@@ -335,15 +336,15 @@ DrFinish:
     jz      CetDone\r
                                 ; SSP should be 0xFC0 at this point\r
     mov     rax, 0x04           ; advance past cs:lip:prevssp;supervisor shadow stack token\r
-    INCSSP_RAX                  ; After this SSP should be 0xFE0\r
-    SAVEPREVSSP                 ; now the shadow stack restore token will be created at 0xFB8\r
-    READSSP_RAX                 ; Read new SSP, SSP should be 0xFE8\r
+    incsspq rax                 ; After this SSP should be 0xFE0\r
+    saveprevssp                 ; now the shadow stack restore token will be created at 0xFB8\r
+    rdsspq  rax                 ; Read new SSP, SSP should be 0xFE8\r
     sub     rax, 0x10\r
-    CLRSSBSY_RAX                ; Clear token at 0xFD8, SSP should be 0 after this\r
+    clrssbsy [rax]              ; Clear token at 0xFD8, SSP should be 0 after this\r
     sub     rax, 0x20\r
-    RSTORSSP_RAX                ; Restore to token at 0xFB8, new SSP will be 0xFB8\r
+    rstorssp [rax]              ; Restore to token at 0xFB8, new SSP will be 0xFB8\r
     mov     rax, 0x01           ; Pop off the new save token created\r
-    INCSSP_RAX                  ; SSP should be 0xFC0 now\r
+    incsspq rax                 ; SSP should be 0xFC0 now\r
 CetDone:\r
 \r
     cli\r
@@ -353,7 +354,7 @@ CetDone:
 ;; FX_SAVE_STATE_X64 FxSaveState;\r
 \r
     mov rsi, rsp\r
-    db 0xf, 0xae, 0xE ; fxrstor [rsi]\r
+    fxrstor [rsi]\r
     add rsp, 512\r
 \r
 ;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
@@ -440,8 +441,7 @@ DoReturn:
     push    qword [rax + 0x18]       ; save EFLAGS in new location\r
     mov     rax, [rax]        ; restore rax\r
     popfq                     ; restore EFLAGS\r
-    DB      0x48                ; prefix to composite "retq" with next "retf"\r
-    retf                        ; far return\r
+    retfq\r
 DoIret:\r
     iretq\r
 \r

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index f7f2937fafadd6f4c192c671f5a446039a93e51f..f1422fd30accd69a968e9586ec2f9b8a25393ae5 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -345,7 +345,7 @@ BITS 64
     ;\r
     ; Far return into 32-bit mode\r
     ;\r
-o64 retf\r
+    retfq\r
 \r
 BITS 32\r
 CompatMode:\r
@@ -507,7 +507,7 @@ NoSevEs:
     ;\r
     ; Far return into 32-bit mode\r
     ;\r
-o64 retf\r
+    retfq\r
 \r
 BITS 32\r
 PmEntry:\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
index 0919d6d05fe6324ff209f487cd6a95d61c27d61e..9d66b9c5dadd90c8d47bf5749babc8f94ac0d133 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ;-------------------------------------------------------------------------------\r
@@ -13,7 +13,7 @@ ASM_PFX(DisableCet):
 \r
     ; Skip the pushed data for call\r
     mov     eax, 1\r
-    INCSSP_EAX\r
+    incsspd eax\r
 \r
     mov     eax, cr4\r
     btr     eax, 23                      ; clear CET\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 167f5e14dbd4c822e7b330aff77c49d694bb1523..19de5f614e875fddfe18f4d9482032a9b2dbc59e 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
@@ -252,7 +252,7 @@ CetInterruptDone:
     mov     eax, 0x668 | CR4_CET\r
     mov     cr4, eax\r
 \r
-    SETSSBSY\r
+    setssbsy\r
 \r
 CetDone:\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
index 3240f9d974d3bfa94d17be75510c22b51ab226ef..8bbdbb31cc931a0b46d4cc3ff44bc6207dff2005 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ;-------------------------------------------------------------------------------\r
@@ -14,7 +14,7 @@ ASM_PFX(DisableCet):
 \r
     ; Skip the pushed data for call\r
     mov     rax, 1\r
-    INCSSP_RAX\r
+    incsspq rax\r
 \r
     mov     rax, cr4\r
     btr     eax, 23                      ; clear CET\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 0e154e5db9490640a809808bb2506065f7e4d1be..d302ca8d018fbf7974cd3822ea8518c4d0c84123 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
@@ -279,7 +279,7 @@ CetInterruptDone:
     mov     eax, 0x668 | CR4_CET\r
     mov     cr4, rax\r
 \r
-    SETSSBSY\r
+    setssbsy\r
 \r
 CetDone:\r
 \r