ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailable

Even if the CPU id registers indicate hardware support for the
System Register interface to the GIC, higher exception levels
may disable that interface and only allow access through MMIO.

So move the enabling of the SRE bit to the GIC version detection
routine: if we trigger an exception, we would have anyway at a
later stage, so the net effect is the same. However, if setting
the bit doesn't stick, it means we can switch to MMIO and proceed
normally otherwise.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
index 5a7837f43d9412a46e0e8e446d38b2ecdf45f914..9da69b2131e38326d766fbe4e4f8119739c34e11 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
+++ b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
@@ -15,6 +15,8 @@
 #include <Library/ArmLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
+#include "GicV3/ArmGicV3Lib.h"\r
+\r
 ARM_GIC_ARCH_REVISION\r
 EFIAPI\r
 ArmGicGetSupportedArchRevision (\r
@@ -28,7 +30,17 @@ ArmGicGetSupportedArchRevision (
   // driver requires SRE. If only Memory mapped access is available we try to\r
   // drive the GIC as a v2.\r
   if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r
-    return ARM_GIC_ARCH_REVISION_3;\r
+    // Make sure System Register access is enabled (SRE). This depends on the\r
+    // higher privilege level giving us permission, otherwise we will either\r
+    // cause an exception here, or the write doesn't stick in which case we need\r
+    // to fall back to the GICv2 MMIO interface.\r
+    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
+    // at the same exception level.\r
+    // It is the OS responsibility to set this bit.\r
+    ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);\r
+    if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {\r
+      return ARM_GIC_ARCH_REVISION_3;\r
+    }\r
   }\r
 \r
   return ARM_GIC_ARCH_REVISION_2;\r

diff --git a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
index 668858f79a3df9cc1e296e4ef93beba7d2b4be4f..f360a405833d85971b0ddee22ea2ddeb3fce4df1 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
+++ b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
@@ -15,6 +15,8 @@
 #include <Library/ArmLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
+#include "GicV3/ArmGicV3Lib.h"\r
+\r
 ARM_GIC_ARCH_REVISION\r
 EFIAPI\r
 ArmGicGetSupportedArchRevision (\r
@@ -28,7 +30,17 @@ ArmGicGetSupportedArchRevision (
   // driver requires SRE. If only Memory mapped access is available we try to\r
   // drive the GIC as a v2.\r
   if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
-    return ARM_GIC_ARCH_REVISION_3;\r
+    // Make sure System Register access is enabled (SRE). This depends on the\r
+    // higher privilege level giving us permission, otherwise we will either\r
+    // cause an exception here, or the write doesn't stick in which case we need\r
+    // to fall back to the GICv2 MMIO interface.\r
+    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
+    // at the same exception level.\r
+    // It is the OS responsibility to set this bit.\r
+    ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);\r
+    if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {\r
+      return ARM_GIC_ARCH_REVISION_3;\r
+    }\r
   }\r
 \r
   return ARM_GIC_ARCH_REVISION_2;\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 8042f718f5b092e86bccec006f7e6a7eae63c2f3..f756d308038617cbf659137f942b8abcafef806d 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -281,14 +281,6 @@ GicV3DxeInitialize (
     }\r
   }\r
 \r
-  // Make sure System Register access is enabled (SRE). This depends on the\r
-  // lower levels giving us permission, otherwise we will cause an exception\r
-  // here.\r
-  // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started at the\r
-  // same exception level.\r
-  // It is the OS responsibility to set this bit.\r
-  ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);\r
-\r
   // Set binary point reg to 0x7 (no preemption)\r
   ArmGicV3SetBinaryPointer (0x7);\r
 \r