ArmPkg/CpuDxe: Fixed some typo issues in the AArch64 exception code

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15710 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
index 72111d1892e1f834fb1c9346df90954e9e3be509..2682f4fe7515ee67aaf623f84cfe7c1c8de31a80 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
@@ -90,8 +90,8 @@
   UINT64  ELR;    0x300   // Exception Link Register\r
   UINT64  SPSR;   0x308   // Saved Processor Status Register\r
   UINT64  FPSR;   0x310   // Floating Point Status Register\r
-  UINT64  ESR;    0x318   // EL1 Fault Address Register\r
-  UINT64  FAR;    0x320   // EL1 Exception syndrome register\r
+  UINT64  ESR;    0x318   // Exception syndrome register\r
+  UINT64  FAR;    0x320   // Fault Address Register\r
   UINT64  Padding;0x328   // Required for stack alignment\r
 */\r
 \r
@@ -127,7 +127,7 @@ GCC_ASM_EXPORT(CommonCExceptionHandler)
         REG_PAIR (x28, x29, 0x0e0, GP_CONTEXT_SIZE);    \\r
         REG_ONE  (x30,      0x0f0, GP_CONTEXT_SIZE);\r
 \r
-// In order to save the SP we need to put it somwhere else first.\r
+// In order to save the SP we need to put it somewhere else first.\r
 // STR only works with XZR/WZR directly\r
 #define SAVE_SP \\r
         add x1, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE); \\r
@@ -252,7 +252,7 @@ ASM_PFX(SynchronousExceptionEntry):
   // This does not save r31(SP) as it is special. We do that later.\r
   ALL_GP_REGS\r
 \r
-  // Record the tipe of exception that occured.\r
+  // Record the type of exception that occurred.\r
   mov       x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
 \r
   // Jump to our general handler to deal with all the common parts and process the exception.\r
@@ -298,8 +298,8 @@ ASM_PFX(ExceptionHandlersEnd):
 //\r
 ASM_PFX(AsmCommonExceptionEntry):\r
   /* NOTE:\r
-     We have to break up the save code because the immidiate value to be used\r
-     with the SP is to big to do it all in one step so we need to shuffle the SP\r
+     We have to break up the save code because the immediate value to be used\r
+     with the SP is too big to do it all in one step so we need to shuffle the SP\r
      along as we go. (we only have 9bits of immediate to work with) */\r
 \r
   // Save the current Stack pointer before we start modifying it.\r
@@ -317,8 +317,8 @@ ASM_PFX(AsmCommonExceptionEntry):
 2:mrs      x1, elr_el2   // Exception Link Register\r
   mrs      x2, spsr_el2  // Saved Processor Status Register 32bit\r
   mrs      x3, fpsr      // Floating point Status Register  32bit\r
-  mrs      x4, esr_el2   // EL1 Exception syndrome register 32bit\r
-  mrs      x5, far_el2   // EL1 Fault Address Register\r
+  mrs      x4, esr_el2   // EL2 Exception syndrome register 32bit\r
+  mrs      x5, far_el2   // EL2 Fault Address Register\r
 \r
   // Adjust SP to save next set\r
 3:add      sp, sp, #FP_CONTEXT_SIZE\r
@@ -356,7 +356,6 @@ ASM_PFX(AsmCommonExceptionEntry):
 #undef REG_PAIR\r
 #undef REG_ONE\r
 #define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE)    ldp  REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-\r
 #define REG_ONE(REG1, OFFSET, CONTEXT_SIZE)           ldur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]\r
 \r
   // Adjust SP to pop system registers\r
@@ -373,8 +372,8 @@ ASM_PFX(AsmCommonExceptionEntry):
 2:msr      elr_el2, x1   // Exception Link Register\r
   msr      spsr_el2,x2   // Saved Processor Status Register 32bit\r
   msr      fpsr, x3      // Floating point Status Register  32bit\r
-  msr      esr_el2, x4   // EL1 Exception syndrome register 32bit\r
-  msr      far_el2, x5   // EL1 Fault Address Register\r
+  msr      esr_el2, x4   // EL2 Exception syndrome register 32bit\r
+  msr      far_el2, x5   // EL2 Fault Address Register\r
 \r
 3:// pop all regs and return from exception.\r
   sub     sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r