"!!!! IA32 Exception Type - %08x !!!!\n",\r
InterruptType\r
));\r
- if (mErrorCodeFlag & (1 << InterruptType)) {\r
+ if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {\r
DEBUG ((\r
EFI_D_ERROR,\r
"ExceptionData - %08x\n",\r
"!!!! X64 Exception Type - %016lx !!!!\n",\r
(UINT64)InterruptType\r
));\r
- if (mErrorCodeFlag & (1 << InterruptType)) {\r
+ if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {\r
DEBUG ((\r
EFI_D_ERROR,\r
"ExceptionData - %016lx\n",\r
}\r
\r
/**\r
- Gets GCD Mem Space type from MTRR Type\r
+ Gets GCD Mem Space type from MTRR Type.\r
\r
- This function gets GCD Mem Space type from MTRR Type\r
+ This function gets GCD Mem Space type from MTRR Type.\r
\r
- @param MtrrAttribute MTRR memory type\r
+ @param MtrrAttributes MTRR memory type\r
\r
@return GCD Mem Space type\r
\r
Initialize Interrupt Descriptor Table for interrupt handling.\r
\r
**/\r
-STATIC\r
VOID\r
InitInterruptDescriptorTable (\r
VOID\r
/** @file\r
CPU DXE Module.\r
\r
- Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
-#ifndef _CPU_DXE_H\r
-#define _CPU_DXE_H\r
+#ifndef _CPU_DXE_H_\r
+#define _CPU_DXE_H_\r
\r
#include <PiDxe.h>\r
\r
)\r
\r
\r
-//\r
-// Function declarations\r
-//\r
+/**\r
+ Flush CPU data cache. If the instruction cache is fully coherent\r
+ with all DMA operations then function can just return EFI_SUCCESS.\r
+\r
+ @param This Protocol instance structure\r
+ @param Start Physical address to start flushing from.\r
+ @param Length Number of bytes to flush. Round up to chipset\r
+ granularity.\r
+ @param FlushType Specifies the type of flush operation to perform.\r
+\r
+ @retval EFI_SUCCESS If cache was flushed\r
+ @retval EFI_UNSUPPORTED If flush type is not supported.\r
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
IN EFI_CPU_FLUSH_TYPE FlushType\r
);\r
\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+ @param This Protocol instance structure\r
+\r
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU\r
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+ @param This Protocol instance structure\r
+\r
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
+/**\r
+ Return the state of interrupts.\r
+\r
+ @param This Protocol instance structure\r
+ @param State Pointer to the CPU's current interrupt state\r
+\r
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
+ @retval EFI_INVALID_PARAMETER State is NULL.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
OUT BOOLEAN *State\r
);\r
\r
+/**\r
+ Generates an INIT to the CPU.\r
+\r
+ @param This Protocol instance structure\r
+ @param InitType Type of CPU INIT to perform\r
+\r
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
+ seen.\r
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.\r
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
IN EFI_CPU_INIT_TYPE InitType\r
);\r
\r
+/**\r
+ Registers a function to be called from the CPU interrupt handler.\r
+\r
+ @param This Protocol instance structure\r
+ @param InterruptType Defines which interrupt to hook. IA-32\r
+ valid range is 0x00 through 0xFF\r
+ @param InterruptHandler A pointer to a function of type\r
+ EFI_CPU_INTERRUPT_HANDLER that is called\r
+ when a processor interrupt occurs. A null\r
+ pointer is an error condition.\r
+\r
+ @retval EFI_SUCCESS If handler installed or uninstalled.\r
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
+ for InterruptType was previously installed.\r
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
+ InterruptType was not previously installed.\r
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
+ is not supported.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
+/**\r
+ Returns a timer value from one of the CPU's internal timers. There is no\r
+ inherent time interval between ticks but is a function of the CPU frequency.\r
+\r
+ @param This - Protocol instance structure.\r
+ @param TimerIndex - Specifies which CPU timer is requested.\r
+ @param TimerValue - Pointer to the returned timer value.\r
+ @param TimerPeriod - A pointer to the amount of time that passes\r
+ in femtoseconds (10-15) for each increment\r
+ of TimerValue. If TimerValue does not\r
+ increment at a predictable rate, then 0 is\r
+ returned. The amount of time that has\r
+ passed between two calls to GetTimerValue()\r
+ can be calculated with the formula\r
+ (TimerValue2 - TimerValue1) * TimerPeriod.\r
+ This parameter is optional and may be NULL.\r
+\r
+ @retval EFI_SUCCESS - If the CPU timer count was returned.\r
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
OUT UINT64 *TimerPeriod OPTIONAL\r
);\r
\r
+/**\r
+ Set memory cacheability attributes for given range of memeory.\r
+\r
+ @param This Protocol instance structure\r
+ @param BaseAddress Specifies the start address of the\r
+ memory range\r
+ @param Length Specifies the length of the memory range\r
+ @param Attributes The memory cacheability for the memory range\r
+\r
+ @retval EFI_SUCCESS If the cacheability of that memory range is\r
+ set successfully\r
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done\r
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
+ such as Length = 0\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
IN UINT64 Attributes\r
);\r
\r
+/**\r
+ Label of base address of IDT vector 0.\r
+\r
+ This is just a label of base address of IDT vector 0.\r
+\r
+**/\r
VOID\r
EFIAPI\r
AsmIdtVector00 (\r
VOID\r
);\r
\r
+/**\r
+ Initializes the pointer to the external interrupt vector table.\r
+\r
+ @param VectorTable Address of the external interrupt vector table.\r
+\r
+**/\r
VOID\r
EFIAPI\r
InitializeExternalVectorTablePtr (\r
EFI_CPU_INTERRUPT_HANDLER *VectorTable\r
);\r
\r
+/**\r
+ Initialize Global Descriptor Table.\r
+\r
+**/\r
VOID\r
InitGlobalDescriptorTable (\r
VOID\r
);\r
\r
+/**\r
+ Sets the code selector (CS).\r
+\r
+ @param Selector Value of code selector.\r
+\r
+**/\r
VOID\r
EFIAPI\r
SetCodeSelector (\r
UINT16 Selector\r
);\r
\r
+/**\r
+ Sets the data selector (DS).\r
+\r
+ @param Selector Value of data selector.\r
+\r
+**/\r
VOID\r
EFIAPI\r
SetDataSelectors (\r
C based implemention of IA32 interrupt handling only\r
requiring a minimal assembly interrupt entry point.\r
\r
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Global Descriptor Entry structures\r
//\r
\r
-typedef\r
-struct _GDT_ENTRY {\r
- UINT16 limit15_0;\r
- UINT16 base15_0;\r
- UINT8 base23_16;\r
- UINT8 type;\r
- UINT8 limit19_16_and_flags;\r
- UINT8 base31_24;\r
+typedef struct _GDT_ENTRY {\r
+ UINT16 Limit15_0;\r
+ UINT16 Base15_0;\r
+ UINT8 Base23_16;\r
+ UINT8 Type;\r
+ UINT8 Limit19_16_and_flags;\r
+ UINT8 Base31_24;\r
} GDT_ENTRY;\r
\r
typedef\r
};\r
\r
/**\r
- Initialize Global Descriptor Table\r
+ Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
+ VOID\r
)\r
{\r
GDT_ENTRIES *gdt;\r
\r
**/\r
\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/CpuIo2.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#define MAX_IO_PORT_ADDRESS 0xFFFF\r
-\r
-//\r
-// Function Prototypes\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceRead (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceWrite (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceRead (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceWrite (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
+#include "CpuIo2Dxe.h"\r
\r
//\r
// Handle for the CPU I/O 2 Protocol\r
--- /dev/null
+/** @file\r
+ Internal include file for the CPU I/O 2 Protocol.\r
+\r
+Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef _CPU_IO2_DXE_H_\r
+#define _CPU_IO2_DXE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/CpuIo2.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#define MAX_IO_PORT_ADDRESS 0xFFFF\r
+\r
+/**\r
+ Reads memory-mapped registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is responsible \r
+ for satisfying any alignment and I/O width restrictions that a PI System on a \r
+ platform might require. For example on some platforms, width requests of \r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ be handled by the driver.\r
+ \r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+ each of the Count operations that is performed.\r
+ \r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times on the same Address.\r
+ \r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times from the first element of Buffer.\r
+ \r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O or Memory operation.\r
+ @param[in] Address The base address of the I/O operation. \r
+ @param[in] Count The number of I/O operations to perform. The number of \r
+ bytes moved is Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this PI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceRead (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Writes memory-mapped registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is responsible \r
+ for satisfying any alignment and I/O width restrictions that a PI System on a \r
+ platform might require. For example on some platforms, width requests of \r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ be handled by the driver.\r
+ \r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+ each of the Count operations that is performed.\r
+ \r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times on the same Address.\r
+ \r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times from the first element of Buffer.\r
+ \r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O or Memory operation.\r
+ @param[in] Address The base address of the I/O operation. \r
+ @param[in] Count The number of I/O operations to perform. The number of \r
+ bytes moved is Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this PI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceWrite (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Reads I/O registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is responsible \r
+ for satisfying any alignment and I/O width restrictions that a PI System on a \r
+ platform might require. For example on some platforms, width requests of \r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ be handled by the driver.\r
+ \r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+ each of the Count operations that is performed.\r
+ \r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times on the same Address.\r
+ \r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times from the first element of Buffer.\r
+ \r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O or Memory operation.\r
+ @param[in] Address The base address of the I/O operation. \r
+ @param[in] Count The number of I/O operations to perform. The number of \r
+ bytes moved is Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this PI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceRead (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Write I/O registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is responsible \r
+ for satisfying any alignment and I/O width restrictions that a PI System on a \r
+ platform might require. For example on some platforms, width requests of \r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ be handled by the driver.\r
+ \r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+ each of the Count operations that is performed.\r
+ \r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times on the same Address.\r
+ \r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
+ incremented for each of the Count operations that is performed. The read or \r
+ write operation is performed Count times from the first element of Buffer.\r
+ \r
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O or Memory operation.\r
+ @param[in] Address The base address of the I/O operation. \r
+ @param[in] Count The number of I/O operations to perform. The number of \r
+ bytes moved is Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PI system.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this PI system.\r
+ \r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceWrite (\r
+ IN EFI_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+#endif\r
\r
[Sources]\r
CpuIo2Dxe.c\r
-\r
+ CpuIo2Dxe.h\r
+ \r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
\r
**/\r
\r
-#include <PiSmm.h>\r
-\r
-#include <Protocol/SmmCpuIo2.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/SmmServicesTableLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-\r
-#define MAX_IO_PORT_ADDRESS 0xFFFF\r
-\r
-//\r
-// Function Prototypes\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceRead (\r
- IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceWrite (\r
- IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceRead (\r
- IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceWrite (\r
- IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
+#include "CpuIo2Smm.h"\r
\r
//\r
// Handle for the SMM CPU I/O Protocol\r
@param[in] Address The base address of the I/O operations. The caller is \r
responsible for aligning the Address if required. \r
@param[in] Count The number of I/O operations to perform.\r
- @param[out] Buffer For read operations, the destination buffer to store \r
+ @param[in] Buffer For read operations, the destination buffer to store \r
the results. For write operations, the source buffer \r
from which to write data.\r
\r
IN EFI_HANDLE ImageHandle,\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
- {\r
+{\r
EFI_STATUS Status;\r
\r
//\r
--- /dev/null
+/** @file\r
+ Internal include file for the SMM CPU I/O Protocol.\r
+\r
+Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef _CPU_IO2_SMM_H_\r
+#define _CPU_IO2_SMM_H_\r
+\r
+#include <PiSmm.h>\r
+\r
+#include <Protocol/SmmCpuIo2.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+#define MAX_IO_PORT_ADDRESS 0xFFFF\r
+\r
+/**\r
+ Reads memory-mapped registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is \r
+ responsible for any alignment and I/O width issues that the bus, device, \r
+ platform, or type of I/O might require.\r
+\r
+ @param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is \r
+ responsible for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform.\r
+ @param[out] Buffer For read operations, the destination buffer to store \r
+ the results. For write operations, the source buffer \r
+ from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the device.\r
+ @retval EFI_UNSUPPORTED The Address is not valid for this system.\r
+ @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ lack of resources\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceRead (\r
+ IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Writes memory-mapped registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is \r
+ responsible for any alignment and I/O width issues that the bus, device, \r
+ platform, or type of I/O might require.\r
+\r
+ @param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is \r
+ responsible for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform.\r
+ @param[in] Buffer For read operations, the destination buffer to store \r
+ the results. For write operations, the source buffer \r
+ from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the device.\r
+ @retval EFI_UNSUPPORTED The Address is not valid for this system.\r
+ @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ lack of resources\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceWrite (\r
+ IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Reads I/O registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is \r
+ responsible for any alignment and I/O width issues that the bus, device, \r
+ platform, or type of I/O might require.\r
+\r
+ @param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is \r
+ responsible for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform.\r
+ @param[out] Buffer For read operations, the destination buffer to store \r
+ the results. For write operations, the source buffer \r
+ from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the device.\r
+ @retval EFI_UNSUPPORTED The Address is not valid for this system.\r
+ @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ lack of resources\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceRead (\r
+ IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Write I/O registers.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is \r
+ responsible for any alignment and I/O width issues that the bus, device, \r
+ platform, or type of I/O might require.\r
+\r
+ @param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is \r
+ responsible for aligning the Address if required. \r
+ @param[in] Count The number of I/O operations to perform.\r
+ @param[in] Buffer For read operations, the destination buffer to store \r
+ the results. For write operations, the source buffer \r
+ from which to write data.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the device.\r
+ @retval EFI_UNSUPPORTED The Address is not valid for this system.\r
+ @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ lack of resources\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceWrite (\r
+ IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+#endif\r
\r
[Sources]\r
CpuIo2Smm.c\r
+ CpuIo2Smm.h\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
**/\r
\r
-#include <PiDxe.h>\r
+#include "CpuIoPei.h"\r
\r
-#include <Ppi/CpuIo.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PeiServicesLib.h>\r
-\r
-#define MAX_IO_PORT_ADDRESS 0xFFFF\r
-\r
-//\r
-// Function Prototypes\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceRead (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceWrite (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceRead (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceWrite (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-UINT8\r
-EFIAPI\r
-CpuIoRead8 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT16\r
-EFIAPI\r
-CpuIoRead16 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-CpuIoRead32 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-CpuIoRead64 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuIoWrite8 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT8 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuIoWrite16 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT16 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuIoWrite32 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT32 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuIoWrite64 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT64 Data\r
- );\r
-\r
-UINT8\r
-EFIAPI\r
-CpuMemRead8 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT16\r
-EFIAPI\r
-CpuMemRead16 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-CpuMemRead32 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-CpuMemRead64 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuMemWrite8 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT8 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuMemWrite16 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT16 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuMemWrite32 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT32 Data\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-CpuMemWrite64 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address,\r
- IN UINT64 Data\r
- );\r
- \r
//\r
// Instance of CPU I/O PPI\r
//\r
--- /dev/null
+/** @file\r
+ Internal include file for the CPU I/O PPI.\r
+\r
+Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef _CPU_IO2_PEI_H_\r
+#define _CPU_IO2_PEI_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Ppi/CpuIo.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+\r
+#define MAX_IO_PORT_ADDRESS 0xFFFF\r
+\r
+/**\r
+ Reads memory-mapped registers.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Width The width of the access. Enumerated in bytes.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Count The number of accesses to perform.\r
+ @param[out] Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceRead (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Writes memory-mapped registers.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Width The width of the access. Enumerated in bytes.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Count The number of accesses to perform.\r
+ @param[in] Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuMemoryServiceWrite (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Reads I/O registers.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Width The width of the access. Enumerated in bytes.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Count The number of accesses to perform.\r
+ @param[out] Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceRead (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Write I/O registers.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Width The width of the access. Enumerated in bytes.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Count The number of accesses to perform.\r
+ @param[in] Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ and Count is not valid for this EFI system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuIoServiceWrite (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ 8-bit I/O read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return An 8-bit value returned from the I/O space.\r
+**/\r
+UINT8\r
+EFIAPI\r
+CpuIoRead8 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 16-bit I/O read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 16-bit value returned from the I/O space.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CpuIoRead16 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 32-bit I/O read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 32-bit value returned from the I/O space.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CpuIoRead32 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 64-bit I/O read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 64-bit value returned from the I/O space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CpuIoRead64 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 8-bit I/O write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuIoWrite8 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT8 Data\r
+ );\r
+\r
+/**\r
+ 16-bit I/O write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuIoWrite16 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT16 Data\r
+ );\r
+\r
+/**\r
+ 32-bit I/O write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuIoWrite32 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT32 Data\r
+ );\r
+\r
+/**\r
+ 64-bit I/O write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuIoWrite64 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT64 Data\r
+ );\r
+\r
+/**\r
+ 8-bit memory read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return An 8-bit value returned from the memory space.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CpuMemRead8 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 16-bit memory read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 16-bit value returned from the memory space.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CpuMemRead16 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 32-bit memory read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 32-bit value returned from the memory space.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CpuMemRead32 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 64-bit memory read operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+\r
+ @return A 64-bit value returned from the memory space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CpuMemRead64 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+/**\r
+ 8-bit memory write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuMemWrite8 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT8 Data\r
+ );\r
+\r
+/**\r
+ 16-bit memory write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuMemWrite16 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT16 Data\r
+ );\r
+\r
+/**\r
+ 32-bit memory write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuMemWrite32 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT32 Data\r
+ );\r
+\r
+/**\r
+ 64-bit memory write operations.\r
+\r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ by the PEI Foundation.\r
+ @param[in] This Pointer to local data for the interface.\r
+ @param[in] Address The physical address of the access.\r
+ @param[in] Data The data to write.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuMemWrite64 (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address,\r
+ IN UINT64 Data\r
+ );\r
+ \r
+#endif\r
\r
[Sources]\r
CpuIoPei.c\r
-\r
+ CpuIoPei.h\r
+ \r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
VOID\r
EFIAPI\r
MtrrDebugPrintAllMtrrs (\r
+ VOID\r
);\r
\r
/**\r
//\r
// This table defines the offset, base and length of the fixed MTRRs\r
//\r
-STATIC\r
FIXED_MTRR MtrrLibFixedMtrrTable[] = {\r
{\r
MTRR_LIB_IA32_MTRR_FIX64K_00000,\r
{\r
UINT64 Result;\r
\r
- if (RShiftU64 (MemoryLength, 32)) {\r
+ if (RShiftU64 (MemoryLength, 32) != 0) {\r
Result = LShiftU64 (\r
(UINT64) GetPowerOfTwo32 (\r
(UINT32) RShiftU64 (MemoryLength, 32)\r
@param VariableMtrr The array to shadow variable MTRRs content\r
\r
**/\r
-STATIC\r
VOID\r
InvalidateMtrr (\r
IN VARIABLE_MTRR *VariableMtrr\r
Index = 0;\r
VariableMtrrCount = GetVariableMtrrCount ();\r
while (Index < VariableMtrrCount) {\r
- if (VariableMtrr[Index].Valid == FALSE && VariableMtrr[Index].Used == TRUE ) {\r
+ if (!VariableMtrr[Index].Valid && VariableMtrr[Index].Used) {\r
AsmWriteMsr64 (VariableMtrr[Index].Msr, 0);\r
AsmWriteMsr64 (VariableMtrr[Index].Msr + 1, 0);\r
VariableMtrr[Index].Used = FALSE;\r
@param MtrrValidAddressMask The valid address mask for MTRR\r
\r
**/\r
-STATIC\r
VOID\r
ProgramVariableMtrr (\r
IN UINTN MtrrNumber,\r
@return The enum item in MTRR_MEMORY_CACHE_TYPE\r
\r
**/\r
-STATIC\r
MTRR_MEMORY_CACHE_TYPE\r
GetMemoryCacheTypeFromMtrrType (\r
IN UINT64 MtrrType\r
@param MtrrValidAddressMask The valid address mask for the MTRR\r
\r
**/\r
-STATIC\r
VOID\r
MtrrLibInitializeMtrrMask (\r
OUT UINT64 *MtrrValidBitsMask,\r
This function prints all MTRRs for debugging.\r
**/\r
VOID\r
+EFIAPI\r
MtrrDebugPrintAllMtrrs (\r
+ VOID\r
)\r
{\r
DEBUG_CODE (\r
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