There are many overlong lines; it's hard to work with the library like
this. Rewrap all files to 79 columns.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
This function clears memory encryption bit for the memory region specified\r
by BaseAddress and Number of pages from the current page table context.\r
\r
This function clears memory encryption bit for the memory region specified\r
by BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the memory\r
+ region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
This function sets memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
This function sets memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were set for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were set for the memory\r
+ region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
# are licensed and made available under the terms and conditions of the BSD\r
# License which accompanies this distribution. The full text of the license\r
# may be found at http://opensource.org/licenses/bsd-license.php\r
# are licensed and made available under the terms and conditions of the BSD\r
# License which accompanies this distribution. The full text of the license\r
# may be found at http://opensource.org/licenses/bsd-license.php\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR\r
+# IMPLIED.\r
LIBRARY_CLASS = MemEncryptSevLib|PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER\r
\r
#\r
LIBRARY_CLASS = MemEncryptSevLib|PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER\r
\r
#\r
-# The following information is for reference only and not required by the build tools.\r
+# The following information is for reference only and not required by the build\r
+# tools.\r
#\r
# VALID_ARCHITECTURES = IA32 X64\r
#\r
#\r
# VALID_ARCHITECTURES = IA32 X64\r
#\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD\r
- License which accompanies this distribution. The full text of the license may\r
- be found at http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
This function clears memory encryption bit for the memory region specified\r
by BaseAddress and Number of pages from the current page table context.\r
\r
This function clears memory encryption bit for the memory region specified\r
by BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3)\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current\r
+ CR3)\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the memory\r
+ region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
This function sets memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
This function sets memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3)\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current\r
+ CR3)\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were set for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were set for the memory\r
+ region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_UNSUPPORTED Clearing memory encryption attribute is not\r
supported\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD\r
- License which accompanies this distribution. The full text of the license may\r
- be found at http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD\r
- License which accompanies this distribution. The full text of the license may\r
- be found at http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
This function clears memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
This function clears memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3)\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use\r
+ current CR3)\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory\r
- region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Clearing the memory encryption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Clearing the memory encryption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
IN BOOLEAN Flush\r
)\r
{\r
IN BOOLEAN Flush\r
)\r
{\r
- return InternalMemEncryptSevSetMemoryDecrypted (Cr3BaseAddress, BaseAddress, EFI_PAGES_TO_SIZE(NumPages), Flush);\r
+ return InternalMemEncryptSevSetMemoryDecrypted (\r
+ Cr3BaseAddress,\r
+ BaseAddress,\r
+ EFI_PAGES_TO_SIZE (NumPages),\r
+ Flush\r
+ );\r
This function clears memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
This function clears memory encryption bit for the memory region specified by\r
BaseAddress and Number of pages from the current page table context.\r
\r
- @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3)\r
- @param[in] BaseAddress The physical address that is the start address\r
- of a memory region.\r
- @param[in] NumberOfPages The number of pages from start memory region.\r
+ @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use\r
+ current CR3)\r
+ @param[in] BaseAddress The physical address that is the start\r
+ address of a memory region.\r
+ @param[in] NumberOfPages The number of pages from start memory\r
+ region.\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
@param[in] Flush Flush the caches before clearing the bit\r
(mostly TRUE except MMIO addresses)\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory\r
- region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Clearing the memory encryption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Clearing the memory encryption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
IN BOOLEAN Flush\r
)\r
{\r
IN BOOLEAN Flush\r
)\r
{\r
- return InternalMemEncryptSevSetMemoryEncrypted (Cr3BaseAddress, BaseAddress, EFI_PAGES_TO_SIZE(NumPages), Flush);\r
+ return InternalMemEncryptSevSetMemoryEncrypted (\r
+ Cr3BaseAddress,\r
+ BaseAddress,\r
+ EFI_PAGES_TO_SIZE (NumPages),\r
+ Flush\r
+ );\r
\r
Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
\r
Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c\r
+ Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c\r
To reduce the potential split operation on page table, the pages reserved for\r
page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and\r
at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always\r
To reduce the potential split operation on page table, the pages reserved for\r
page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and\r
at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always\r
- initialized with number of pages greater than or equal to the given PoolPages.\r
+ initialized with number of pages greater than or equal to the given\r
+ PoolPages.\r
\r
Once the pages in the pool are used up, this method should be called again to\r
\r
Once the pages in the pool are used up, this method should be called again to\r
- reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't happen\r
- often in practice.\r
+ reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't\r
+ happen often in practice.\r
\r
@param[in] PoolPages The least page number of the pool to be created.\r
\r
\r
@param[in] PoolPages The least page number of the pool to be created.\r
\r
/**\r
Split 2M page to 4K.\r
\r
/**\r
Split 2M page to 4K.\r
\r
- @param[in] PhysicalAddress Start physical address the 2M page covered.\r
+ @param[in] PhysicalAddress Start physical address the 2M page\r
+ covered.\r
@param[in, out] PageEntry2M Pointer to 2M page entry.\r
@param[in] StackBase Stack base address.\r
@param[in] StackSize Stack size.\r
@param[in, out] PageEntry2M Pointer to 2M page entry.\r
@param[in] StackBase Stack base address.\r
@param[in] StackSize Stack size.\r
ASSERT (*PageEntry2M & AddressEncMask);\r
\r
PhysicalAddress4K = PhysicalAddress;\r
ASSERT (*PageEntry2M & AddressEncMask);\r
\r
PhysicalAddress4K = PhysicalAddress;\r
- for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {\r
+ for (IndexOfPageTableEntries = 0;\r
+ IndexOfPageTableEntries < 512;\r
+ (IndexOfPageTableEntries++,\r
+ PageTableEntry++,\r
+ PhysicalAddress4K += SIZE_4KB)) {\r
//\r
// Fill in the Page Table entries\r
//\r
PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;\r
PageTableEntry->Bits.ReadWrite = 1;\r
PageTableEntry->Bits.Present = 1;\r
//\r
// Fill in the Page Table entries\r
//\r
PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;\r
PageTableEntry->Bits.ReadWrite = 1;\r
PageTableEntry->Bits.Present = 1;\r
- if ((PhysicalAddress4K >= StackBase) && (PhysicalAddress4K < StackBase + StackSize)) {\r
+ if ((PhysicalAddress4K >= StackBase) &&\r
+ (PhysicalAddress4K < StackBase + StackSize)) {\r
//\r
// Set Nx bit for stack.\r
//\r
//\r
// Set Nx bit for stack.\r
//\r
//\r
// Fill in 2M page entry.\r
//\r
//\r
// Fill in 2M page entry.\r
//\r
- *PageEntry2M = (UINT64) (UINTN) PageTableEntry1 | IA32_PG_P | IA32_PG_RW | AddressEncMask;\r
+ *PageEntry2M = ((UINT64)(UINTN)PageTableEntry1 |\r
+ IA32_PG_P | IA32_PG_RW | AddressEncMask);\r
PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);\r
\r
//\r
PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);\r
\r
//\r
- // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which\r
- // is one of page size of the processor (2MB by default). Let's apply the\r
- // protection to them one by one.\r
+ // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE,\r
+ // which is one of page size of the processor (2MB by default). Let's apply\r
+ // the protection to them one by one.\r
//\r
while (PoolSize > 0) {\r
SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);\r
//\r
while (PoolSize > 0) {\r
SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);\r
/**\r
Split 1G page to 2M.\r
\r
/**\r
Split 1G page to 2M.\r
\r
- @param[in] PhysicalAddress Start physical address the 1G page covered.\r
+ @param[in] PhysicalAddress Start physical address the 1G page\r
+ covered.\r
@param[in, out] PageEntry1G Pointer to 1G page entry.\r
@param[in] StackBase Stack base address.\r
@param[in] StackSize Stack size.\r
@param[in, out] PageEntry1G Pointer to 1G page entry.\r
@param[in] StackBase Stack base address.\r
@param[in] StackSize Stack size.\r
//\r
// Fill in 1G page entry.\r
//\r
//\r
// Fill in 1G page entry.\r
//\r
- *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_PG_RW | AddressEncMask;\r
+ *PageEntry1G = ((UINT64)(UINTN)PageDirectoryEntry |\r
+ IA32_PG_P | IA32_PG_RW | AddressEncMask);\r
\r
PhysicalAddress2M = PhysicalAddress;\r
\r
PhysicalAddress2M = PhysicalAddress;\r
- for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {\r
- if ((PhysicalAddress2M < StackBase + StackSize) && ((PhysicalAddress2M + SIZE_2MB) > StackBase)) {\r
+ for (IndexOfPageDirectoryEntries = 0;\r
+ IndexOfPageDirectoryEntries < 512;\r
+ (IndexOfPageDirectoryEntries++,\r
+ PageDirectoryEntry++,\r
+ PhysicalAddress2M += SIZE_2MB)) {\r
+ if ((PhysicalAddress2M < StackBase + StackSize) &&\r
+ ((PhysicalAddress2M + SIZE_2MB) > StackBase)) {\r
//\r
// Need to split this 2M page that covers stack range.\r
//\r
//\r
// Need to split this 2M page that covers stack range.\r
//\r
- Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);\r
+ Split2MPageTo4K (\r
+ PhysicalAddress2M,\r
+ (UINT64 *)PageDirectoryEntry,\r
+ StackBase,\r
+ StackSize\r
+ );\r
} else {\r
//\r
// Fill in the Page Directory entries\r
} else {\r
//\r
// Fill in the Page Directory entries\r
- This function either sets or clears memory encryption bit for the memory region\r
- specified by PhysicalAddress and length from the current page table context.\r
+ This function either sets or clears memory encryption bit for the memory\r
+ region specified by PhysicalAddress and length from the current page table\r
+ context.\r
\r
The function iterates through the physicalAddress one page at a time, and set\r
or clears the memory encryption mask in the page table. If it encounters\r
\r
The function iterates through the physicalAddress one page at a time, and set\r
or clears the memory encryption mask in the page table. If it encounters\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory\r
- region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
\r
//\r
// We are going to change the memory encryption attribute from C=0 -> C=1 or\r
\r
//\r
// We are going to change the memory encryption attribute from C=0 -> C=1 or\r
- // vice versa Flush the caches to ensure that data is written into memory with\r
- // correct C-bit\r
+ // vice versa Flush the caches to ensure that data is written into memory\r
+ // with correct C-bit\r
//\r
if (CacheFlush) {\r
WriteBackInvalidateDataCacheRange((VOID*) (UINTN)PhysicalAddress, Length);\r
//\r
if (CacheFlush) {\r
WriteBackInvalidateDataCacheRange((VOID*) (UINTN)PhysicalAddress, Length);\r
- PageDirectory1GEntry = (VOID*) ((PageMapLevel4Entry->Bits.PageTableBaseAddress<<12) & ~PgTableMask);\r
+ PageDirectory1GEntry = (VOID *)(\r
+ (PageMapLevel4Entry->Bits.PageTableBaseAddress <<\r
+ 12) & ~PgTableMask\r
+ );\r
PageDirectory1GEntry += PDP_OFFSET(PhysicalAddress);\r
if (!PageDirectory1GEntry->Bits.Present) {\r
DEBUG ((\r
PageDirectory1GEntry += PDP_OFFSET(PhysicalAddress);\r
if (!PageDirectory1GEntry->Bits.Present) {\r
DEBUG ((\r
__FUNCTION__,\r
PhysicalAddress\r
));\r
__FUNCTION__,\r
PhysicalAddress\r
));\r
- Split1GPageTo2M(((UINT64)PageDirectory1GEntry->Bits.PageTableBaseAddress)<<30, (UINT64*) PageDirectory1GEntry, 0, 0);\r
+ Split1GPageTo2M (\r
+ (UINT64)PageDirectory1GEntry->Bits.PageTableBaseAddress << 30,\r
+ (UINT64 *)PageDirectory1GEntry,\r
+ 0,\r
+ 0\r
+ );\r
continue;\r
}\r
} else {\r
//\r
// Actually a PDP\r
//\r
continue;\r
}\r
} else {\r
//\r
// Actually a PDP\r
//\r
- PageUpperDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER*) PageDirectory1GEntry;\r
- PageDirectory2MEntry = (VOID*) ((PageUpperDirectoryPointerEntry->Bits.PageTableBaseAddress<<12) & ~PgTableMask);\r
+ PageUpperDirectoryPointerEntry =\r
+ (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory1GEntry;\r
+ PageDirectory2MEntry =\r
+ (VOID *)(\r
+ (PageUpperDirectoryPointerEntry->Bits.PageTableBaseAddress <<\r
+ 12) & ~PgTableMask\r
+ );\r
PageDirectory2MEntry += PDE_OFFSET(PhysicalAddress);\r
if (!PageDirectory2MEntry->Bits.Present) {\r
DEBUG ((\r
PageDirectory2MEntry += PDE_OFFSET(PhysicalAddress);\r
if (!PageDirectory2MEntry->Bits.Present) {\r
DEBUG ((\r
__FUNCTION__,\r
PhysicalAddress\r
));\r
__FUNCTION__,\r
PhysicalAddress\r
));\r
- Split2MPageTo4K (((UINT64)PageDirectory2MEntry->Bits.PageTableBaseAddress) << 21, (UINT64*) PageDirectory2MEntry, 0, 0);\r
+ Split2MPageTo4K (\r
+ (UINT64)PageDirectory2MEntry->Bits.PageTableBaseAddress << 21,\r
+ (UINT64 *)PageDirectory2MEntry,\r
+ 0,\r
+ 0\r
+ );\r
continue;\r
}\r
} else {\r
continue;\r
}\r
} else {\r
- PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER*) PageDirectory2MEntry;\r
- PageTableEntry = (VOID*) (PageDirectoryPointerEntry->Bits.PageTableBaseAddress<<12 & ~PgTableMask);\r
+ PageDirectoryPointerEntry =\r
+ (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory2MEntry;\r
+ PageTableEntry =\r
+ (VOID *)(\r
+ (PageDirectoryPointerEntry->Bits.PageTableBaseAddress <<\r
+ 12) & ~PgTableMask\r
+ );\r
PageTableEntry += PTE_OFFSET(PhysicalAddress);\r
if (!PageTableEntry->Bits.Present) {\r
DEBUG ((\r
PageTableEntry += PTE_OFFSET(PhysicalAddress);\r
if (!PageTableEntry->Bits.Present) {\r
DEBUG ((\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory\r
- region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
- return SetMemoryEncDec (Cr3BaseAddress, PhysicalAddress, Length, ClearCBit, Flush);\r
+ return SetMemoryEncDec (\r
+ Cr3BaseAddress,\r
+ PhysicalAddress,\r
+ Length,\r
+ ClearCBit,\r
+ Flush\r
+ );\r
}\r
\r
/**\r
This function sets memory encryption bit for the memory region specified by\r
PhysicalAddress and length from the current page table context.\r
\r
}\r
\r
/**\r
This function sets memory encryption bit for the memory region specified by\r
PhysicalAddress and length from the current page table context.\r
\r
- @param[in] PhysicalAddress The physical address that is the start address\r
- of a memory region.\r
+ @param[in] PhysicalAddress The physical address that is the start\r
+ address of a memory region.\r
@param[in] Length The length of memory region\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
@param[in] Length The length of memory region\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory\r
- region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
IN BOOLEAN Flush\r
)\r
{\r
IN BOOLEAN Flush\r
)\r
{\r
- return SetMemoryEncDec (Cr3BaseAddress, PhysicalAddress, Length, SetCBit, Flush);\r
+ return SetMemoryEncDec (\r
+ Cr3BaseAddress,\r
+ PhysicalAddress,\r
+ Length,\r
+ SetCBit,\r
+ Flush\r
+ );\r
\r
Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
\r
Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
+ Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
\r
typedef union {\r
struct {\r
\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
UINT64 Reserved:1; // Reserved\r
UINT64 MustBeZero:2; // Must Be Zero\r
UINT64 Available:3; // Available for use by system software\r
UINT64 Reserved:1; // Reserved\r
UINT64 MustBeZero:2; // Must Be Zero\r
UINT64 Available:3; // Available for use by system software\r
//\r
typedef union {\r
struct {\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
//\r
typedef union {\r
struct {\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1=Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
UINT64 MustBe1:1; // Must be 1\r
UINT64 MustBe1:1; // Must be 1\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:8; // Must be zero;\r
UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:8; // Must be zero;\r
UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_ENTRY;\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_ENTRY;\r
//\r
typedef union {\r
struct {\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
UINT64 MustBe1:1; // Must be 1\r
UINT64 MustBe1:1; // Must be 1\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:17; // Must be zero;\r
UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:17; // Must be zero;\r
UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
-#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
+#define PAGE_TABLE_POOL_UNIT_PAGES \\r
+ EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK \\r
(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
#define PAGE_TABLE_POOL_ALIGN_MASK \\r
(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
- This function clears memory encryption bit for the memory region specified by PhysicalAddress\r
- and length from the current page table context.\r
+ This function clears memory encryption bit for the memory region specified by\r
+ PhysicalAddress and length from the current page table context.\r
- @param[in] PhysicalAddress The physical address that is the start address of a memory region.\r
+ @param[in] PhysicalAddress The physical address that is the start\r
+ address of a memory region.\r
@param[in] Length The length of memory region\r
@param[in] Length The length of memory region\r
- @param[in] Flush Flush the caches before applying the encryption mask\r
+ @param[in] Flush Flush the caches before applying the\r
+ encryption mask\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
This function sets memory encryption bit for the memory region specified by\r
PhysicalAddress and length from the current page table context.\r
\r
This function sets memory encryption bit for the memory region specified by\r
PhysicalAddress and length from the current page table context.\r
\r
- @param[in] PhysicalAddress The physical address that is the start address\r
- of a memory region.\r
+ @param[in] PhysicalAddress The physical address that is the start\r
+ address of a memory region.\r
@param[in] Length The length of memory region\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
@param[in] Length The length of memory region\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
**/\r
RETURN_STATUS\r
EFIAPI\r
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