ArmPlatformPkg/Sec: Replaced hardcode SCR and NSACR values by PCDs to enable CPU...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12637 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index c9bf606666ae297e7ca0a8edc647ed4861ddbee2..9a3bc3a7b0956a9b86e5c52b82c3a3ce436677ef 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -101,6 +101,34 @@
   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+  \r
+  #\r
+  # ARM Security Extension\r
+  #\r
+  \r
+  # Secure Configuration Register\r
+  # - BIT0 : NS - Non Secure bit \r
+  # - BIT1 : IRQ Handler\r
+  # - BIT2 : FIQ Handler\r
+  # - BIT3 : EA - External Abort\r
+  # - BIT4 : FW - F bit writable\r
+  # - BIT5 : AW - A bit writable\r
+  # - BIT6 : nET - Not Early Termination\r
+  # - BIT7 : SCD - Secure Monitor Call Disable\r
+  # - BIT8 : HCE - Hyp Call enable\r
+  # - BIT9 : SIF - Secure Instruction Fetch\r
+  # 0x31 = NS | EA | FW\r
+  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+  \r
+  # Non Secure Access Control Register\r
+  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
+  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+  # 0xC00 = cp10 | cp11\r
+  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+  \r
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r

diff --git a/ArmPlatformPkg/Sec/Helper.S b/ArmPlatformPkg/Sec/Helper.S
index da3b0e033b53140c209b1f92e874912c7a5ea256..61491b565561c211fa588f688ba56dddcd8d93df 100644 (file)
--- a/ArmPlatformPkg/Sec/Helper.S
+++ b/ArmPlatformPkg/Sec/Helper.S
@@ -19,6 +19,7 @@ GCC_ASM_EXPORT(monitor_vector_table)
 GCC_ASM_EXPORT(return_from_exception)\r
 GCC_ASM_EXPORT(enter_monitor_mode)\r
 GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
+GCC_ASM_EXPORT(set_non_secure_mode)\r
 \r
 ASM_PFX(monitor_vector_table):\r
     ldr pc, dead\r
@@ -68,6 +69,18 @@ ASM_PFX(copy_cpsr_into_spsr):
     msr     spsr_cxsf, r0\r
     bx      lr\r
 \r
+# Set the Non Secure Mode\r
+ASM_PFX(set_non_secure_mode):\r
+    push    { r1 }\r
+    and            r0, r0, #0x1f     @ Keep only the mode bits\r
+    mrs     r1, spsr          @ Read the spsr\r
+    bic     r1, r1, #0x1f     @ Clear all mode bits\r
+    orr            r1, r1, r0\r
+    msr     spsr_cxsf, r1     @ write back spsr (may have caused a mode switch)\r
+    isb\r
+    pop     { r1 }\r
+    bx      lr                @ return (hopefully thumb-safe!)\r
+\r
 dead:\r
     b       dead\r
     \r

diff --git a/ArmPlatformPkg/Sec/Helper.asm b/ArmPlatformPkg/Sec/Helper.asm
index 43a0749138acf40392c60179ed95cf45f3be0a1c..1649df399adae8f1dbf01f0c9d80858b4dc1b45e 100644 (file)
--- a/ArmPlatformPkg/Sec/Helper.asm
+++ b/ArmPlatformPkg/Sec/Helper.asm
@@ -15,6 +15,7 @@
     EXPORT  return_from_exception\r
     EXPORT  enter_monitor_mode\r
     EXPORT  copy_cpsr_into_spsr\r
+    EXPORT  set_non_secure_mode\r
     \r
     AREA   Helper, CODE, READONLY\r
 \r
@@ -60,6 +61,18 @@ copy_cpsr_into_spsr
     msr     spsr_cxsf, r0\r
     bx      lr\r
 \r
+// Set the Non Secure Mode\r
+set_non_secure_mode\r
+    push    { r1 }\r
+    and        r0, r0, #0x1f     // Keep only the mode bits\r
+    mrs     r1, spsr          // Read the spsr\r
+    bic     r1, r1, #0x1f     // Clear all mode bits\r
+    orr            r1, r1, r0\r
+    msr     spsr_cxsf, r1     // write back spsr (may have caused a mode switch)\r
+    isb\r
+    pop     { r1 }\r
+    bx      lr                // return (hopefully thumb-safe!)\r
+\r
 dead\r
     B       dead\r
     \r

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index a40f43683a7d9f22bf83a7097add2cac92c25e6d..d9831a5c44ce671c4fd7fe792255642d07f82405 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -133,16 +133,11 @@ CEntryPoint (
     // Transfer the interrupt to Non-secure World
     ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 
-    // Write to CP15 Non-secure Access Control Register :
-    //   - Enable CP10 and CP11 accesses in NS World
-    //   - Enable Access to Preload Engine in NS World
-    //   - Enable lockable TLB entries allocation in NS world
-    //   - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
-    ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
-
-    // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
-    // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
-    ArmWriteScr (SCR_NS | SCR_FW | SCR_AW);
+    // Write to CP15 Non-secure Access Control Register
+    ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
+
+    // CP15 Secure Configuration Register
+    ArmWriteScr (PcdGet32 (PcdArmScr));
   } else {
     if (IS_PRIMARY_CORE(MpId)) {
       SerialPrint ("Trust Zone Configuration is disabled\n\r");
@@ -157,6 +152,12 @@ CEntryPoint (
   JumpAddress = PcdGet32 (PcdFvBaseAddress);
   ArmPlatformSecExtraAction (MpId, &JumpAddress);
 
+  // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
+  // By not set, the mode for Non Secure World is SVC
+  if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
+    set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
+  }
+
   return_from_exception (JumpAddress);
   //-------------------- Non Secure Mode ---------------------
 

diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index 9980c6b951ed51ab0ca396caf69803d2480b986f..f80db4a630797f4ea0e78375367ed6d32473e435 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -54,9 +54,16 @@
   gArmTokenSpaceGuid.PcdTrustzoneSupport\r
   gArmTokenSpaceGuid.PcdVFPEnabled\r
   \r
+  gArmTokenSpaceGuid.PcdArmScr\r
+  gArmTokenSpaceGuid.PcdArmNsacr\r
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition\r
+  \r
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
   gArmTokenSpaceGuid.PcdArmPrimaryCore\r
   \r
+  gArmTokenSpaceGuid.PcdSecureFvBaseAddress\r
+  gArmTokenSpaceGuid.PcdSecureFvSize\r
+  \r
   gArmTokenSpaceGuid.PcdFvBaseAddress\r
   \r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\r

diff --git a/ArmPlatformPkg/Sec/SecInternal.h b/ArmPlatformPkg/Sec/SecInternal.h
index 4d1b0f60899bae7245eefa7242304da1d10ced7a..cf9c1707d5317196443e2921c72cf3e8bb8383fb 100644 (file)
--- a/ArmPlatformPkg/Sec/SecInternal.h
+++ b/ArmPlatformPkg/Sec/SecInternal.h
@@ -58,6 +58,11 @@ copy_cpsr_into_spsr (
   VOID\r
   );\r
 \r
+VOID\r
+set_non_secure_mode (\r
+  IN ARM_PROCESSOR_MODE              Mode\r
+  );\r
+\r
 VOID\r
 SecCommonExceptionEntry (\r
   IN UINT32 Entry,\r