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c314970)
Add more CPU ID which can support SmmFeatureControl,
according to IA32 SDM.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
// Intel(R) Core(TM) Processor Family MSRs.\r
//\r
if (FamilyId == 0x06) {\r
// Intel(R) Core(TM) Processor Family MSRs.\r
//\r
if (FamilyId == 0x06) {\r
- if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
+ if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||\r
+ ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||\r
+ ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C) {\r
//\r
// Check to see if the CPU supports the SMM Code Access Check feature\r
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
//\r
// Check to see if the CPU supports the SMM Code Access Check feature\r
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r