ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM Support...

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14892 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index 3646209a81d76d3ba4c1947bf217fb70c3a631e0..e67c93f95bc1eba5927af8fadfa9e2d765fee1ac 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -4051,32 +4051,41 @@ ExplainPcieLinkCap (
   )\r
 {\r
   UINT32 PcieLinkCap;\r
-  CHAR16 *SupLinkSpeeds;\r
+  CHAR16 *MaxLinkSpeed;\r
   CHAR16 *AspmValue;\r
 \r
   PcieLinkCap = PciExpressCap->LinkCap;\r
-  switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
+  switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
     case 1:\r
-      SupLinkSpeeds = L"2.5 GT/s";\r
+      MaxLinkSpeed = L"2.5 GT/s";\r
       break;\r
     case 2:\r
-      SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
+      MaxLinkSpeed = L"5.0 GT/s";\r
+      break;\r
+    case 3:\r
+      MaxLinkSpeed = L"8.0 GT/s";\r
       break;\r
     default:\r
-      SupLinkSpeeds = L"Unknown";\r
+      MaxLinkSpeed = L"Unknown";\r
       break;\r
   }\r
   ShellPrintEx (-1, -1,\r
-    L"  Supported Link Speeds(3:0):                         %E%s supported%N\r\n",\r
-    SupLinkSpeeds\r
+    L"  Maximum Link Speed(3:0):                            %E%s%N\r\n",\r
+    MaxLinkSpeed\r
    );\r
   ShellPrintEx (-1, -1,\r
     L"  Maximum Link Width(9:4):                            %Ex%d%N\r\n",\r
     PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
    );\r
   switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+    case 0:\r
+      AspmValue = L"Not";\r
+      break;\r
     case 1:\r
-      AspmValue = L"L0s Entry";\r
+      AspmValue = L"L0s";\r
+      break;\r
+    case 2:\r
+      AspmValue = L"L1";\r
       break;\r
     case 3:\r
       AspmValue = L"L0s and L1";\r
@@ -4204,23 +4213,26 @@ ExplainPcieLinkStatus (
   )\r
 {\r
   UINT16 PcieLinkStatus;\r
-  CHAR16 *SupLinkSpeeds;\r
+  CHAR16 *CurLinkSpeed;\r
 \r
   PcieLinkStatus = PciExpressCap->LinkStatus;\r
   switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
     case 1:\r
-      SupLinkSpeeds = L"2.5 GT/s";\r
+      CurLinkSpeed = L"2.5 GT/s";\r
       break;\r
     case 2:\r
-      SupLinkSpeeds = L"5.0 GT/s";\r
+      CurLinkSpeed = L"5.0 GT/s";\r
+      break;\r
+    case 3:\r
+      CurLinkSpeed = L"8.0 GT/s";\r
       break;\r
     default:\r
-      SupLinkSpeeds = L"Reserved";\r
+      CurLinkSpeed = L"Reserved";\r
       break;\r
   }\r
   ShellPrintEx (-1, -1,\r
     L"  Current Link Speed(3:0):                            %E%s%N\r\n",\r
-    SupLinkSpeeds\r
+    CurLinkSpeed\r
    );\r
   ShellPrintEx (-1, -1,\r
     L"  Negotiated Link Width(9:4):                         %Ex%d%N\r\n",\r

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
index 04a22da52c83f140153e091ce5041aaa27f742d1..8a053ab981c7704d9cf649ae6c5fb9d5a32f94b9 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
@@ -1,6 +1,7 @@
 /** @file\r
   Header file for Pci shell Debug1 function.\r
 \r
+  Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
   Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -157,7 +158,7 @@ typedef enum {
 //\r
 // Link Capabilities Register\r
 //\r
-#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \\r
+#define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \\r
     ((PcieLinkCap) & 0x0f)\r
 #define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \\r
     (((PcieLinkCap) >> 4) & 0x3f)\r