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ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM Support...
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
c37e0f16 4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
3737ac2b 5 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
5d73d92f 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "UefiShellDebug1CommandsLib.h"\r
17#include <Protocol/PciRootBridgeIo.h>\r
18#include <Library/ShellLib.h>\r
19#include <IndustryStandard/Pci.h>\r
20#include <IndustryStandard/Acpi.h>\r
21#include "Pci.h"\r
22\r
23#define PCI_CLASS_STRING_LIMIT 54\r
24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
79PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
80\r
81//\r
82// Base class strings entries\r
83//\r
84PCI_CLASS_ENTRY gClassStringList[] = {\r
85 {\r
86 0x00,\r
87 L"Pre 2.0 device",\r
88 PCISubClass_00\r
89 },\r
90 {\r
91 0x01,\r
92 L"Mass Storage Controller",\r
93 PCISubClass_01\r
94 },\r
95 {\r
96 0x02,\r
97 L"Network Controller",\r
98 PCISubClass_02\r
99 },\r
100 {\r
101 0x03,\r
102 L"Display Controller",\r
103 PCISubClass_03\r
104 },\r
105 {\r
106 0x04,\r
107 L"Multimedia Device",\r
108 PCISubClass_04\r
109 },\r
110 {\r
111 0x05,\r
112 L"Memory Controller",\r
113 PCISubClass_05\r
114 },\r
115 {\r
116 0x06,\r
117 L"Bridge Device",\r
118 PCISubClass_06\r
119 },\r
120 {\r
121 0x07,\r
122 L"Simple Communications Controllers",\r
123 PCISubClass_07\r
124 },\r
125 {\r
126 0x08,\r
127 L"Base System Peripherals",\r
128 PCISubClass_08\r
129 },\r
130 {\r
131 0x09,\r
132 L"Input Devices",\r
133 PCISubClass_09\r
134 },\r
135 {\r
136 0x0a,\r
137 L"Docking Stations",\r
138 PCISubClass_0a\r
139 },\r
140 {\r
141 0x0b,\r
142 L"Processors",\r
143 PCISubClass_0b\r
144 },\r
145 {\r
146 0x0c,\r
147 L"Serial Bus Controllers",\r
148 PCISubClass_0c\r
149 },\r
150 {\r
151 0x0d,\r
152 L"Wireless Controllers",\r
153 PCISubClass_0d\r
154 },\r
155 {\r
156 0x0e,\r
157 L"Intelligent IO Controllers",\r
158 PCISubClass_0e\r
159 },\r
160 {\r
161 0x0f,\r
162 L"Satellite Communications Controllers",\r
163 PCISubClass_0f\r
164 },\r
165 {\r
166 0x10,\r
167 L"Encryption/Decryption Controllers",\r
168 PCISubClass_10\r
169 },\r
170 {\r
171 0x11,\r
172 L"Data Acquisition & Signal Processing Controllers",\r
173 PCISubClass_11\r
174 },\r
175 {\r
176 0xff,\r
177 L"Device does not fit in any defined classes",\r
178 PCIBlankEntry\r
179 },\r
180 {\r
181 0x00,\r
182 NULL,\r
183 /* null string ends the list */NULL\r
184 }\r
185};\r
186\r
187//\r
188// Subclass strings entries\r
189//\r
190PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
191 {\r
192 0x00,\r
193 L"",\r
194 PCIBlankEntry\r
195 },\r
196 {\r
197 0x00,\r
198 NULL,\r
199 /* null string ends the list */NULL\r
200 }\r
201};\r
202\r
203PCI_CLASS_ENTRY PCISubClass_00[] = {\r
204 {\r
205 0x00,\r
206 L"All devices other than VGA",\r
207 PCIBlankEntry\r
208 },\r
209 {\r
210 0x01,\r
211 L"VGA-compatible devices",\r
212 PCIBlankEntry\r
213 },\r
214 {\r
215 0x00,\r
216 NULL,\r
217 /* null string ends the list */NULL\r
218 }\r
219};\r
220\r
221PCI_CLASS_ENTRY PCISubClass_01[] = {\r
222 {\r
223 0x00,\r
224 L"SCSI controller",\r
225 PCIBlankEntry\r
226 },\r
227 {\r
228 0x01,\r
229 L"IDE controller",\r
230 PCIPIFClass_0101\r
231 },\r
232 {\r
233 0x02,\r
234 L"Floppy disk controller",\r
235 PCIBlankEntry\r
236 },\r
237 {\r
238 0x03,\r
239 L"IPI controller",\r
240 PCIBlankEntry\r
241 },\r
242 {\r
243 0x04,\r
244 L"RAID controller",\r
245 PCIBlankEntry\r
246 },\r
247 {\r
248 0x80,\r
249 L"Other mass storage controller",\r
250 PCIBlankEntry\r
251 },\r
252 {\r
253 0x00,\r
254 NULL,\r
255 /* null string ends the list */NULL\r
256 }\r
257};\r
258\r
259PCI_CLASS_ENTRY PCISubClass_02[] = {\r
260 {\r
261 0x00,\r
262 L"Ethernet controller",\r
263 PCIBlankEntry\r
264 },\r
265 {\r
266 0x01,\r
267 L"Token ring controller",\r
268 PCIBlankEntry\r
269 },\r
270 {\r
271 0x02,\r
272 L"FDDI controller",\r
273 PCIBlankEntry\r
274 },\r
275 {\r
276 0x03,\r
277 L"ATM controller",\r
278 PCIBlankEntry\r
279 },\r
280 {\r
281 0x04,\r
282 L"ISDN controller",\r
283 PCIBlankEntry\r
284 },\r
285 {\r
286 0x80,\r
287 L"Other network controller",\r
288 PCIBlankEntry\r
289 },\r
290 {\r
291 0x00,\r
292 NULL,\r
293 /* null string ends the list */NULL\r
294 }\r
295};\r
296\r
297PCI_CLASS_ENTRY PCISubClass_03[] = {\r
298 {\r
299 0x00,\r
300 L"VGA/8514 controller",\r
301 PCIPIFClass_0300\r
302 },\r
303 {\r
304 0x01,\r
305 L"XGA controller",\r
306 PCIBlankEntry\r
307 },\r
308 {\r
309 0x02,\r
310 L"3D controller",\r
311 PCIBlankEntry\r
312 },\r
313 {\r
314 0x80,\r
315 L"Other display controller",\r
316 PCIBlankEntry\r
317 },\r
318 {\r
319 0x00,\r
320 NULL,\r
321 /* null string ends the list */PCIBlankEntry\r
322 }\r
323};\r
324\r
325PCI_CLASS_ENTRY PCISubClass_04[] = {\r
326 {\r
327 0x00,\r
328 L"Video device",\r
329 PCIBlankEntry\r
330 },\r
331 {\r
332 0x01,\r
333 L"Audio device",\r
334 PCIBlankEntry\r
335 },\r
336 {\r
337 0x02,\r
338 L"Computer Telephony device",\r
339 PCIBlankEntry\r
340 },\r
341 {\r
342 0x80,\r
343 L"Other multimedia device",\r
344 PCIBlankEntry\r
345 },\r
346 {\r
347 0x00,\r
348 NULL,\r
349 /* null string ends the list */NULL\r
350 }\r
351};\r
352\r
353PCI_CLASS_ENTRY PCISubClass_05[] = {\r
354 {\r
355 0x00,\r
356 L"RAM memory controller",\r
357 PCIBlankEntry\r
358 },\r
359 {\r
360 0x01,\r
361 L"Flash memory controller",\r
362 PCIBlankEntry\r
363 },\r
364 {\r
365 0x80,\r
366 L"Other memory controller",\r
367 PCIBlankEntry\r
368 },\r
369 {\r
370 0x00,\r
371 NULL,\r
372 /* null string ends the list */NULL\r
373 }\r
374};\r
375\r
376PCI_CLASS_ENTRY PCISubClass_06[] = {\r
377 {\r
378 0x00,\r
379 L"Host/PCI bridge",\r
380 PCIBlankEntry\r
381 },\r
382 {\r
383 0x01,\r
384 L"PCI/ISA bridge",\r
385 PCIBlankEntry\r
386 },\r
387 {\r
388 0x02,\r
389 L"PCI/EISA bridge",\r
390 PCIBlankEntry\r
391 },\r
392 {\r
393 0x03,\r
394 L"PCI/Micro Channel bridge",\r
395 PCIBlankEntry\r
396 },\r
397 {\r
398 0x04,\r
399 L"PCI/PCI bridge",\r
400 PCIPIFClass_0604\r
401 },\r
402 {\r
403 0x05,\r
404 L"PCI/PCMCIA bridge",\r
405 PCIBlankEntry\r
406 },\r
407 {\r
408 0x06,\r
409 L"NuBus bridge",\r
410 PCIBlankEntry\r
411 },\r
412 {\r
413 0x07,\r
414 L"CardBus bridge",\r
415 PCIBlankEntry\r
416 },\r
417 {\r
418 0x08,\r
419 L"RACEway bridge",\r
420 PCIBlankEntry\r
421 },\r
422 {\r
423 0x80,\r
424 L"Other bridge type",\r
425 PCIBlankEntry\r
426 },\r
427 {\r
428 0x00,\r
429 NULL,\r
430 /* null string ends the list */NULL\r
431 }\r
432};\r
433\r
434PCI_CLASS_ENTRY PCISubClass_07[] = {\r
435 {\r
436 0x00,\r
437 L"Serial controller",\r
438 PCIPIFClass_0700\r
439 },\r
440 {\r
441 0x01,\r
442 L"Parallel port",\r
443 PCIPIFClass_0701\r
444 },\r
445 {\r
446 0x02,\r
447 L"Multiport serial controller",\r
448 PCIBlankEntry\r
449 },\r
450 {\r
451 0x03,\r
452 L"Modem",\r
453 PCIPIFClass_0703\r
454 },\r
455 {\r
456 0x80,\r
457 L"Other communication device",\r
458 PCIBlankEntry\r
459 },\r
460 {\r
461 0x00,\r
462 NULL,\r
463 /* null string ends the list */NULL\r
464 }\r
465};\r
466\r
467PCI_CLASS_ENTRY PCISubClass_08[] = {\r
468 {\r
469 0x00,\r
470 L"PIC",\r
471 PCIPIFClass_0800\r
472 },\r
473 {\r
474 0x01,\r
475 L"DMA controller",\r
476 PCIPIFClass_0801\r
477 },\r
478 {\r
479 0x02,\r
480 L"System timer",\r
481 PCIPIFClass_0802\r
482 },\r
483 {\r
484 0x03,\r
485 L"RTC controller",\r
486 PCIPIFClass_0803\r
487 },\r
488 {\r
489 0x04,\r
490 L"Generic PCI Hot-Plug controller",\r
491 PCIBlankEntry\r
492 },\r
493 {\r
494 0x80,\r
495 L"Other system peripheral",\r
496 PCIBlankEntry\r
497 },\r
498 {\r
499 0x00,\r
500 NULL,\r
501 /* null string ends the list */NULL\r
502 }\r
503};\r
504\r
505PCI_CLASS_ENTRY PCISubClass_09[] = {\r
506 {\r
507 0x00,\r
508 L"Keyboard controller",\r
509 PCIBlankEntry\r
510 },\r
511 {\r
512 0x01,\r
513 L"Digitizer (pen)",\r
514 PCIBlankEntry\r
515 },\r
516 {\r
517 0x02,\r
518 L"Mouse controller",\r
519 PCIBlankEntry\r
520 },\r
521 {\r
522 0x03,\r
523 L"Scanner controller",\r
524 PCIBlankEntry\r
525 },\r
526 {\r
527 0x04,\r
528 L"Gameport controller",\r
529 PCIPIFClass_0904\r
530 },\r
531 {\r
532 0x80,\r
533 L"Other input controller",\r
534 PCIBlankEntry\r
535 },\r
536 {\r
537 0x00,\r
538 NULL,\r
539 /* null string ends the list */NULL\r
540 }\r
541};\r
542\r
543PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
544 {\r
545 0x00,\r
546 L"Generic docking station",\r
547 PCIBlankEntry\r
548 },\r
549 {\r
550 0x80,\r
551 L"Other type of docking station",\r
552 PCIBlankEntry\r
553 },\r
554 {\r
555 0x00,\r
556 NULL,\r
557 /* null string ends the list */NULL\r
558 }\r
559};\r
560\r
561PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
562 {\r
563 0x00,\r
564 L"386",\r
565 PCIBlankEntry\r
566 },\r
567 {\r
568 0x01,\r
569 L"486",\r
570 PCIBlankEntry\r
571 },\r
572 {\r
573 0x02,\r
574 L"Pentium",\r
575 PCIBlankEntry\r
576 },\r
577 {\r
578 0x10,\r
579 L"Alpha",\r
580 PCIBlankEntry\r
581 },\r
582 {\r
583 0x20,\r
584 L"PowerPC",\r
585 PCIBlankEntry\r
586 },\r
587 {\r
588 0x30,\r
589 L"MIPS",\r
590 PCIBlankEntry\r
591 },\r
592 {\r
593 0x40,\r
594 L"Co-processor",\r
595 PCIBlankEntry\r
596 },\r
597 {\r
598 0x80,\r
599 L"Other processor",\r
600 PCIBlankEntry\r
601 },\r
602 {\r
603 0x00,\r
604 NULL,\r
605 /* null string ends the list */NULL\r
606 }\r
607};\r
608\r
609PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
610 {\r
611 0x00,\r
612 L"Firewire(IEEE 1394)",\r
613 PCIPIFClass_0c03\r
614 },\r
615 {\r
616 0x01,\r
617 L"ACCESS.bus",\r
618 PCIBlankEntry\r
619 },\r
620 {\r
621 0x02,\r
622 L"SSA",\r
623 PCIBlankEntry\r
624 },\r
625 {\r
626 0x03,\r
627 L"USB",\r
628 PCIPIFClass_0c00\r
629 },\r
630 {\r
631 0x04,\r
632 L"Fibre Channel",\r
633 PCIBlankEntry\r
634 },\r
635 {\r
636 0x05,\r
637 L"System Management Bus",\r
638 PCIBlankEntry\r
639 },\r
640 {\r
641 0x80,\r
642 L"Other bus type",\r
643 PCIBlankEntry\r
644 },\r
645 {\r
646 0x00,\r
647 NULL,\r
648 /* null string ends the list */NULL\r
649 }\r
650};\r
651\r
652PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
653 {\r
654 0x00,\r
655 L"iRDA compatible controller",\r
656 PCIBlankEntry\r
657 },\r
658 {\r
659 0x01,\r
660 L"Consumer IR controller",\r
661 PCIBlankEntry\r
662 },\r
663 {\r
664 0x10,\r
665 L"RF controller",\r
666 PCIBlankEntry\r
667 },\r
668 {\r
669 0x80,\r
670 L"Other type of wireless controller",\r
671 PCIBlankEntry\r
672 },\r
673 {\r
674 0x00,\r
675 NULL,\r
676 /* null string ends the list */NULL\r
677 }\r
678};\r
679\r
680PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
681 {\r
682 0x00,\r
683 L"I2O Architecture",\r
684 PCIPIFClass_0e00\r
685 },\r
686 {\r
687 0x00,\r
688 NULL,\r
689 /* null string ends the list */NULL\r
690 }\r
691};\r
692\r
693PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
694 {\r
695 0x00,\r
696 L"TV",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x01,\r
701 L"Audio",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x02,\r
706 L"Voice",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x03,\r
711 L"Data",\r
712 PCIBlankEntry\r
713 },\r
714 {\r
715 0x00,\r
716 NULL,\r
717 /* null string ends the list */NULL\r
718 }\r
719};\r
720\r
721PCI_CLASS_ENTRY PCISubClass_10[] = {\r
722 {\r
723 0x00,\r
724 L"Network & computing Encrypt/Decrypt",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x01,\r
729 L"Entertainment Encrypt/Decrypt",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x80,\r
734 L"Other Encrypt/Decrypt",\r
735 PCIBlankEntry\r
736 },\r
737 {\r
738 0x00,\r
739 NULL,\r
740 /* null string ends the list */NULL\r
741 }\r
742};\r
743\r
744PCI_CLASS_ENTRY PCISubClass_11[] = {\r
745 {\r
746 0x00,\r
747 L"DPIO modules",\r
748 PCIBlankEntry\r
749 },\r
750 {\r
751 0x80,\r
752 L"Other DAQ & SP controllers",\r
753 PCIBlankEntry\r
754 },\r
755 {\r
756 0x00,\r
757 NULL,\r
758 /* null string ends the list */NULL\r
759 }\r
760};\r
761\r
762//\r
763// Programming Interface entries\r
764//\r
765PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
766 {\r
767 0x00,\r
768 L"",\r
769 PCIBlankEntry\r
770 },\r
771 {\r
772 0x01,\r
773 L"OM-primary",\r
774 PCIBlankEntry\r
775 },\r
776 {\r
777 0x02,\r
778 L"PI-primary",\r
779 PCIBlankEntry\r
780 },\r
781 {\r
782 0x03,\r
783 L"OM/PI-primary",\r
784 PCIBlankEntry\r
785 },\r
786 {\r
787 0x04,\r
788 L"OM-secondary",\r
789 PCIBlankEntry\r
790 },\r
791 {\r
792 0x05,\r
793 L"OM-primary, OM-secondary",\r
794 PCIBlankEntry\r
795 },\r
796 {\r
797 0x06,\r
798 L"PI-primary, OM-secondary",\r
799 PCIBlankEntry\r
800 },\r
801 {\r
802 0x07,\r
803 L"OM/PI-primary, OM-secondary",\r
804 PCIBlankEntry\r
805 },\r
806 {\r
807 0x08,\r
808 L"OM-secondary",\r
809 PCIBlankEntry\r
810 },\r
811 {\r
812 0x09,\r
813 L"OM-primary, PI-secondary",\r
814 PCIBlankEntry\r
815 },\r
816 {\r
817 0x0a,\r
818 L"PI-primary, PI-secondary",\r
819 PCIBlankEntry\r
820 },\r
821 {\r
822 0x0b,\r
823 L"OM/PI-primary, PI-secondary",\r
824 PCIBlankEntry\r
825 },\r
826 {\r
827 0x0c,\r
828 L"OM-secondary",\r
829 PCIBlankEntry\r
830 },\r
831 {\r
832 0x0d,\r
833 L"OM-primary, OM/PI-secondary",\r
834 PCIBlankEntry\r
835 },\r
836 {\r
837 0x0e,\r
838 L"PI-primary, OM/PI-secondary",\r
839 PCIBlankEntry\r
840 },\r
841 {\r
842 0x0f,\r
843 L"OM/PI-primary, OM/PI-secondary",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
847 0x80,\r
848 L"Master",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
852 0x81,\r
853 L"Master, OM-primary",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
857 0x82,\r
858 L"Master, PI-primary",\r
859 PCIBlankEntry\r
860 },\r
861 {\r
862 0x83,\r
863 L"Master, OM/PI-primary",\r
864 PCIBlankEntry\r
865 },\r
866 {\r
867 0x84,\r
868 L"Master, OM-secondary",\r
869 PCIBlankEntry\r
870 },\r
871 {\r
872 0x85,\r
873 L"Master, OM-primary, OM-secondary",\r
874 PCIBlankEntry\r
875 },\r
876 {\r
877 0x86,\r
878 L"Master, PI-primary, OM-secondary",\r
879 PCIBlankEntry\r
880 },\r
881 {\r
882 0x87,\r
883 L"Master, OM/PI-primary, OM-secondary",\r
884 PCIBlankEntry\r
885 },\r
886 {\r
887 0x88,\r
888 L"Master, OM-secondary",\r
889 PCIBlankEntry\r
890 },\r
891 {\r
892 0x89,\r
893 L"Master, OM-primary, PI-secondary",\r
894 PCIBlankEntry\r
895 },\r
896 {\r
897 0x8a,\r
898 L"Master, PI-primary, PI-secondary",\r
899 PCIBlankEntry\r
900 },\r
901 {\r
902 0x8b,\r
903 L"Master, OM/PI-primary, PI-secondary",\r
904 PCIBlankEntry\r
905 },\r
906 {\r
907 0x8c,\r
908 L"Master, OM-secondary",\r
909 PCIBlankEntry\r
910 },\r
911 {\r
912 0x8d,\r
913 L"Master, OM-primary, OM/PI-secondary",\r
914 PCIBlankEntry\r
915 },\r
916 {\r
917 0x8e,\r
918 L"Master, PI-primary, OM/PI-secondary",\r
919 PCIBlankEntry\r
920 },\r
921 {\r
922 0x8f,\r
923 L"Master, OM/PI-primary, OM/PI-secondary",\r
924 PCIBlankEntry\r
925 },\r
926 {\r
927 0x00,\r
928 NULL,\r
929 /* null string ends the list */NULL\r
930 }\r
931};\r
932\r
933PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
934 {\r
935 0x00,\r
936 L"VGA compatible",\r
937 PCIBlankEntry\r
938 },\r
939 {\r
940 0x01,\r
941 L"8514 compatible",\r
942 PCIBlankEntry\r
943 },\r
944 {\r
945 0x00,\r
946 NULL,\r
947 /* null string ends the list */NULL\r
948 }\r
949};\r
950\r
951PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
952 {\r
953 0x00,\r
954 L"",\r
955 PCIBlankEntry\r
956 },\r
957 {\r
958 0x01,\r
959 L"Subtractive decode",\r
960 PCIBlankEntry\r
961 },\r
962 {\r
963 0x00,\r
964 NULL,\r
965 /* null string ends the list */NULL\r
966 }\r
967};\r
968\r
969PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
970 {\r
971 0x00,\r
972 L"Generic XT-compatible",\r
973 PCIBlankEntry\r
974 },\r
975 {\r
976 0x01,\r
977 L"16450-compatible",\r
978 PCIBlankEntry\r
979 },\r
980 {\r
981 0x02,\r
982 L"16550-compatible",\r
983 PCIBlankEntry\r
984 },\r
985 {\r
986 0x03,\r
987 L"16650-compatible",\r
988 PCIBlankEntry\r
989 },\r
990 {\r
991 0x04,\r
992 L"16750-compatible",\r
993 PCIBlankEntry\r
994 },\r
995 {\r
996 0x05,\r
997 L"16850-compatible",\r
998 PCIBlankEntry\r
999 },\r
1000 {\r
1001 0x06,\r
1002 L"16950-compatible",\r
1003 PCIBlankEntry\r
1004 },\r
1005 {\r
1006 0x00,\r
1007 NULL,\r
1008 /* null string ends the list */NULL\r
1009 }\r
1010};\r
1011\r
1012PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1013 {\r
1014 0x00,\r
1015 L"",\r
1016 PCIBlankEntry\r
1017 },\r
1018 {\r
1019 0x01,\r
1020 L"Bi-directional",\r
1021 PCIBlankEntry\r
1022 },\r
1023 {\r
1024 0x02,\r
1025 L"ECP 1.X-compliant",\r
1026 PCIBlankEntry\r
1027 },\r
1028 {\r
1029 0x03,\r
1030 L"IEEE 1284",\r
1031 PCIBlankEntry\r
1032 },\r
1033 {\r
1034 0xfe,\r
1035 L"IEEE 1284 target (not a controller)",\r
1036 PCIBlankEntry\r
1037 },\r
1038 {\r
1039 0x00,\r
1040 NULL,\r
1041 /* null string ends the list */NULL\r
1042 }\r
1043};\r
1044\r
1045PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1046 {\r
1047 0x00,\r
1048 L"Generic",\r
1049 PCIBlankEntry\r
1050 },\r
1051 {\r
1052 0x01,\r
1053 L"Hayes-compatible 16450",\r
1054 PCIBlankEntry\r
1055 },\r
1056 {\r
1057 0x02,\r
1058 L"Hayes-compatible 16550",\r
1059 PCIBlankEntry\r
1060 },\r
1061 {\r
1062 0x03,\r
1063 L"Hayes-compatible 16650",\r
1064 PCIBlankEntry\r
1065 },\r
1066 {\r
1067 0x04,\r
1068 L"Hayes-compatible 16750",\r
1069 PCIBlankEntry\r
1070 },\r
1071 {\r
1072 0x00,\r
1073 NULL,\r
1074 /* null string ends the list */NULL\r
1075 }\r
1076};\r
1077\r
1078PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1079 {\r
1080 0x00,\r
1081 L"Generic 8259",\r
1082 PCIBlankEntry\r
1083 },\r
1084 {\r
1085 0x01,\r
1086 L"ISA",\r
1087 PCIBlankEntry\r
1088 },\r
1089 {\r
1090 0x02,\r
1091 L"EISA",\r
1092 PCIBlankEntry\r
1093 },\r
1094 {\r
1095 0x10,\r
1096 L"IO APIC",\r
1097 PCIBlankEntry\r
1098 },\r
1099 {\r
1100 0x20,\r
1101 L"IO(x) APIC interrupt controller",\r
1102 PCIBlankEntry\r
1103 },\r
1104 {\r
1105 0x00,\r
1106 NULL,\r
1107 /* null string ends the list */NULL\r
1108 }\r
1109};\r
1110\r
1111PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1112 {\r
1113 0x00,\r
1114 L"Generic 8237",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x01,\r
1119 L"ISA",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x02,\r
1124 L"EISA",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x00,\r
1129 NULL,\r
1130 /* null string ends the list */NULL\r
1131 }\r
1132};\r
1133\r
1134PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1135 {\r
1136 0x00,\r
1137 L"Generic 8254",\r
1138 PCIBlankEntry\r
1139 },\r
1140 {\r
1141 0x01,\r
1142 L"ISA",\r
1143 PCIBlankEntry\r
1144 },\r
1145 {\r
1146 0x02,\r
1147 L"EISA",\r
1148 PCIBlankEntry\r
1149 },\r
1150 {\r
1151 0x00,\r
1152 NULL,\r
1153 /* null string ends the list */NULL\r
1154 }\r
1155};\r
1156\r
1157PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1158 {\r
1159 0x00,\r
1160 L"Generic",\r
1161 PCIBlankEntry\r
1162 },\r
1163 {\r
1164 0x01,\r
1165 L"ISA",\r
1166 PCIBlankEntry\r
1167 },\r
1168 {\r
1169 0x02,\r
1170 L"EISA",\r
1171 PCIBlankEntry\r
1172 },\r
1173 {\r
1174 0x00,\r
1175 NULL,\r
1176 /* null string ends the list */NULL\r
1177 }\r
1178};\r
1179\r
1180PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1181 {\r
1182 0x00,\r
1183 L"Generic",\r
1184 PCIBlankEntry\r
1185 },\r
1186 {\r
1187 0x10,\r
1188 L"",\r
1189 PCIBlankEntry\r
1190 },\r
1191 {\r
1192 0x00,\r
1193 NULL,\r
1194 /* null string ends the list */NULL\r
1195 }\r
1196};\r
1197\r
1198PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1199 {\r
1200 0x00,\r
1201 L"Universal Host Controller spec",\r
1202 PCIBlankEntry\r
1203 },\r
1204 {\r
1205 0x10,\r
1206 L"Open Host Controller spec",\r
1207 PCIBlankEntry\r
1208 },\r
1209 {\r
1210 0x80,\r
1211 L"No specific programming interface",\r
1212 PCIBlankEntry\r
1213 },\r
1214 {\r
1215 0xfe,\r
1216 L"(Not Host Controller)",\r
1217 PCIBlankEntry\r
1218 },\r
1219 {\r
1220 0x00,\r
1221 NULL,\r
1222 /* null string ends the list */NULL\r
1223 }\r
1224};\r
1225\r
1226PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1227 {\r
1228 0x00,\r
1229 L"",\r
1230 PCIBlankEntry\r
1231 },\r
1232 {\r
1233 0x10,\r
1234 L"Using 1394 OpenHCI spec",\r
1235 PCIBlankEntry\r
1236 },\r
1237 {\r
1238 0x00,\r
1239 NULL,\r
1240 /* null string ends the list */NULL\r
1241 }\r
1242};\r
1243\r
1244PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1245 {\r
1246 0x00,\r
1247 L"Message FIFO at offset 40h",\r
1248 PCIBlankEntry\r
1249 },\r
1250 {\r
1251 0x01,\r
1252 L"",\r
1253 PCIBlankEntry\r
1254 },\r
1255 {\r
1256 0x00,\r
1257 NULL,\r
1258 /* null string ends the list */NULL\r
1259 }\r
1260};\r
1261\r
5d73d92f 1262\r
a1d4bfcc 1263/**\r
5d73d92f 1264 Generates printable Unicode strings that represent PCI device class,\r
1265 subclass and programmed I/F based on a value passed to the function.\r
1266\r
a1d4bfcc 1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1268 PCI device. The encodings are:\r
1269 bits 23:16 - Base Class Code\r
1270 bits 15:8 - Sub-Class Code\r
1271 bits 7:0 - Programming Interface\r
4ff7e37b 1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1273 printable class strings corresponding to ClassCode. The\r
1274 caller must not modify the strings that are pointed by\r
1275 the fields in ClassStrings.\r
5d73d92f 1276**/\r
a1d4bfcc 1277VOID\r
1278PciGetClassStrings (\r
1279 IN UINT32 ClassCode,\r
1280 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1281 )\r
5d73d92f 1282{\r
1283 INTN Index;\r
1284 UINT8 Code;\r
1285 PCI_CLASS_ENTRY *CurrentClass;\r
1286\r
1287 //\r
1288 // Assume no strings found\r
1289 //\r
1290 ClassStrings->BaseClass = L"UNDEFINED";\r
1291 ClassStrings->SubClass = L"UNDEFINED";\r
1292 ClassStrings->PIFClass = L"UNDEFINED";\r
1293\r
1294 CurrentClass = gClassStringList;\r
1295 Code = (UINT8) (ClassCode >> 16);\r
1296 Index = 0;\r
1297\r
1298 //\r
1299 // Go through all entries of the base class, until the entry with a matching\r
1300 // base class code is found. If reaches an entry with a null description\r
1301 // text, the last entry is met, which means no text for the base class was\r
1302 // found, so no more action is needed.\r
1303 //\r
1304 while (Code != CurrentClass[Index].Code) {\r
1305 if (NULL == CurrentClass[Index].DescText) {\r
1306 return ;\r
1307 }\r
1308\r
1309 Index++;\r
1310 }\r
1311 //\r
1312 // A base class was found. Assign description, and check if this class has\r
1313 // sub-class defined. If sub-class defined, no more action is needed,\r
1314 // otherwise, continue to find description for the sub-class code.\r
1315 //\r
1316 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1317 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1318 return ;\r
1319 }\r
1320 //\r
1321 // find Subclass entry\r
1322 //\r
1323 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1324 Code = (UINT8) (ClassCode >> 8);\r
1325 Index = 0;\r
1326\r
1327 //\r
1328 // Go through all entries of the sub-class, until the entry with a matching\r
1329 // sub-class code is found. If reaches an entry with a null description\r
1330 // text, the last entry is met, which means no text for the sub-class was\r
1331 // found, so no more action is needed.\r
1332 //\r
1333 while (Code != CurrentClass[Index].Code) {\r
1334 if (NULL == CurrentClass[Index].DescText) {\r
1335 return ;\r
1336 }\r
1337\r
1338 Index++;\r
1339 }\r
1340 //\r
1341 // A class was found for the sub-class code. Assign description, and check if\r
1342 // this sub-class has programming interface defined. If no, no more action is\r
1343 // needed, otherwise, continue to find description for the programming\r
1344 // interface.\r
1345 //\r
1346 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1347 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1348 return ;\r
1349 }\r
1350 //\r
1351 // Find programming interface entry\r
1352 //\r
1353 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1354 Code = (UINT8) ClassCode;\r
1355 Index = 0;\r
1356\r
1357 //\r
1358 // Go through all entries of the I/F entries, until the entry with a\r
1359 // matching I/F code is found. If reaches an entry with a null description\r
1360 // text, the last entry is met, which means no text was found, so no more\r
1361 // action is needed.\r
1362 //\r
1363 while (Code != CurrentClass[Index].Code) {\r
1364 if (NULL == CurrentClass[Index].DescText) {\r
1365 return ;\r
1366 }\r
1367\r
1368 Index++;\r
1369 }\r
1370 //\r
1371 // A class was found for the I/F code. Assign description, done!\r
1372 //\r
1373 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1374 return ;\r
1375}\r
1376\r
a1d4bfcc 1377/**\r
1378 Print strings that represent PCI device class, subclass and programmed I/F.\r
1379\r
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1381 configuation space.\r
1382 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1383**/\r
5d73d92f 1384VOID\r
1385PciPrintClassCode (\r
1386 IN UINT8 *ClassCodePtr,\r
1387 IN BOOLEAN IncludePIF\r
1388 )\r
5d73d92f 1389{\r
1390 UINT32 ClassCode;\r
1391 PCI_CLASS_STRINGS ClassStrings;\r
5d73d92f 1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
c37e0f16 1405 // Print base class, sub class, and programming inferface name\r
5d73d92f 1406 //\r
c37e0f16 1407 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
5d73d92f 1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
c37e0f16 1415 // Only print base class and sub class name\r
5d73d92f 1416 //\r
c37e0f16 1417 ShellPrintEx (-1, -1, L"%s - %s",\r
5d73d92f 1418 ClassStrings.BaseClass,\r
1419 ClassStrings.SubClass\r
c37e0f16 1420 );\r
5d73d92f 1421 }\r
1422}\r
1423\r
a1d4bfcc 1424/**\r
1425 This function finds out the protocol which is in charge of the given\r
1426 segment, and its bus range covers the current bus number. It lookes\r
1427 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1428 criteria is found.\r
1429\r
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1432 @param[in] Segment Segment number of device we are dealing with.\r
1433 @param[in] Bus Bus number of device we are dealing with.\r
1434 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1435\r
1436 @retval EFI_SUCCESS The command completed successfully.\r
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1438\r
a1d4bfcc 1439**/\r
5d73d92f 1440EFI_STATUS\r
1441PciFindProtocolInterface (\r
1442 IN EFI_HANDLE *HandleBuf,\r
1443 IN UINTN HandleCount,\r
1444 IN UINT16 Segment,\r
1445 IN UINT16 Bus,\r
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1447 );\r
1448\r
a1d4bfcc 1449/**\r
1450 This function gets the protocol interface from the given handle, and\r
1451 obtains its address space descriptors.\r
1452\r
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1454 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1455 @param[out] Descriptors Points to the address space descriptors.\r
1456\r
1457 @retval EFI_SUCCESS The command completed successfully\r
1458**/\r
5d73d92f 1459EFI_STATUS\r
1460PciGetProtocolAndResource (\r
1461 IN EFI_HANDLE Handle,\r
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1464 );\r
1465\r
a1d4bfcc 1466/**\r
1467 This function get the next bus range of given address space descriptors.\r
1468 It also moves the pointer backward a node, to get prepared to be called\r
1469 again.\r
1470\r
4ff7e37b
ED		 1471 @param[in, out] Descriptors Points to current position of a serial of address space\r
1472 descriptors.\r
1473 @param[out] MinBus The lower range of bus number.\r
1474 @param[out] MaxBus The upper range of bus number.\r
1475 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 1476\r
1477 @retval EFI_SUCCESS The command completed successfully.\r
1478**/\r
5d73d92f 1479EFI_STATUS\r
1480PciGetNextBusRange (\r
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1482 OUT UINT16 *MinBus,\r
1483 OUT UINT16 *MaxBus,\r
1484 OUT BOOLEAN *IsEnd\r
1485 );\r
1486\r
a1d4bfcc 1487/**\r
1488 Explain the data in PCI configuration space. The part which is common for\r
1489 PCI device and bridge is interpreted in this function. It calls other\r
1490 functions to interpret data unique for device or bridge.\r
1491\r
1492 @param[in] ConfigSpace Data in PCI configuration space.\r
1493 @param[in] Address Address used to access configuration space of this PCI device.\r
1494 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1495\r
1496 @retval EFI_SUCCESS The command completed successfully.\r
1497**/\r
5d73d92f 1498EFI_STATUS\r
1499PciExplainData (\r
1500 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1501 IN UINT64 Address,\r
1502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1503 );\r
1504\r
a1d4bfcc 1505/**\r
1506 Explain the device specific part of data in PCI configuration space.\r
1507\r
1508 @param[in] Device Data in PCI configuration space.\r
1509 @param[in] Address Address used to access configuration space of this PCI device.\r
1510 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1511\r
1512 @retval EFI_SUCCESS The command completed successfully.\r
1513**/\r
5d73d92f 1514EFI_STATUS\r
1515PciExplainDeviceData (\r
1516 IN PCI_DEVICE_HEADER *Device,\r
1517 IN UINT64 Address,\r
1518 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1519 );\r
1520\r
a1d4bfcc 1521/**\r
1522 Explain the bridge specific part of data in PCI configuration space.\r
1523\r
1524 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1525 @param[in] Address Address used to access configuration space of this PCI device.\r
1526 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1527\r
1528 @retval EFI_SUCCESS The command completed successfully.\r
1529**/\r
5d73d92f 1530EFI_STATUS\r
1531PciExplainBridgeData (\r
a1d4bfcc 1532 IN PCI_BRIDGE_HEADER *Bridge,\r
1533 IN UINT64 Address,\r
1534 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1535 );\r
1536\r
a1d4bfcc 1537/**\r
1538 Explain the Base Address Register(Bar) in PCI configuration space.\r
1539\r
4ff7e37b
ED		 1540 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1541 @param[in] Command Points to the register Command.\r
1542 @param[in] Address Address used to access configuration space of this PCI device.\r
1543 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1544 @param[in, out] Index The Index.\r
a1d4bfcc 1545\r
1546 @retval EFI_SUCCESS The command completed successfully.\r
1547**/\r
5d73d92f 1548EFI_STATUS\r
1549PciExplainBar (\r
1550 IN UINT32 *Bar,\r
1551 IN UINT16 *Command,\r
1552 IN UINT64 Address,\r
1553 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1554 IN OUT UINTN *Index\r
1555 );\r
1556\r
a1d4bfcc 1557/**\r
1558 Explain the cardbus specific part of data in PCI configuration space.\r
1559\r
1560 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1561 @param[in] Address Address used to access configuration space of this PCI device.\r
1562 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1563\r
1564 @retval EFI_SUCCESS The command completed successfully.\r
1565**/\r
5d73d92f 1566EFI_STATUS\r
1567PciExplainCardBusData (\r
1568 IN PCI_CARDBUS_HEADER *CardBus,\r
1569 IN UINT64 Address,\r
1570 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1571 );\r
1572\r
a1d4bfcc 1573/**\r
1574 Explain each meaningful bit of register Status. The definition of Status is\r
1575 slightly different depending on the PCI header type.\r
1576\r
1577 @param[in] Status Points to the content of register Status.\r
1578 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1579 status).\r
1580 @param[in] HeaderType Header type of this PCI device.\r
1581\r
1582 @retval EFI_SUCCESS The command completed successfully.\r
1583**/\r
5d73d92f 1584EFI_STATUS\r
1585PciExplainStatus (\r
1586 IN UINT16 *Status,\r
1587 IN BOOLEAN MainStatus,\r
1588 IN PCI_HEADER_TYPE HeaderType\r
1589 );\r
1590\r
a1d4bfcc 1591/**\r
1592 Explain each meaningful bit of register Command.\r
1593\r
1594 @param[in] Command Points to the content of register Command.\r
1595\r
1596 @retval EFI_SUCCESS The command completed successfully.\r
1597**/\r
5d73d92f 1598EFI_STATUS\r
1599PciExplainCommand (\r
1600 IN UINT16 *Command\r
1601 );\r
1602\r
a1d4bfcc 1603/**\r
1604 Explain each meaningful bit of register Bridge Control.\r
1605\r
1606 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1607 @param[in] HeaderType The headertype.\r
1608\r
1609 @retval EFI_SUCCESS The command completed successfully.\r
1610**/\r
5d73d92f 1611EFI_STATUS\r
1612PciExplainBridgeControl (\r
1613 IN UINT16 *BridgeControl,\r
1614 IN PCI_HEADER_TYPE HeaderType\r
1615 );\r
1616\r
a1d4bfcc 1617/**\r
1618 Print each capability structure.\r
1619\r
1620 @param[in] IoDev The pointer to the deivce.\r
1621 @param[in] Address The address to start at.\r
1622 @param[in] CapPtr The offset from the address.\r
1623\r
1624 @retval EFI_SUCCESS The operation was successful.\r
1625**/\r
5d73d92f 1626EFI_STATUS\r
1627PciExplainCapabilityStruct (\r
1628 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1629 IN UINT64 Address,\r
1630 IN UINT8 CapPtr\r
1631 );\r
1632\r
a1d4bfcc 1633/**\r
1634 Display Pcie device structure.\r
1635\r
1636 @param[in] IoDev The pointer to the root pci protocol.\r
1637 @param[in] Address The Address to start at.\r
1638 @param[in] CapabilityPtr The offset from the address to start.\r
1639**/\r
5d73d92f 1640EFI_STATUS\r
1641PciExplainPciExpress (\r
1642 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1643 IN UINT64 Address,\r
1644 IN UINT8 CapabilityPtr\r
1645 );\r
1646\r
a1d4bfcc 1647/**\r
1648 Print out information of the capability information.\r
1649\r
1650 @param[in] PciExpressCap The pointer to the structure about the device.\r
1651\r
1652 @retval EFI_SUCCESS The operation was successful.\r
1653**/\r
5d73d92f 1654EFI_STATUS\r
1655ExplainPcieCapReg (\r
1656 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1657 );\r
1658\r
1659/**\r
1660 Print out information of the device capability information.\r
1661\r
1662 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1663\r
a1d4bfcc 1664 @retval EFI_SUCCESS The operation was successful.\r
1665**/\r
5d73d92f 1666EFI_STATUS\r
1667ExplainPcieDeviceCap (\r
1668 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1669 );\r
1670\r
1671/**\r
1672 Print out information of the device control information.\r
5d73d92f 1673\r
a1d4bfcc 1674 @param[in] PciExpressCap The pointer to the structure about the device.\r
1675\r
1676 @retval EFI_SUCCESS The operation was successful.\r
1677**/\r
5d73d92f 1678EFI_STATUS\r
1679ExplainPcieDeviceControl (\r
1680 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1681 );\r
5d73d92f 1682\r
a1d4bfcc 1683/**\r
1684 Print out information of the device status information.\r
1685\r
1686 @param[in] PciExpressCap The pointer to the structure about the device.\r
1687\r
1688 @retval EFI_SUCCESS The operation was successful.\r
1689**/\r
5d73d92f 1690EFI_STATUS\r
1691ExplainPcieDeviceStatus (\r
1692 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1693 );\r
1694\r
1695/**\r
1696 Print out information of the device link information.\r
1697\r
1698 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1699\r
a1d4bfcc 1700 @retval EFI_SUCCESS The operation was successful.\r
1701**/\r
5d73d92f 1702EFI_STATUS\r
1703ExplainPcieLinkCap (\r
1704 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1705 );\r
1706\r
1707/**\r
1708 Print out information of the device link control information.\r
5d73d92f 1709\r
a1d4bfcc 1710 @param[in] PciExpressCap The pointer to the structure about the device.\r
1711\r
1712 @retval EFI_SUCCESS The operation was successful.\r
1713**/\r
5d73d92f 1714EFI_STATUS\r
1715ExplainPcieLinkControl (\r
1716 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1717 );\r
5d73d92f 1718\r
a1d4bfcc 1719/**\r
1720 Print out information of the device link status information.\r
1721\r
1722 @param[in] PciExpressCap The pointer to the structure about the device.\r
1723\r
1724 @retval EFI_SUCCESS The operation was successful.\r
1725**/\r
5d73d92f 1726EFI_STATUS\r
1727ExplainPcieLinkStatus (\r
1728 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1729 );\r
1730\r
1731/**\r
1732 Print out information of the device slot information.\r
1733\r
1734 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1735\r
a1d4bfcc 1736 @retval EFI_SUCCESS The operation was successful.\r
1737**/\r
5d73d92f 1738EFI_STATUS\r
1739ExplainPcieSlotCap (\r
1740 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1741 );\r
1742\r
1743/**\r
1744 Print out information of the device slot control information.\r
5d73d92f 1745\r
a1d4bfcc 1746 @param[in] PciExpressCap The pointer to the structure about the device.\r
1747\r
1748 @retval EFI_SUCCESS The operation was successful.\r
1749**/\r
5d73d92f 1750EFI_STATUS\r
1751ExplainPcieSlotControl (\r
1752 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1753 );\r
5d73d92f 1754\r
a1d4bfcc 1755/**\r
1756 Print out information of the device slot status information.\r
1757\r
1758 @param[in] PciExpressCap The pointer to the structure about the device.\r
1759\r
1760 @retval EFI_SUCCESS The operation was successful.\r
1761**/\r
5d73d92f 1762EFI_STATUS\r
1763ExplainPcieSlotStatus (\r
1764 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1765 );\r
1766\r
1767/**\r
1768 Print out information of the device root information.\r
1769\r
1770 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1771\r
a1d4bfcc 1772 @retval EFI_SUCCESS The operation was successful.\r
1773**/\r
5d73d92f 1774EFI_STATUS\r
1775ExplainPcieRootControl (\r
1776 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1777 );\r
1778\r
1779/**\r
1780 Print out information of the device root capability information.\r
5d73d92f 1781\r
a1d4bfcc 1782 @param[in] PciExpressCap The pointer to the structure about the device.\r
1783\r
1784 @retval EFI_SUCCESS The operation was successful.\r
1785**/\r
5d73d92f 1786EFI_STATUS\r
1787ExplainPcieRootCap (\r
1788 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1789 );\r
5d73d92f 1790\r
a1d4bfcc 1791/**\r
1792 Print out information of the device root status information.\r
1793\r
1794 @param[in] PciExpressCap The pointer to the structure about the device.\r
1795\r
1796 @retval EFI_SUCCESS The operation was successful.\r
1797**/\r
5d73d92f 1798EFI_STATUS\r
1799ExplainPcieRootStatus (\r
1800 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1801 );\r
5d73d92f 1802\r
1803typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1804\r
1805typedef enum {\r
1806 FieldWidthUINT8,\r
1807 FieldWidthUINT16,\r
1808 FieldWidthUINT32\r
1809} PCIE_CAPREG_FIELD_WIDTH;\r
1810\r
1811typedef enum {\r
1812 PcieExplainTypeCommon,\r
1813 PcieExplainTypeDevice,\r
1814 PcieExplainTypeLink,\r
1815 PcieExplainTypeSlot,\r
1816 PcieExplainTypeRoot,\r
1817 PcieExplainTypeMax\r
1818} PCIE_EXPLAIN_TYPE;\r
1819\r
1820typedef struct\r
1821{\r
1822 UINT16 Token;\r
1823 UINTN Offset;\r
1824 PCIE_CAPREG_FIELD_WIDTH Width;\r
1825 PCIE_EXPLAIN_FUNCTION Func;\r
1826 PCIE_EXPLAIN_TYPE Type;\r
1827} PCIE_EXPLAIN_STRUCT;\r
1828\r
1829PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1830 {\r
1831 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1832 0x00,\r
1833 FieldWidthUINT8,\r
1834 NULL,\r
1835 PcieExplainTypeCommon\r
1836 },\r
1837 {\r
1838 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1839 0x01,\r
1840 FieldWidthUINT8,\r
1841 NULL,\r
1842 PcieExplainTypeCommon\r
1843 },\r
1844 {\r
1845 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1846 0x02,\r
1847 FieldWidthUINT16,\r
1848 ExplainPcieCapReg,\r
1849 PcieExplainTypeCommon\r
1850 },\r
1851 {\r
1852 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1853 0x04,\r
1854 FieldWidthUINT32,\r
1855 ExplainPcieDeviceCap,\r
1856 PcieExplainTypeDevice\r
1857 },\r
1858 {\r
1859 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1860 0x08,\r
1861 FieldWidthUINT16,\r
1862 ExplainPcieDeviceControl,\r
1863 PcieExplainTypeDevice\r
1864 },\r
1865 {\r
1866 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1867 0x0a,\r
1868 FieldWidthUINT16,\r
1869 ExplainPcieDeviceStatus,\r
1870 PcieExplainTypeDevice\r
1871 },\r
1872 {\r
1873 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1874 0x0c,\r
1875 FieldWidthUINT32,\r
1876 ExplainPcieLinkCap,\r
1877 PcieExplainTypeLink\r
1878 },\r
1879 {\r
1880 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1881 0x10,\r
1882 FieldWidthUINT16,\r
1883 ExplainPcieLinkControl,\r
1884 PcieExplainTypeLink\r
1885 },\r
1886 {\r
1887 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1888 0x12,\r
1889 FieldWidthUINT16,\r
1890 ExplainPcieLinkStatus,\r
1891 PcieExplainTypeLink\r
1892 },\r
1893 {\r
1894 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1895 0x14,\r
1896 FieldWidthUINT32,\r
1897 ExplainPcieSlotCap,\r
1898 PcieExplainTypeSlot\r
1899 },\r
1900 {\r
1901 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1902 0x18,\r
1903 FieldWidthUINT16,\r
1904 ExplainPcieSlotControl,\r
1905 PcieExplainTypeSlot\r
1906 },\r
1907 {\r
1908 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1909 0x1a,\r
1910 FieldWidthUINT16,\r
1911 ExplainPcieSlotStatus,\r
1912 PcieExplainTypeSlot\r
1913 },\r
1914 {\r
1915 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1916 0x1c,\r
1917 FieldWidthUINT16,\r
1918 ExplainPcieRootControl,\r
1919 PcieExplainTypeRoot\r
1920 },\r
1921 {\r
1922 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1923 0x1e,\r
1924 FieldWidthUINT16,\r
1925 ExplainPcieRootCap,\r
1926 PcieExplainTypeRoot\r
1927 },\r
1928 {\r
1929 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1930 0x20,\r
1931 FieldWidthUINT32,\r
1932 ExplainPcieRootStatus,\r
1933 PcieExplainTypeRoot\r
1934 },\r
1935 {\r
1936 0,\r
1937 0,\r
1938 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1939 NULL,\r
1940 PcieExplainTypeMax\r
1941 }\r
1942};\r
1943\r
1944//\r
1945// Global Variables\r
1946//\r
1947PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1948STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1949 {L"-s", TypeValue},\r
1950 {L"-i", TypeFlag},\r
1951 {NULL, TypeMax}\r
1952 };\r
1953\r
1954CHAR16 *DevicePortTypeTable[] = {\r
1955 L"PCI Express Endpoint",\r
1956 L"Legacy PCI Express Endpoint",\r
1957 L"Unknown Type",\r
1958 L"Unknonw Type",\r
1959 L"Root Port of PCI Express Root Complex",\r
1960 L"Upstream Port of PCI Express Switch",\r
1961 L"Downstream Port of PCI Express Switch",\r
1962 L"PCI Express to PCI/PCI-X Bridge",\r
1963 L"PCI/PCI-X to PCI Express Bridge",\r
1964 L"Root Complex Integrated Endpoint",\r
1965 L"Root Complex Event Collector"\r
1966};\r
1967\r
1968CHAR16 *L0sLatencyStrTable[] = {\r
1969 L"Less than 64ns",\r
1970 L"64ns to less than 128ns",\r
1971 L"128ns to less than 256ns",\r
1972 L"256ns to less than 512ns",\r
1973 L"512ns to less than 1us",\r
1974 L"1us to less than 2us",\r
1975 L"2us-4us",\r
1976 L"More than 4us"\r
1977};\r
1978\r
1979CHAR16 *L1LatencyStrTable[] = {\r
1980 L"Less than 1us",\r
1981 L"1us to less than 2us",\r
1982 L"2us to less than 4us",\r
1983 L"4us to less than 8us",\r
1984 L"8us to less than 16us",\r
1985 L"16us to less than 32us",\r
1986 L"32us-64us",\r
1987 L"More than 64us"\r
1988};\r
1989\r
1990CHAR16 *ASPMCtrlStrTable[] = {\r
1991 L"Disabled",\r
1992 L"L0s Entry Enabled",\r
1993 L"L1 Entry Enabled",\r
1994 L"L0s and L1 Entry Enabled"\r
1995};\r
1996\r
1997CHAR16 *SlotPwrLmtScaleTable[] = {\r
1998 L"1.0x",\r
1999 L"0.1x",\r
2000 L"0.01x",\r
2001 L"0.001x"\r
2002};\r
2003\r
2004CHAR16 *IndicatorTable[] = {\r
2005 L"Reserved",\r
2006 L"On",\r
2007 L"Blink",\r
2008 L"Off"\r
2009};\r
2010\r
2011\r
a1d4bfcc 2012/**\r
2013 Function for 'pci' command.\r
2014\r
2015 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2016 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2017**/\r
5d73d92f 2018SHELL_STATUS\r
2019EFIAPI\r
2020ShellCommandRunPci (\r
2021 IN EFI_HANDLE ImageHandle,\r
2022 IN EFI_SYSTEM_TABLE *SystemTable\r
2023 )\r
2024{\r
2025 UINT16 Segment;\r
2026 UINT16 Bus;\r
2027 UINT16 Device;\r
2028 UINT16 Func;\r
2029 UINT64 Address;\r
2030 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2031 EFI_STATUS Status;\r
2032 PCI_COMMON_HEADER PciHeader;\r
2033 PCI_CONFIG_SPACE ConfigSpace;\r
2034 UINTN ScreenCount;\r
2035 UINTN TempColumn;\r
2036 UINTN ScreenSize;\r
2037 BOOLEAN ExplainData;\r
2038 UINTN Index;\r
2039 UINTN SizeOfHeader;\r
2040 BOOLEAN PrintTitle;\r
2041 UINTN HandleBufSize;\r
2042 EFI_HANDLE *HandleBuf;\r
2043 UINTN HandleCount;\r
2044 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2045 UINT16 MinBus;\r
2046 UINT16 MaxBus;\r
2047 BOOLEAN IsEnd;\r
2048 LIST_ENTRY *Package;\r
2049 CHAR16 *ProblemParam;\r
2050 SHELL_STATUS ShellStatus;\r
5d73d92f 2051 CONST CHAR16 *Temp;\r
2052\r
2053 ShellStatus = SHELL_SUCCESS;\r
2054 Status = EFI_SUCCESS;\r
2055 Address = 0;\r
5d73d92f 2056 IoDev = NULL;\r
2057 HandleBuf = NULL;\r
2058 Package = NULL;\r
2059\r
2060 //\r
2061 // initialize the shell lib (we must be in non-auto-init...)\r
2062 //\r
2063 Status = ShellInitialize();\r
2064 ASSERT_EFI_ERROR(Status);\r
2065\r
2066 Status = CommandInit();\r
2067 ASSERT_EFI_ERROR(Status);\r
2068\r
2069 //\r
2070 // parse the command line\r
2071 //\r
2072 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2073 if (EFI_ERROR(Status)) {\r
2074 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2075 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2076 FreePool(ProblemParam);\r
2077 ShellStatus = SHELL_INVALID_PARAMETER;\r
2078 } else {\r
2079 ASSERT(FALSE);\r
2080 }\r
2081 } else {\r
2082\r
3737ac2b 2083 if (ShellCommandLineGetCount(Package) == 2) {\r
2084 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2085 ShellStatus = SHELL_INVALID_PARAMETER;\r
2086 goto Done;\r
2087 }\r
5d73d92f 2088\r
3737ac2b 2089 if (ShellCommandLineGetCount(Package) > 4) {\r
2090 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2091 ShellStatus = SHELL_INVALID_PARAMETER;\r
2092 goto Done;\r
2093 }\r
2094 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2095 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2096 ShellStatus = SHELL_INVALID_PARAMETER;\r
2097 goto Done;\r
2098 }\r
5d73d92f 2099 //\r
2100 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2101 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2102 // space for handles and call it again.\r
2103 //\r
2104 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2105 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2106 if (HandleBuf == NULL) {\r
2107 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2108 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2109 goto Done;\r
2110 }\r
2111\r
2112 Status = gBS->LocateHandle (\r
2113 ByProtocol,\r
2114 &gEfiPciRootBridgeIoProtocolGuid,\r
2115 NULL,\r
2116 &HandleBufSize,\r
2117 HandleBuf\r
2118 );\r
2119\r
2120 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2121 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2122 if (HandleBuf == NULL) {\r
2123 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2124 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2125 goto Done;\r
2126 }\r
2127\r
2128 Status = gBS->LocateHandle (\r
2129 ByProtocol,\r
2130 &gEfiPciRootBridgeIoProtocolGuid,\r
2131 NULL,\r
2132 &HandleBufSize,\r
2133 HandleBuf\r
2134 );\r
2135 }\r
2136\r
2137 if (EFI_ERROR (Status)) {\r
2138 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2139 ShellStatus = SHELL_NOT_FOUND;\r
2140 goto Done;\r
2141 }\r
2142\r
2143 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2144 //\r
2145 // Argument Count == 1(no other argument): enumerate all pci functions\r
2146 //\r
3737ac2b 2147 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2148 gST->ConOut->QueryMode (\r
2149 gST->ConOut,\r
2150 gST->ConOut->Mode->Mode,\r
2151 &TempColumn,\r
2152 &ScreenSize\r
2153 );\r
2154\r
2155 ScreenCount = 0;\r
2156 ScreenSize -= 4;\r
2157 if ((ScreenSize & 1) == 1) {\r
2158 ScreenSize -= 1;\r
2159 }\r
2160\r
2161 PrintTitle = TRUE;\r
2162\r
2163 //\r
2164 // For each handle, which decides a segment and a bus number range,\r
2165 // enumerate all devices on it.\r
2166 //\r
2167 for (Index = 0; Index < HandleCount; Index++) {\r
2168 Status = PciGetProtocolAndResource (\r
2169 HandleBuf[Index],\r
2170 &IoDev,\r
2171 &Descriptors\r
2172 );\r
2173 if (EFI_ERROR (Status)) {\r
2174 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2175 ShellStatus = SHELL_NOT_FOUND;\r
2176 goto Done;\r
2177 }\r
2178 //\r
2179 // No document say it's impossible for a RootBridgeIo protocol handle\r
2180 // to have more than one address space descriptors, so find out every\r
2181 // bus range and for each of them do device enumeration.\r
2182 //\r
2183 while (TRUE) {\r
2184 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2185\r
2186 if (EFI_ERROR (Status)) {\r
2187 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2188 ShellStatus = SHELL_NOT_FOUND;\r
2189 goto Done;\r
2190 }\r
2191\r
2192 if (IsEnd) {\r
2193 break;\r
2194 }\r
2195\r
2196 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2197 //\r
2198 // For each devices, enumerate all functions it contains\r
2199 //\r
2200 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2201 //\r
2202 // For each function, read its configuration space and print summary\r
2203 //\r
2204 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2205 if (ShellGetExecutionBreakFlag ()) {\r
2206 ShellStatus = SHELL_ABORTED;\r
2207 goto Done;\r
2208 }\r
2209 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2210 IoDev->Pci.Read (\r
2211 IoDev,\r
2212 EfiPciWidthUint16,\r
2213 Address,\r
2214 1,\r
2215 &PciHeader.VendorId\r
2216 );\r
2217\r
2218 //\r
2219 // If VendorId = 0xffff, there does not exist a device at this\r
2220 // location. For each device, if there is any function on it,\r
2221 // there must be 1 function at Function 0. So if Func = 0, there\r
2222 // will be no more functions in the same device, so we can break\r
2223 // loop to deal with the next device.\r
2224 //\r
2225 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2226 break;\r
2227 }\r
2228\r
2229 if (PciHeader.VendorId != 0xffff) {\r
2230\r
2231 if (PrintTitle) {\r
2232 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2233 PrintTitle = FALSE;\r
2234 }\r
2235\r
2236 IoDev->Pci.Read (\r
2237 IoDev,\r
2238 EfiPciWidthUint32,\r
2239 Address,\r
2240 sizeof (PciHeader) / sizeof (UINT32),\r
2241 &PciHeader\r
2242 );\r
2243\r
2244 ShellPrintHiiEx(\r
2245 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2246 IoDev->SegmentNumber,\r
2247 Bus,\r
2248 Device,\r
2249 Func\r
2250 );\r
2251\r
2252 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2253 ShellPrintHiiEx(\r
2254 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2255 PciHeader.VendorId,\r
2256 PciHeader.DeviceId,\r
2257 PciHeader.ClassCode[0]\r
2258 );\r
2259\r
2260 ScreenCount += 2;\r
2261 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2262 //\r
2263 // If ScreenSize == 0 we have the console redirected so don't\r
2264 // block updates\r
2265 //\r
2266 ScreenCount = 0;\r
2267 }\r
2268 //\r
2269 // If this is not a multi-function device, we can leave the loop\r
2270 // to deal with the next device.\r
2271 //\r
2272 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2273 break;\r
2274 }\r
2275 }\r
2276 }\r
2277 }\r
2278 }\r
2279 //\r
2280 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2281 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2282 // devices on all bus, we can leave loop.\r
2283 //\r
2284 if (Descriptors == NULL) {\r
2285 break;\r
2286 }\r
2287 }\r
2288 }\r
2289\r
2290 Status = EFI_SUCCESS;\r
2291 goto Done;\r
2292 }\r
2293\r
5d73d92f 2294 ExplainData = FALSE;\r
2295 Segment = 0;\r
2296 Bus = 0;\r
2297 Device = 0;\r
2298 Func = 0;\r
2299 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2300 ExplainData = TRUE;\r
2301 }\r
2302\r
2303 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2304 if (Temp != NULL) {\r
3737ac2b 2305 Segment = (UINT16) ShellStrToUintn (Temp);\r
5d73d92f 2306 }\r
2307\r
2308 //\r
2309 // The first Argument(except "-i") is assumed to be Bus number, second\r
2310 // to be Device number, and third to be Func number.\r
2311 //\r
2312 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2313 if (Temp != NULL) {\r
3737ac2b 2314 Bus = (UINT16)ShellStrToUintn(Temp);\r
5d73d92f 2315 if (Bus > MAX_BUS_NUMBER) {\r
2316 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2317 ShellStatus = SHELL_INVALID_PARAMETER;\r
2318 goto Done;\r
2319 }\r
2320 }\r
2321 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2322 if (Temp != NULL) {\r
3737ac2b 2323 Device = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2324 if (Device > MAX_DEVICE_NUMBER){\r
2325 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2326 ShellStatus = SHELL_INVALID_PARAMETER;\r
2327 goto Done;\r
2328 }\r
2329 }\r
2330\r
2331 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2332 if (Temp != NULL) {\r
3737ac2b 2333 Func = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2334 if (Func > MAX_FUNCTION_NUMBER){\r
2335 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2336 ShellStatus = SHELL_INVALID_PARAMETER;\r
2337 goto Done;\r
2338 }\r
2339 }\r
2340\r
2341 //\r
2342 // Find the protocol interface who's in charge of current segment, and its\r
2343 // bus range covers the current bus\r
2344 //\r
2345 Status = PciFindProtocolInterface (\r
2346 HandleBuf,\r
2347 HandleCount,\r
2348 Segment,\r
2349 Bus,\r
2350 &IoDev\r
2351 );\r
2352\r
2353 if (EFI_ERROR (Status)) {\r
2354 ShellPrintHiiEx(\r
2355 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
5d73d92f 2356 Segment,\r
2357 Bus\r
2358 );\r
2359 ShellStatus = SHELL_NOT_FOUND;\r
2360 goto Done;\r
2361 }\r
2362\r
2363 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2364 Status = IoDev->Pci.Read (\r
2365 IoDev,\r
2366 EfiPciWidthUint8,\r
2367 Address,\r
2368 sizeof (ConfigSpace),\r
2369 &ConfigSpace\r
2370 );\r
2371\r
2372 if (EFI_ERROR (Status)) {\r
2373 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2374 ShellStatus = SHELL_ACCESS_DENIED;\r
2375 goto Done;\r
2376 }\r
2377\r
2378 mConfigSpace = &ConfigSpace;\r
2379 ShellPrintHiiEx(\r
2380 -1,\r
2381 -1,\r
2382 NULL,\r
2383 STRING_TOKEN (STR_PCI_INFO),\r
2384 gShellDebug1HiiHandle,\r
2385 Segment,\r
2386 Bus,\r
2387 Device,\r
2388 Func,\r
2389 Segment,\r
2390 Bus,\r
2391 Device,\r
2392 Func\r
2393 );\r
2394\r
2395 //\r
2396 // Dump standard header of configuration space\r
2397 //\r
2398 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2399\r
a1d4bfcc 2400 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2401 ShellPrintEx(-1,-1, L"\r\n");\r
2402\r
2403 //\r
2404 // Dump device dependent Part of configuration space\r
2405 //\r
a1d4bfcc 2406 DumpHex (\r
5d73d92f 2407 2,\r
2408 SizeOfHeader,\r
2409 sizeof (ConfigSpace) - SizeOfHeader,\r
2410 ConfigSpace.Data\r
2411 );\r
2412\r
2413 //\r
2414 // If "-i" appears in command line, interpret data in configuration space\r
2415 //\r
2416 if (ExplainData) {\r
2417 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2418 }\r
2419 }\r
2420Done:\r
2421 if (HandleBuf != NULL) {\r
2422 FreePool (HandleBuf);\r
2423 }\r
2424 if (Package != NULL) {\r
2425 ShellCommandLineFreeVarList (Package);\r
2426 }\r
2427 mConfigSpace = NULL;\r
2428 return ShellStatus;\r
2429}\r
2430\r
a1d4bfcc 2431/**\r
5d73d92f 2432 This function finds out the protocol which is in charge of the given\r
2433 segment, and its bus range covers the current bus number. It lookes\r
2434 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2435 criteria is found.\r
2436\r
a1d4bfcc 2437 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2438 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2439 @param[in] Segment Segment number of device we are dealing with.\r
2440 @param[in] Bus Bus number of device we are dealing with.\r
2441 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2442\r
a1d4bfcc 2443 @retval EFI_SUCCESS The command completed successfully.\r
2444 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2445\r
2446**/\r
a1d4bfcc 2447EFI_STATUS\r
2448PciFindProtocolInterface (\r
2449 IN EFI_HANDLE *HandleBuf,\r
2450 IN UINTN HandleCount,\r
2451 IN UINT16 Segment,\r
2452 IN UINT16 Bus,\r
2453 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2454 )\r
5d73d92f 2455{\r
2456 UINTN Index;\r
2457 EFI_STATUS Status;\r
5d73d92f 2458 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2459 UINT16 MinBus;\r
2460 UINT16 MaxBus;\r
2461 BOOLEAN IsEnd;\r
2462\r
5d73d92f 2463 //\r
2464 // Go through all handles, until the one meets the criteria is found\r
2465 //\r
2466 for (Index = 0; Index < HandleCount; Index++) {\r
2467 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2468 if (EFI_ERROR (Status)) {\r
2469 return Status;\r
2470 }\r
2471 //\r
2472 // When Descriptors == NULL, the Configuration() is not implemented,\r
2473 // so we only check the Segment number\r
2474 //\r
2475 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2476 return EFI_SUCCESS;\r
2477 }\r
2478\r
2479 if ((*IoDev)->SegmentNumber != Segment) {\r
2480 continue;\r
2481 }\r
2482\r
2483 while (TRUE) {\r
2484 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2485 if (EFI_ERROR (Status)) {\r
2486 return Status;\r
2487 }\r
2488\r
2489 if (IsEnd) {\r
2490 break;\r
2491 }\r
2492\r
2493 if (MinBus <= Bus && MaxBus >= Bus) {\r
2c46dd23 2494 return EFI_SUCCESS;\r
5d73d92f 2495 }\r
2496 }\r
2497 }\r
2498\r
2c46dd23 2499 return EFI_NOT_FOUND;\r
5d73d92f 2500}\r
2501\r
a1d4bfcc 2502/**\r
2503 This function gets the protocol interface from the given handle, and\r
2504 obtains its address space descriptors.\r
2505\r
2506 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2507 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2508 @param[out] Descriptors Points to the address space descriptors.\r
2509\r
2510 @retval EFI_SUCCESS The command completed successfully\r
2511**/\r
5d73d92f 2512EFI_STATUS\r
2513PciGetProtocolAndResource (\r
2514 IN EFI_HANDLE Handle,\r
2515 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2516 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2517 )\r
5d73d92f 2518{\r
2519 EFI_STATUS Status;\r
2520\r
2521 //\r
2522 // Get inferface from protocol\r
2523 //\r
2524 Status = gBS->HandleProtocol (\r
2525 Handle,\r
2526 &gEfiPciRootBridgeIoProtocolGuid,\r
2527 (VOID**)IoDev\r
2528 );\r
2529\r
2530 if (EFI_ERROR (Status)) {\r
2531 return Status;\r
2532 }\r
2533 //\r
2534 // Call Configuration() to get address space descriptors\r
2535 //\r
2536 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2537 if (Status == EFI_UNSUPPORTED) {\r
2538 *Descriptors = NULL;\r
2539 return EFI_SUCCESS;\r
2540\r
2541 } else {\r
2542 return Status;\r
2543 }\r
2544}\r
2545\r
a1d4bfcc 2546/**\r
2547 This function get the next bus range of given address space descriptors.\r
2548 It also moves the pointer backward a node, to get prepared to be called\r
2549 again.\r
2550\r
4ff7e37b
ED		 2551 @param[in, out] Descriptors Points to current position of a serial of address space\r
2552 descriptors.\r
2553 @param[out] MinBus The lower range of bus number.\r
2554 @param[out] MaxBus The upper range of bus number.\r
2555 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 2556\r
2557 @retval EFI_SUCCESS The command completed successfully.\r
2558**/\r
5d73d92f 2559EFI_STATUS\r
2560PciGetNextBusRange (\r
2561 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2562 OUT UINT16 *MinBus,\r
2563 OUT UINT16 *MaxBus,\r
2564 OUT BOOLEAN *IsEnd\r
2565 )\r
5d73d92f 2566{\r
2567 *IsEnd = FALSE;\r
2568\r
2569 //\r
2570 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2571 // range is 0~PCI_MAX_BUS\r
2572 //\r
2573 if ((*Descriptors) == NULL) {\r
2574 *MinBus = 0;\r
2575 *MaxBus = PCI_MAX_BUS;\r
2576 return EFI_SUCCESS;\r
2577 }\r
2578 //\r
2579 // *Descriptors points to one or more address space descriptors, which\r
2580 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2581 // if a bus typed one is found and its bus range covers bus, this handle\r
2582 // is the handle we are looking for.\r
2583 //\r
5d73d92f 2584\r
2585 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2586 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2587 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2588 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2589 (*Descriptors)++;\r
3737ac2b 2590 return (EFI_SUCCESS);\r
5d73d92f 2591 }\r
2592\r
2593 (*Descriptors)++;\r
2594 }\r
2595\r
3737ac2b 2596 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2597 *IsEnd = TRUE;\r
2598 }\r
2599\r
5d73d92f 2600 return EFI_SUCCESS;\r
2601}\r
2602\r
a1d4bfcc 2603/**\r
5d73d92f 2604 Explain the data in PCI configuration space. The part which is common for\r
2605 PCI device and bridge is interpreted in this function. It calls other\r
2606 functions to interpret data unique for device or bridge.\r
2607\r
a1d4bfcc 2608 @param[in] ConfigSpace Data in PCI configuration space.\r
2609 @param[in] Address Address used to access configuration space of this PCI device.\r
2610 @param[in] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2611\r
a1d4bfcc 2612 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 2613**/\r
a1d4bfcc 2614EFI_STATUS\r
2615PciExplainData (\r
2616 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2617 IN UINT64 Address,\r
2618 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2619 )\r
5d73d92f 2620{\r
2621 PCI_COMMON_HEADER *Common;\r
2622 PCI_HEADER_TYPE HeaderType;\r
2623 EFI_STATUS Status;\r
2624 UINT8 CapPtr;\r
2625\r
2626 Common = &(ConfigSpace->Common);\r
2627\r
c37e0f16 2628 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 2629\r
2630 //\r
2631 // Print Vendor Id and Device Id\r
2632 //\r
2633 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2634 INDEX_OF (&(Common->VendorId)),\r
2635 Common->VendorId,\r
2636 INDEX_OF (&(Common->DeviceId)),\r
2637 Common->DeviceId\r
2638 );\r
2639\r
2640 //\r
2641 // Print register Command\r
2642 //\r
2643 PciExplainCommand (&(Common->Command));\r
2644\r
2645 //\r
2646 // Print register Status\r
2647 //\r
2648 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2649\r
2650 //\r
2651 // Print register Revision ID\r
2652 //\r
14b5e3fd 2653 ShellPrintEx(-1, -1, L"\r\n");\r
5d73d92f 2654 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2655 INDEX_OF (&(Common->RevisionId)),\r
2656 Common->RevisionId\r
2657 );\r
2658\r
2659 //\r
2660 // Print register BIST\r
2661 //\r
a1d4bfcc 2662 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2663 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2664 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
5d73d92f 2665 } else {\r
2666 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2667 }\r
2668 //\r
2669 // Print register Cache Line Size\r
2670 //\r
2671 ShellPrintHiiEx(-1, -1, NULL,\r
2672 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2673 gShellDebug1HiiHandle,\r
2674 INDEX_OF (&(Common->CacheLineSize)),\r
2675 Common->CacheLineSize\r
2676 );\r
2677\r
2678 //\r
2679 // Print register Latency Timer\r
2680 //\r
2681 ShellPrintHiiEx(-1, -1, NULL,\r
2682 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2683 gShellDebug1HiiHandle,\r
2684 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2685 Common->PrimaryLatencyTimer\r
2686 );\r
2687\r
2688 //\r
2689 // Print register Header Type\r
2690 //\r
2691 ShellPrintHiiEx(-1, -1, NULL,\r
2692 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2693 gShellDebug1HiiHandle,\r
2694 INDEX_OF (&(Common->HeaderType)),\r
2695 Common->HeaderType\r
2696 );\r
2697\r
2698 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2699 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2700\r
2701 } else {\r
2702 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2703 }\r
2704\r
2705 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2706 switch (HeaderType) {\r
2707 case PciDevice:\r
2708 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2709 break;\r
2710\r
2711 case PciP2pBridge:\r
2712 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2713 break;\r
2714\r
2715 case PciCardBusBridge:\r
2716 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2717 break;\r
2718\r
2719 default:\r
2720 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2721 HeaderType = PciUndefined;\r
2722 }\r
2723\r
2724 //\r
2725 // Print register Class Code\r
2726 //\r
2727 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2728 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
c37e0f16 2729 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 2730\r
2731 if (ShellGetExecutionBreakFlag()) {\r
2732 return EFI_SUCCESS;\r
2733 }\r
2734\r
2735 //\r
2736 // Interpret remaining part of PCI configuration header depending on\r
2737 // HeaderType\r
2738 //\r
2739 CapPtr = 0;\r
2740 Status = EFI_SUCCESS;\r
2741 switch (HeaderType) {\r
2742 case PciDevice:\r
2743 Status = PciExplainDeviceData (\r
2744 &(ConfigSpace->NonCommon.Device),\r
2745 Address,\r
2746 IoDev\r
2747 );\r
2748 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2749 break;\r
2750\r
2751 case PciP2pBridge:\r
2752 Status = PciExplainBridgeData (\r
2753 &(ConfigSpace->NonCommon.Bridge),\r
2754 Address,\r
2755 IoDev\r
2756 );\r
2757 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2758 break;\r
2759\r
2760 case PciCardBusBridge:\r
2761 Status = PciExplainCardBusData (\r
2762 &(ConfigSpace->NonCommon.CardBus),\r
2763 Address,\r
2764 IoDev\r
2765 );\r
2766 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2767 break;\r
d8f8021c 2768 case PciUndefined:\r
2769 default:\r
2770 break;\r
5d73d92f 2771 }\r
2772 //\r
2773 // If Status bit4 is 1, dump or explain capability structure\r
2774 //\r
2775 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2776 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2777 }\r
2778\r
2779 return Status;\r
2780}\r
2781\r
a1d4bfcc 2782/**\r
2783 Explain the device specific part of data in PCI configuration space.\r
2784\r
2785 @param[in] Device Data in PCI configuration space.\r
2786 @param[in] Address Address used to access configuration space of this PCI device.\r
2787 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2788\r
2789 @retval EFI_SUCCESS The command completed successfully.\r
2790**/\r
5d73d92f 2791EFI_STATUS\r
2792PciExplainDeviceData (\r
2793 IN PCI_DEVICE_HEADER *Device,\r
2794 IN UINT64 Address,\r
2795 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2796 )\r
5d73d92f 2797{\r
2798 UINTN Index;\r
2799 BOOLEAN BarExist;\r
2800 EFI_STATUS Status;\r
2801 UINTN BarCount;\r
2802\r
2803 //\r
2804 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2805 // exist. If these no Bar for this function, print "none", otherwise\r
2806 // list detail information about this Bar.\r
2807 //\r
2808 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2809\r
2810 BarExist = FALSE;\r
2811 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2812 for (Index = 0; Index < BarCount; Index++) {\r
2813 if (Device->Bar[Index] == 0) {\r
2814 continue;\r
2815 }\r
2816\r
2817 if (!BarExist) {\r
2818 BarExist = TRUE;\r
2819 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 2820 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 2821 }\r
2822\r
2823 Status = PciExplainBar (\r
2824 &(Device->Bar[Index]),\r
2825 &(mConfigSpace->Common.Command),\r
2826 Address,\r
2827 IoDev,\r
2828 &Index\r
2829 );\r
2830\r
2831 if (EFI_ERROR (Status)) {\r
2832 break;\r
2833 }\r
2834 }\r
2835\r
2836 if (!BarExist) {\r
2837 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2838\r
2839 } else {\r
c37e0f16 2840 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 2841 }\r
2842\r
2843 //\r
2844 // Print register Expansion ROM Base Address\r
2845 //\r
2846 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2847 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2848\r
2849 } else {\r
2850 ShellPrintHiiEx(-1, -1, NULL,\r
2851 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2852 gShellDebug1HiiHandle,\r
2853 INDEX_OF (&(Device->ROMBar)),\r
2854 Device->ROMBar\r
2855 );\r
2856 }\r
2857 //\r
2858 // Print register Cardbus CIS ptr\r
2859 //\r
2860 ShellPrintHiiEx(-1, -1, NULL,\r
2861 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2862 gShellDebug1HiiHandle,\r
2863 INDEX_OF (&(Device->CardBusCISPtr)),\r
2864 Device->CardBusCISPtr\r
2865 );\r
2866\r
2867 //\r
2868 // Print register Sub-vendor ID and subsystem ID\r
2869 //\r
2870 ShellPrintHiiEx(-1, -1, NULL,\r
2871 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2872 gShellDebug1HiiHandle,\r
2873 INDEX_OF (&(Device->SubVendorId)),\r
2874 Device->SubVendorId\r
2875 );\r
2876\r
2877 ShellPrintHiiEx(-1, -1, NULL,\r
2878 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2879 gShellDebug1HiiHandle,\r
2880 INDEX_OF (&(Device->SubSystemId)),\r
2881 Device->SubSystemId\r
2882 );\r
2883\r
2884 //\r
2885 // Print register Capabilities Ptr\r
2886 //\r
2887 ShellPrintHiiEx(-1, -1, NULL,\r
2888 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2889 gShellDebug1HiiHandle,\r
2890 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2891 Device->CapabilitiesPtr\r
2892 );\r
2893\r
2894 //\r
2895 // Print register Interrupt Line and interrupt pin\r
2896 //\r
2897 ShellPrintHiiEx(-1, -1, NULL,\r
2898 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2899 gShellDebug1HiiHandle,\r
2900 INDEX_OF (&(Device->InterruptLine)),\r
2901 Device->InterruptLine\r
2902 );\r
2903\r
2904 ShellPrintHiiEx(-1, -1, NULL,\r
2905 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2906 gShellDebug1HiiHandle,\r
2907 INDEX_OF (&(Device->InterruptPin)),\r
2908 Device->InterruptPin\r
2909 );\r
2910\r
2911 //\r
2912 // Print register Min_Gnt and Max_Lat\r
2913 //\r
2914 ShellPrintHiiEx(-1, -1, NULL,\r
2915 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2916 gShellDebug1HiiHandle,\r
2917 INDEX_OF (&(Device->MinGnt)),\r
2918 Device->MinGnt\r
2919 );\r
2920\r
2921 ShellPrintHiiEx(-1, -1, NULL,\r
2922 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2923 gShellDebug1HiiHandle,\r
2924 INDEX_OF (&(Device->MaxLat)),\r
2925 Device->MaxLat\r
2926 );\r
2927\r
2928 return EFI_SUCCESS;\r
2929}\r
2930\r
a1d4bfcc 2931/**\r
2932 Explain the bridge specific part of data in PCI configuration space.\r
2933\r
2934 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2935 @param[in] Address Address used to access configuration space of this PCI device.\r
2936 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2937\r
2938 @retval EFI_SUCCESS The command completed successfully.\r
2939**/\r
5d73d92f 2940EFI_STATUS\r
2941PciExplainBridgeData (\r
2942 IN PCI_BRIDGE_HEADER *Bridge,\r
2943 IN UINT64 Address,\r
2944 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2945 )\r
5d73d92f 2946{\r
2947 UINTN Index;\r
2948 BOOLEAN BarExist;\r
2949 UINTN BarCount;\r
2950 UINT32 IoAddress32;\r
2951 EFI_STATUS Status;\r
2952\r
2953 //\r
2954 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2955 // exist. If these no Bar for this function, print "none", otherwise\r
2956 // list detail information about this Bar.\r
2957 //\r
2958 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2959\r
2960 BarExist = FALSE;\r
2961 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
2962\r
2963 for (Index = 0; Index < BarCount; Index++) {\r
2964 if (Bridge->Bar[Index] == 0) {\r
2965 continue;\r
2966 }\r
2967\r
2968 if (!BarExist) {\r
2969 BarExist = TRUE;\r
2970 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 2971 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 2972 }\r
2973\r
2974 Status = PciExplainBar (\r
2975 &(Bridge->Bar[Index]),\r
2976 &(mConfigSpace->Common.Command),\r
2977 Address,\r
2978 IoDev,\r
2979 &Index\r
2980 );\r
2981\r
2982 if (EFI_ERROR (Status)) {\r
2983 break;\r
2984 }\r
2985 }\r
2986\r
2987 if (!BarExist) {\r
2988 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2989 } else {\r
c37e0f16 2990 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 2991 }\r
2992\r
2993 //\r
2994 // Expansion register ROM Base Address\r
2995 //\r
2996 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
2997 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
2998\r
2999 } else {\r
3000 ShellPrintHiiEx(-1, -1, NULL,\r
3001 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3002 gShellDebug1HiiHandle,\r
3003 INDEX_OF (&(Bridge->ROMBar)),\r
3004 Bridge->ROMBar\r
3005 );\r
3006 }\r
3007 //\r
3008 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3009 //\r
3010 ShellPrintHiiEx(-1, -1, NULL,\r
3011 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3012 gShellDebug1HiiHandle,\r
3013 INDEX_OF (&(Bridge->PrimaryBus)),\r
3014 INDEX_OF (&(Bridge->SecondaryBus)),\r
3015 INDEX_OF (&(Bridge->SubordinateBus))\r
3016 );\r
3017\r
c37e0f16 3018 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3019\r
3020 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3021 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3022 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3023\r
3024 //\r
3025 // Print register Secondary Latency Timer\r
3026 //\r
3027 ShellPrintHiiEx(-1, -1, NULL,\r
3028 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3029 gShellDebug1HiiHandle,\r
3030 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3031 Bridge->SecondaryLatencyTimer\r
3032 );\r
3033\r
3034 //\r
3035 // Print register Secondary Status\r
3036 //\r
3037 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3038\r
3039 //\r
3040 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3041 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3042 // base and limit address are listed.\r
3043 //\r
3044 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3045 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3046\r
3047 //\r
3048 // IO Base & Limit\r
3049 //\r
3050 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3051 IoAddress32 &= 0xfffff000;\r
3052 ShellPrintHiiEx(-1, -1, NULL,\r
3053 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3054 gShellDebug1HiiHandle,\r
3055 INDEX_OF (&(Bridge->IoBase)),\r
3056 IoAddress32\r
3057 );\r
3058\r
3059 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3060 IoAddress32 |= 0x00000fff;\r
3061 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3062\r
3063 //\r
3064 // Memory Base & Limit\r
3065 //\r
3066 ShellPrintHiiEx(-1, -1, NULL,\r
3067 STRING_TOKEN (STR_PCI2_MEMORY),\r
3068 gShellDebug1HiiHandle,\r
3069 INDEX_OF (&(Bridge->MemoryBase)),\r
3070 (Bridge->MemoryBase << 16) & 0xfff00000\r
3071 );\r
3072\r
3073 ShellPrintHiiEx(-1, -1, NULL,\r
3074 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3075 gShellDebug1HiiHandle,\r
3076 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3077 );\r
3078\r
3079 //\r
3080 // Pre-fetch-able Memory Base & Limit\r
3081 //\r
3082 ShellPrintHiiEx(-1, -1, NULL,\r
3083 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3084 gShellDebug1HiiHandle,\r
3085 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3086 Bridge->PrefetchableBaseUpper,\r
3087 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3088 );\r
3089\r
3090 ShellPrintHiiEx(-1, -1, NULL,\r
3091 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3092 gShellDebug1HiiHandle,\r
3093 Bridge->PrefetchableLimitUpper,\r
3094 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3095 );\r
3096\r
3097 //\r
3098 // Print register Capabilities Pointer\r
3099 //\r
3100 ShellPrintHiiEx(-1, -1, NULL,\r
3101 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3102 gShellDebug1HiiHandle,\r
3103 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3104 Bridge->CapabilitiesPtr\r
3105 );\r
3106\r
3107 //\r
3108 // Print register Bridge Control\r
3109 //\r
3110 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3111\r
3112 //\r
3113 // Print register Interrupt Line & PIN\r
3114 //\r
3115 ShellPrintHiiEx(-1, -1, NULL,\r
3116 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3117 gShellDebug1HiiHandle,\r
3118 INDEX_OF (&(Bridge->InterruptLine)),\r
3119 Bridge->InterruptLine\r
3120 );\r
3121\r
3122 ShellPrintHiiEx(-1, -1, NULL,\r
3123 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3124 gShellDebug1HiiHandle,\r
3125 INDEX_OF (&(Bridge->InterruptPin)),\r
3126 Bridge->InterruptPin\r
3127 );\r
3128\r
3129 return EFI_SUCCESS;\r
3130}\r
3131\r
a1d4bfcc 3132/**\r
3133 Explain the Base Address Register(Bar) in PCI configuration space.\r
3134\r
4ff7e37b
ED		 3135 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3136 @param[in] Command Points to the register Command.\r
3137 @param[in] Address Address used to access configuration space of this PCI device.\r
3138 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3139 @param[in, out] Index The Index.\r
a1d4bfcc 3140\r
3141 @retval EFI_SUCCESS The command completed successfully.\r
3142**/\r
5d73d92f 3143EFI_STATUS\r
3144PciExplainBar (\r
3145 IN UINT32 *Bar,\r
3146 IN UINT16 *Command,\r
3147 IN UINT64 Address,\r
3148 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3149 IN OUT UINTN *Index\r
3150 )\r
5d73d92f 3151{\r
3152 UINT16 OldCommand;\r
3153 UINT16 NewCommand;\r
3154 UINT64 Bar64;\r
3155 UINT32 OldBar32;\r
3156 UINT32 NewBar32;\r
3157 UINT64 OldBar64;\r
3158 UINT64 NewBar64;\r
3159 BOOLEAN IsMem;\r
3160 BOOLEAN IsBar32;\r
3161 UINT64 RegAddress;\r
3162\r
3163 IsBar32 = TRUE;\r
3164 Bar64 = 0;\r
3165 NewBar32 = 0;\r
3166 NewBar64 = 0;\r
3167\r
3168 //\r
3169 // According the bar type, list detail about this bar, for example: 32 or\r
3170 // 64 bits; pre-fetchable or not.\r
3171 //\r
3172 if ((*Bar & PCI_BIT_0) == 0) {\r
3173 //\r
3174 // This bar is of memory type\r
3175 //\r
3176 IsMem = TRUE;\r
3177\r
3178 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3179 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3180 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3181 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3182\r
3183 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3184 Bar64 = 0x0;\r
3185 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
46cb4043 3186 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
2b578de0 3187 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
5d73d92f 3188 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3189 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3190 IsBar32 = FALSE;\r
3191 *Index += 1;\r
3192\r
3193 } else {\r
3194 //\r
3195 // Reserved\r
3196 //\r
3197 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3198 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3199 }\r
3200\r
3201 if ((*Bar & PCI_BIT_3) == 0) {\r
3202 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3203\r
3204 } else {\r
3205 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3206 }\r
3207\r
3208 } else {\r
3209 //\r
3210 // This bar is of io type\r
3211 //\r
3212 IsMem = FALSE;\r
3213 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
c37e0f16 3214 ShellPrintEx (-1, -1, L"I/O ");\r
5d73d92f 3215 }\r
3216\r
3217 //\r
3218 // Get BAR length(or the amount of resource this bar demands for). To get\r
3219 // Bar length, first we should temporarily disable I/O and memory access\r
3220 // of this function(by set bits in the register Command), then write all\r
3221 // "1"s to this bar. The bar value read back is the amount of resource\r
3222 // this bar demands for.\r
3223 //\r
3224 //\r
3225 // Disable io & mem access\r
3226 //\r
3227 OldCommand = *Command;\r
3228 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3229 RegAddress = Address | INDEX_OF (Command);\r
3230 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3231\r
3232 RegAddress = Address | INDEX_OF (Bar);\r
3233\r
3234 //\r
3235 // Read after write the BAR to get the size\r
3236 //\r
3237 if (IsBar32) {\r
3238 OldBar32 = *Bar;\r
3239 NewBar32 = 0xffffffff;\r
3240\r
3241 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3242 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3243 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3244\r
3245 if (IsMem) {\r
3246 NewBar32 = NewBar32 & 0xfffffff0;\r
3247 NewBar32 = (~NewBar32) + 1;\r
3248\r
3249 } else {\r
3250 NewBar32 = NewBar32 & 0xfffffffc;\r
3251 NewBar32 = (~NewBar32) + 1;\r
3252 NewBar32 = NewBar32 & 0x0000ffff;\r
3253 }\r
3254 } else {\r
3255\r
3256 OldBar64 = 0x0;\r
3257 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
2b578de0 3258 NewBar64 = 0xffffffffffffffffULL;\r
5d73d92f 3259\r
3260 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3261 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3262 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3263\r
3264 if (IsMem) {\r
2b578de0 3265 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
5d73d92f 3266 NewBar64 = (~NewBar64) + 1;\r
3267\r
3268 } else {\r
2b578de0 3269 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
5d73d92f 3270 NewBar64 = (~NewBar64) + 1;\r
3271 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3272 }\r
3273 }\r
3274 //\r
3275 // Enable io & mem access\r
3276 //\r
3277 RegAddress = Address | INDEX_OF (Command);\r
3278 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3279\r
3280 if (IsMem) {\r
3281 if (IsBar32) {\r
3282 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3283 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3284\r
3285 } else {\r
46cb4043 3286 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
5d73d92f 3287 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
c37e0f16 3288 ShellPrintEx (-1, -1, L" ");\r
5d73d92f 3289 ShellPrintHiiEx(-1, -1, NULL,\r
3290 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3291 gShellDebug1HiiHandle,\r
46cb4043 3292 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
5d73d92f 3293 );\r
2b578de0 3294 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
5d73d92f 3295\r
3296 }\r
3297 } else {\r
3298 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3299 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3300 }\r
3301\r
3302 return EFI_SUCCESS;\r
3303}\r
3304\r
a1d4bfcc 3305/**\r
3306 Explain the cardbus specific part of data in PCI configuration space.\r
3307\r
3308 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3309 @param[in] Address Address used to access configuration space of this PCI device.\r
3310 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3311\r
3312 @retval EFI_SUCCESS The command completed successfully.\r
3313**/\r
5d73d92f 3314EFI_STATUS\r
3315PciExplainCardBusData (\r
3316 IN PCI_CARDBUS_HEADER *CardBus,\r
3317 IN UINT64 Address,\r
3318 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3319 )\r
5d73d92f 3320{\r
3321 BOOLEAN Io32Bit;\r
3322 PCI_CARDBUS_DATA *CardBusData;\r
3323\r
3324 ShellPrintHiiEx(-1, -1, NULL,\r
3325 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3326 gShellDebug1HiiHandle,\r
3327 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3328 CardBus->CardBusSocketReg\r
3329 );\r
3330\r
3331 //\r
3332 // Print Secondary Status\r
3333 //\r
3334 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3335\r
3336 //\r
3337 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3338 // Subordinate bus number\r
3339 //\r
3340 ShellPrintHiiEx(-1, -1, NULL,\r
3341 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3342 gShellDebug1HiiHandle,\r
3343 INDEX_OF (&(CardBus->PciBusNumber)),\r
3344 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3345 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3346 );\r
3347\r
c37e0f16 3348 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3349\r
3350 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3351 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3352 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3353\r
3354 //\r
3355 // Print CardBus Latency Timer\r
3356 //\r
3357 ShellPrintHiiEx(-1, -1, NULL,\r
3358 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3359 gShellDebug1HiiHandle,\r
3360 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3361 CardBus->CardBusLatencyTimer\r
3362 );\r
3363\r
3364 //\r
3365 // Print Memory/Io ranges this cardbus bridge forwards\r
3366 //\r
3367 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3368 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3369\r
3370 ShellPrintHiiEx(-1, -1, NULL,\r
3371 STRING_TOKEN (STR_PCI2_MEM_3),\r
3372 gShellDebug1HiiHandle,\r
3373 INDEX_OF (&(CardBus->MemoryBase0)),\r
3374 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3375 CardBus->MemoryBase0 & 0xfffff000,\r
3376 CardBus->MemoryLimit0 | 0x00000fff\r
3377 );\r
3378\r
3379 ShellPrintHiiEx(-1, -1, NULL,\r
3380 STRING_TOKEN (STR_PCI2_MEM_3),\r
3381 gShellDebug1HiiHandle,\r
3382 INDEX_OF (&(CardBus->MemoryBase1)),\r
3383 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3384 CardBus->MemoryBase1 & 0xfffff000,\r
3385 CardBus->MemoryLimit1 | 0x00000fff\r
3386 );\r
3387\r
3388 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3389 ShellPrintHiiEx(-1, -1, NULL,\r
3390 STRING_TOKEN (STR_PCI2_IO_2),\r
3391 gShellDebug1HiiHandle,\r
3392 INDEX_OF (&(CardBus->IoBase0)),\r
3393 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3394 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3395 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3396 );\r
3397\r
3398 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3399 ShellPrintHiiEx(-1, -1, NULL,\r
3400 STRING_TOKEN (STR_PCI2_IO_2),\r
3401 gShellDebug1HiiHandle,\r
3402 INDEX_OF (&(CardBus->IoBase1)),\r
3403 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3404 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3405 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3406 );\r
3407\r
3408 //\r
3409 // Print register Interrupt Line & PIN\r
3410 //\r
3411 ShellPrintHiiEx(-1, -1, NULL,\r
3412 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3413 gShellDebug1HiiHandle,\r
3414 INDEX_OF (&(CardBus->InterruptLine)),\r
3415 CardBus->InterruptLine,\r
3416 INDEX_OF (&(CardBus->InterruptPin)),\r
3417 CardBus->InterruptPin\r
3418 );\r
3419\r
3420 //\r
3421 // Print register Bridge Control\r
3422 //\r
3423 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3424\r
3425 //\r
3426 // Print some registers in data region of PCI configuration space for cardbus\r
3427 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3428 // Address.\r
3429 //\r
3430 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3431\r
3432 ShellPrintHiiEx(-1, -1, NULL,\r
3433 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3434 gShellDebug1HiiHandle,\r
3435 INDEX_OF (&(CardBusData->SubVendorId)),\r
3436 CardBusData->SubVendorId,\r
3437 INDEX_OF (&(CardBusData->SubSystemId)),\r
3438 CardBusData->SubSystemId\r
3439 );\r
3440\r
3441 ShellPrintHiiEx(-1, -1, NULL,\r
3442 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3443 gShellDebug1HiiHandle,\r
3444 INDEX_OF (&(CardBusData->LegacyBase)),\r
3445 CardBusData->LegacyBase\r
3446 );\r
3447\r
3448 return EFI_SUCCESS;\r
3449}\r
3450\r
a1d4bfcc 3451/**\r
3452 Explain each meaningful bit of register Status. The definition of Status is\r
3453 slightly different depending on the PCI header type.\r
3454\r
3455 @param[in] Status Points to the content of register Status.\r
3456 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3457 status).\r
3458 @param[in] HeaderType Header type of this PCI device.\r
3459\r
3460 @retval EFI_SUCCESS The command completed successfully.\r
3461**/\r
5d73d92f 3462EFI_STATUS\r
3463PciExplainStatus (\r
3464 IN UINT16 *Status,\r
3465 IN BOOLEAN MainStatus,\r
3466 IN PCI_HEADER_TYPE HeaderType\r
3467 )\r
5d73d92f 3468{\r
3469 if (MainStatus) {\r
3470 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3471\r
3472 } else {\r
3473 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3474 }\r
3475\r
3476 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3477\r
3478 //\r
3479 // Bit 5 is meaningless for CardBus Bridge\r
3480 //\r
3481 if (HeaderType == PciCardBusBridge) {\r
3482 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3483\r
3484 } else {\r
3485 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3486 }\r
3487\r
3488 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3489\r
3490 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3491 //\r
3492 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3493 //\r
3494 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3495 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3496 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3497\r
3498 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3499 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3500\r
3501 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3502 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3503\r
3504 } else {\r
3505 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3506 }\r
3507\r
3508 ShellPrintHiiEx(-1, -1, NULL,\r
3509 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3510 gShellDebug1HiiHandle,\r
3511 (*Status & PCI_BIT_11) != 0\r
3512 );\r
3513\r
3514 ShellPrintHiiEx(-1, -1, NULL,\r
3515 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3516 gShellDebug1HiiHandle,\r
3517 (*Status & PCI_BIT_12) != 0\r
3518 );\r
3519\r
3520 ShellPrintHiiEx(-1, -1, NULL,\r
3521 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3522 gShellDebug1HiiHandle,\r
3523 (*Status & PCI_BIT_13) != 0\r
3524 );\r
3525\r
3526 if (MainStatus) {\r
3527 ShellPrintHiiEx(-1, -1, NULL,\r
3528 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3529 gShellDebug1HiiHandle,\r
3530 (*Status & PCI_BIT_14) != 0\r
3531 );\r
3532\r
3533 } else {\r
3534 ShellPrintHiiEx(-1, -1, NULL,\r
3535 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3536 gShellDebug1HiiHandle,\r
3537 (*Status & PCI_BIT_14) != 0\r
3538 );\r
3539 }\r
3540\r
3541 ShellPrintHiiEx(-1, -1, NULL,\r
3542 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3543 gShellDebug1HiiHandle,\r
3544 (*Status & PCI_BIT_15) != 0\r
3545 );\r
3546\r
3547 return EFI_SUCCESS;\r
3548}\r
3549\r
a1d4bfcc 3550/**\r
5d73d92f 3551 Explain each meaningful bit of register Command.\r
3552\r
a1d4bfcc 3553 @param[in] Command Points to the content of register Command.\r
5d73d92f 3554\r
a1d4bfcc 3555 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 3556**/\r
a1d4bfcc 3557EFI_STATUS\r
3558PciExplainCommand (\r
3559 IN UINT16 *Command\r
3560 )\r
5d73d92f 3561{\r
3562 //\r
3563 // Print the binary value of register Command\r
3564 //\r
3565 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3566\r
3567 //\r
3568 // Explain register Command bit by bit\r
3569 //\r
3570 ShellPrintHiiEx(-1, -1, NULL,\r
3571 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3572 gShellDebug1HiiHandle,\r
3573 (*Command & PCI_BIT_0) != 0\r
3574 );\r
3575\r
3576 ShellPrintHiiEx(-1, -1, NULL,\r
3577 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3578 gShellDebug1HiiHandle,\r
3579 (*Command & PCI_BIT_1) != 0\r
3580 );\r
3581\r
3582 ShellPrintHiiEx(-1, -1, NULL,\r
3583 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3584 gShellDebug1HiiHandle,\r
3585 (*Command & PCI_BIT_2) != 0\r
3586 );\r
3587\r
3588 ShellPrintHiiEx(-1, -1, NULL,\r
3589 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3590 gShellDebug1HiiHandle,\r
3591 (*Command & PCI_BIT_3) != 0\r
3592 );\r
3593\r
3594 ShellPrintHiiEx(-1, -1, NULL,\r
3595 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3596 gShellDebug1HiiHandle,\r
3597 (*Command & PCI_BIT_4) != 0\r
3598 );\r
3599\r
3600 ShellPrintHiiEx(-1, -1, NULL,\r
3601 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3602 gShellDebug1HiiHandle,\r
3603 (*Command & PCI_BIT_5) != 0\r
3604 );\r
3605\r
3606 ShellPrintHiiEx(-1, -1, NULL,\r
3607 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3608 gShellDebug1HiiHandle,\r
3609 (*Command & PCI_BIT_6) != 0\r
3610 );\r
3611\r
3612 ShellPrintHiiEx(-1, -1, NULL,\r
3613 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3614 gShellDebug1HiiHandle,\r
3615 (*Command & PCI_BIT_7) != 0\r
3616 );\r
3617\r
3618 ShellPrintHiiEx(-1, -1, NULL,\r
3619 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3620 gShellDebug1HiiHandle,\r
3621 (*Command & PCI_BIT_8) != 0\r
3622 );\r
3623\r
3624 ShellPrintHiiEx(-1, -1, NULL,\r
3625 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3626 gShellDebug1HiiHandle,\r
3627 (*Command & PCI_BIT_9) != 0\r
3628 );\r
3629\r
3630 return EFI_SUCCESS;\r
3631}\r
3632\r
a1d4bfcc 3633/**\r
3634 Explain each meaningful bit of register Bridge Control.\r
3635\r
3636 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3637 @param[in] HeaderType The headertype.\r
3638\r
3639 @retval EFI_SUCCESS The command completed successfully.\r
3640**/\r
5d73d92f 3641EFI_STATUS\r
3642PciExplainBridgeControl (\r
3643 IN UINT16 *BridgeControl,\r
3644 IN PCI_HEADER_TYPE HeaderType\r
3645 )\r
5d73d92f 3646{\r
3647 ShellPrintHiiEx(-1, -1, NULL,\r
3648 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3649 gShellDebug1HiiHandle,\r
3650 INDEX_OF (BridgeControl),\r
3651 *BridgeControl\r
3652 );\r
3653\r
3654 ShellPrintHiiEx(-1, -1, NULL,\r
3655 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3656 gShellDebug1HiiHandle,\r
3657 (*BridgeControl & PCI_BIT_0) != 0\r
3658 );\r
3659 ShellPrintHiiEx(-1, -1, NULL,\r
3660 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3661 gShellDebug1HiiHandle,\r
3662 (*BridgeControl & PCI_BIT_1) != 0\r
3663 );\r
3664 ShellPrintHiiEx(-1, -1, NULL,\r
3665 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3666 gShellDebug1HiiHandle,\r
3667 (*BridgeControl & PCI_BIT_2) != 0\r
3668 );\r
3669 ShellPrintHiiEx(-1, -1, NULL,\r
3670 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3671 gShellDebug1HiiHandle,\r
3672 (*BridgeControl & PCI_BIT_3) != 0\r
3673 );\r
3674 ShellPrintHiiEx(-1, -1, NULL,\r
3675 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3676 gShellDebug1HiiHandle,\r
3677 (*BridgeControl & PCI_BIT_5) != 0\r
3678 );\r
3679\r
3680 //\r
3681 // Register Bridge Control has some slight differences between P2P bridge\r
3682 // and Cardbus bridge from bit 6 to bit 11.\r
3683 //\r
3684 if (HeaderType == PciP2pBridge) {\r
3685 ShellPrintHiiEx(-1, -1, NULL,\r
3686 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3687 gShellDebug1HiiHandle,\r
3688 (*BridgeControl & PCI_BIT_6) != 0\r
3689 );\r
3690 ShellPrintHiiEx(-1, -1, NULL,\r
3691 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3692 gShellDebug1HiiHandle,\r
3693 (*BridgeControl & PCI_BIT_7) != 0\r
3694 );\r
3695 ShellPrintHiiEx(-1, -1, NULL,\r
3696 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3697 gShellDebug1HiiHandle,\r
3698 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3699 );\r
3700 ShellPrintHiiEx(-1, -1, NULL,\r
3701 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3702 gShellDebug1HiiHandle,\r
3703 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3704 );\r
3705 ShellPrintHiiEx(-1, -1, NULL,\r
3706 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3707 gShellDebug1HiiHandle,\r
3708 (*BridgeControl & PCI_BIT_10) != 0\r
3709 );\r
3710 ShellPrintHiiEx(-1, -1, NULL,\r
3711 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3712 gShellDebug1HiiHandle,\r
3713 (*BridgeControl & PCI_BIT_11) != 0\r
3714 );\r
3715\r
3716 } else {\r
3717 ShellPrintHiiEx(-1, -1, NULL,\r
3718 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3719 gShellDebug1HiiHandle,\r
3720 (*BridgeControl & PCI_BIT_6) != 0\r
3721 );\r
3722 ShellPrintHiiEx(-1, -1, NULL,\r
3723 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3724 gShellDebug1HiiHandle,\r
3725 (*BridgeControl & PCI_BIT_7) != 0\r
3726 );\r
3727 ShellPrintHiiEx(-1, -1, NULL,\r
3728 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3729 gShellDebug1HiiHandle,\r
3730 (*BridgeControl & PCI_BIT_10) != 0\r
3731 );\r
3732 }\r
3733\r
3734 return EFI_SUCCESS;\r
3735}\r
3736\r
a1d4bfcc 3737/**\r
3738 Print each capability structure.\r
3739\r
3740 @param[in] IoDev The pointer to the deivce.\r
3741 @param[in] Address The address to start at.\r
3742 @param[in] CapPtr The offset from the address.\r
3743\r
3744 @retval EFI_SUCCESS The operation was successful.\r
3745**/\r
5d73d92f 3746EFI_STATUS\r
3747PciExplainCapabilityStruct (\r
3748 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3749 IN UINT64 Address,\r
3750 IN UINT8 CapPtr\r
3751 )\r
3752{\r
3753 UINT8 CapabilityPtr;\r
3754 UINT16 CapabilityEntry;\r
3755 UINT8 CapabilityID;\r
3756 UINT64 RegAddress;\r
3757\r
3758 CapabilityPtr = CapPtr;\r
3759\r
3760 //\r
3761 // Go through the Capability list\r
3762 //\r
3763 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3764 RegAddress = Address + CapabilityPtr;\r
3765 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3766\r
3767 CapabilityID = (UINT8) CapabilityEntry;\r
3768\r
3769 //\r
3770 // Explain PciExpress data\r
3771 //\r
3772 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3773 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3774 return EFI_SUCCESS;\r
3775 }\r
3776 //\r
3777 // Explain other capabilities here\r
3778 //\r
3779 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3780 }\r
3781\r
3782 return EFI_SUCCESS;\r
3783}\r
3784\r
a1d4bfcc 3785/**\r
3786 Print out information of the capability information.\r
3787\r
3788 @param[in] PciExpressCap The pointer to the structure about the device.\r
3789\r
3790 @retval EFI_SUCCESS The operation was successful.\r
3791**/\r
5d73d92f 3792EFI_STATUS\r
3793ExplainPcieCapReg (\r
3794 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3795 )\r
5d73d92f 3796{\r
3797 UINT16 PcieCapReg;\r
3798 CHAR16 *DevicePortType;\r
3799\r
3800 PcieCapReg = PciExpressCap->PcieCapReg;\r
c37e0f16
CP		 3801 ShellPrintEx (-1, -1,\r
3802 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
5d73d92f 3803 PCIE_CAP_VERSION (PcieCapReg)\r
3804 );\r
3805 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3806 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3807 } else {\r
3808 DevicePortType = L"Unknown Type";\r
3809 }\r
c37e0f16
CP		 3810 ShellPrintEx (-1, -1,\r
3811 L" Device/PortType(7:4): %E%s%N\r\n",\r
5d73d92f 3812 DevicePortType\r
3813 );\r
3814 //\r
3815 // 'Slot Implemented' is only valid for:\r
3816 // a) Root Port of PCI Express Root Complex, or\r
3817 // b) Downstream Port of PCI Express Switch\r
3818 //\r
3819 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3820 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
c37e0f16
CP		 3821 ShellPrintEx (-1, -1,\r
3822 L" Slot Implemented(8): %E%d%N\r\n",\r
5d73d92f 3823 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3824 );\r
3825 }\r
c37e0f16
CP		 3826 ShellPrintEx (-1, -1,\r
3827 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
5d73d92f 3828 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3829 );\r
3830 return EFI_SUCCESS;\r
3831}\r
3832\r
a1d4bfcc 3833/**\r
3834 Print out information of the device capability information.\r
3835\r
3836 @param[in] PciExpressCap The pointer to the structure about the device.\r
3837\r
3838 @retval EFI_SUCCESS The operation was successful.\r
3839**/\r
5d73d92f 3840EFI_STATUS\r
3841ExplainPcieDeviceCap (\r
3842 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3843 )\r
5d73d92f 3844{\r
3845 UINT16 PcieCapReg;\r
3846 UINT32 PcieDeviceCap;\r
3847 UINT8 DevicePortType;\r
3848 UINT8 L0sLatency;\r
3849 UINT8 L1Latency;\r
3850\r
3851 PcieCapReg = PciExpressCap->PcieCapReg;\r
3852 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3853 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
c37e0f16 3854 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
5d73d92f 3855 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
c37e0f16 3856 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
5d73d92f 3857 } else {\r
c37e0f16 3858 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 3859 }\r
c37e0f16
CP		 3860 ShellPrintEx (-1, -1,\r
3861 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
5d73d92f 3862 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3863 );\r
c37e0f16
CP		 3864 ShellPrintEx (-1, -1,\r
3865 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
5d73d92f 3866 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3867 );\r
3868 //\r
3869 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3870 //\r
3871 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
a1d4bfcc 3872 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3873 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
c37e0f16 3874 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
5d73d92f 3875 if (L0sLatency < 4) {\r
c37e0f16 3876 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
5d73d92f 3877 } else {\r
3878 if (L0sLatency < 7) {\r
c37e0f16 3879 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
5d73d92f 3880 } else {\r
c37e0f16 3881 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 3882 }\r
3883 }\r
c37e0f16 3884 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
5d73d92f 3885 if (L1Latency < 7) {\r
c37e0f16 3886 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
5d73d92f 3887 } else {\r
c37e0f16 3888 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 3889 }\r
3890 }\r
c37e0f16
CP		 3891 ShellPrintEx (-1, -1,\r
3892 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
5d73d92f 3893 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3894 );\r
3895 //\r
3896 // Only valid for Upstream Port:\r
3897 // a) Captured Slot Power Limit Value\r
3898 // b) Captured Slot Power Scale\r
3899 //\r
3900 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
c37e0f16
CP		 3901 ShellPrintEx (-1, -1,\r
3902 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
5d73d92f 3903 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3904 );\r
c37e0f16
CP		 3905 ShellPrintEx (-1, -1,\r
3906 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
5d73d92f 3907 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3908 );\r
3909 }\r
3910 //\r
3911 // Function Level Reset Capability is only valid for Endpoint\r
3912 //\r
3913 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
c37e0f16
CP		 3914 ShellPrintEx (-1, -1,\r
3915 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
5d73d92f 3916 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3917 );\r
3918 }\r
3919 return EFI_SUCCESS;\r
3920}\r
3921\r
a1d4bfcc 3922/**\r
3923 Print out information of the device control information.\r
3924\r
3925 @param[in] PciExpressCap The pointer to the structure about the device.\r
3926\r
3927 @retval EFI_SUCCESS The operation was successful.\r
3928**/\r
5d73d92f 3929EFI_STATUS\r
3930ExplainPcieDeviceControl (\r
3931 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3932 )\r
5d73d92f 3933{\r
3934 UINT16 PcieCapReg;\r
3935 UINT16 PcieDeviceControl;\r
3936\r
3937 PcieCapReg = PciExpressCap->PcieCapReg;\r
3938 PcieDeviceControl = PciExpressCap->DeviceControl;\r
c37e0f16
CP		 3939 ShellPrintEx (-1, -1,\r
3940 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
5d73d92f 3941 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3942 );\r
c37e0f16
CP		 3943 ShellPrintEx (-1, -1,\r
3944 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
5d73d92f 3945 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3946 );\r
c37e0f16
CP		 3947 ShellPrintEx (-1, -1,\r
3948 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
5d73d92f 3949 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3950 );\r
c37e0f16
CP		 3951 ShellPrintEx (-1, -1,\r
3952 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
5d73d92f 3953 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3954 );\r
c37e0f16
CP		 3955 ShellPrintEx (-1, -1,\r
3956 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
5d73d92f 3957 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3958 );\r
c37e0f16 3959 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
5d73d92f 3960 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 3961 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 3962 } else {\r
c37e0f16 3963 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 3964 }\r
c37e0f16
CP		 3965 ShellPrintEx (-1, -1,\r
3966 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
5d73d92f 3967 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
3968 );\r
c37e0f16
CP		 3969 ShellPrintEx (-1, -1,\r
3970 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
5d73d92f 3971 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
3972 );\r
c37e0f16
CP		 3973 ShellPrintEx (-1, -1,\r
3974 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
5d73d92f 3975 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
3976 );\r
c37e0f16
CP		 3977 ShellPrintEx (-1, -1,\r
3978 L" Enable No Snoop(11): %E%d%N\r\n",\r
5d73d92f 3979 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
3980 );\r
c37e0f16 3981 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
5d73d92f 3982 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 3983 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 3984 } else {\r
c37e0f16 3985 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 3986 }\r
3987 //\r
3988 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
3989 //\r
3990 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 3991 ShellPrintEx (-1, -1,\r
3992 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
5d73d92f 3993 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
3994 );\r
3995 }\r
3996 return EFI_SUCCESS;\r
3997}\r
3998\r
a1d4bfcc 3999/**\r
4000 Print out information of the device status information.\r
4001\r
4002 @param[in] PciExpressCap The pointer to the structure about the device.\r
4003\r
4004 @retval EFI_SUCCESS The operation was successful.\r
4005**/\r
5d73d92f 4006EFI_STATUS\r
4007ExplainPcieDeviceStatus (\r
4008 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4009 )\r
5d73d92f 4010{\r
4011 UINT16 PcieDeviceStatus;\r
4012\r
4013 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
c37e0f16
CP		 4014 ShellPrintEx (-1, -1,\r
4015 L" Correctable Error Detected(0): %E%d%N\r\n",\r
5d73d92f 4016 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4017 );\r
c37e0f16
CP		 4018 ShellPrintEx (-1, -1,\r
4019 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
5d73d92f 4020 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4021 );\r
c37e0f16
CP		 4022 ShellPrintEx (-1, -1,\r
4023 L" Fatal Error Detected(2): %E%d%N\r\n",\r
5d73d92f 4024 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4025 );\r
c37e0f16
CP		 4026 ShellPrintEx (-1, -1,\r
4027 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
5d73d92f 4028 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4029 );\r
c37e0f16
CP		 4030 ShellPrintEx (-1, -1,\r
4031 L" AUX Power Detected(4): %E%d%N\r\n",\r
5d73d92f 4032 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4033 );\r
c37e0f16
CP		 4034 ShellPrintEx (-1, -1,\r
4035 L" Transactions Pending(5): %E%d%N\r\n",\r
5d73d92f 4036 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4037 );\r
4038 return EFI_SUCCESS;\r
4039}\r
4040\r
a1d4bfcc 4041/**\r
4042 Print out information of the device link information.\r
4043\r
4044 @param[in] PciExpressCap The pointer to the structure about the device.\r
4045\r
4046 @retval EFI_SUCCESS The operation was successful.\r
4047**/\r
5d73d92f 4048EFI_STATUS\r
4049ExplainPcieLinkCap (\r
4050 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4051 )\r
5d73d92f 4052{\r
4053 UINT32 PcieLinkCap;\r
541ddf44 4054 CHAR16 *MaxLinkSpeed;\r
a1d4bfcc 4055 CHAR16 *AspmValue;\r
5d73d92f 4056\r
4057 PcieLinkCap = PciExpressCap->LinkCap;\r
541ddf44 4058 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
5d73d92f 4059 case 1:\r
541ddf44 4060 MaxLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4061 break;\r
4062 case 2:\r
541ddf44
CP		 4063 MaxLinkSpeed = L"5.0 GT/s";\r
4064 break;\r
4065 case 3:\r
4066 MaxLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4067 break;\r
4068 default:\r
541ddf44 4069 MaxLinkSpeed = L"Unknown";\r
5d73d92f 4070 break;\r
4071 }\r
c37e0f16 4072 ShellPrintEx (-1, -1,\r
541ddf44
CP		 4073 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4074 MaxLinkSpeed\r
5d73d92f 4075 );\r
c37e0f16
CP		 4076 ShellPrintEx (-1, -1,\r
4077 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4078 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4079 );\r
4080 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
541ddf44
CP		 4081 case 0:\r
4082 AspmValue = L"Not";\r
4083 break;\r
5d73d92f 4084 case 1:\r
541ddf44
CP		 4085 AspmValue = L"L0s";\r
4086 break;\r
4087 case 2:\r
4088 AspmValue = L"L1";\r
5d73d92f 4089 break;\r
4090 case 3:\r
a1d4bfcc 4091 AspmValue = L"L0s and L1";\r
5d73d92f 4092 break;\r
4093 default:\r
a1d4bfcc 4094 AspmValue = L"Reserved";\r
5d73d92f 4095 break;\r
4096 }\r
c37e0f16
CP		 4097 ShellPrintEx (-1, -1,\r
4098 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
a1d4bfcc 4099 AspmValue\r
5d73d92f 4100 );\r
c37e0f16
CP		 4101 ShellPrintEx (-1, -1,\r
4102 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
a1d4bfcc 4103 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4104 );\r
c37e0f16
CP		 4105 ShellPrintEx (-1, -1,\r
4106 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
a1d4bfcc 4107 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4108 );\r
c37e0f16
CP		 4109 ShellPrintEx (-1, -1,\r
4110 L" Clock Power Management(18): %E%d%N\r\n",\r
5d73d92f 4111 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4112 );\r
c37e0f16
CP		 4113 ShellPrintEx (-1, -1,\r
4114 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
5d73d92f 4115 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4116 );\r
c37e0f16
CP		 4117 ShellPrintEx (-1, -1,\r
4118 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
5d73d92f 4119 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4120 );\r
c37e0f16
CP		 4121 ShellPrintEx (-1, -1,\r
4122 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
5d73d92f 4123 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4124 );\r
c37e0f16
CP		 4125 ShellPrintEx (-1, -1,\r
4126 L" Port Number(31:24): %E0x%02x%N\r\n",\r
5d73d92f 4127 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4128 );\r
4129 return EFI_SUCCESS;\r
4130}\r
4131\r
a1d4bfcc 4132/**\r
4133 Print out information of the device link control information.\r
4134\r
4135 @param[in] PciExpressCap The pointer to the structure about the device.\r
4136\r
4137 @retval EFI_SUCCESS The operation was successful.\r
4138**/\r
5d73d92f 4139EFI_STATUS\r
4140ExplainPcieLinkControl (\r
4141 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4142 )\r
5d73d92f 4143{\r
4144 UINT16 PcieLinkControl;\r
4145 UINT8 DevicePortType;\r
4146\r
4147 PcieLinkControl = PciExpressCap->LinkControl;\r
4148 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
c37e0f16
CP		 4149 ShellPrintEx (-1, -1,\r
4150 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
5d73d92f 4151 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4152 );\r
4153 //\r
4154 // RCB is not applicable to switches\r
4155 //\r
4156 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
c37e0f16
CP		 4157 ShellPrintEx (-1, -1,\r
4158 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
5d73d92f 4159 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4160 );\r
4161 }\r
4162 //\r
4163 // Link Disable is reserved on\r
4164 // a) Endpoints\r
4165 // b) PCI Express to PCI/PCI-X bridges\r
4166 // c) Upstream Ports of Switches\r
4167 //\r
4168 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4169 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4170 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 4171 ShellPrintEx (-1, -1,\r
4172 L" Link Disable(4): %E%d%N\r\n",\r
5d73d92f 4173 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4174 );\r
4175 }\r
c37e0f16
CP		 4176 ShellPrintEx (-1, -1,\r
4177 L" Common Clock Configuration(6): %E%d%N\r\n",\r
5d73d92f 4178 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4179 );\r
c37e0f16
CP		 4180 ShellPrintEx (-1, -1,\r
4181 L" Extended Synch(7): %E%d%N\r\n",\r
5d73d92f 4182 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4183 );\r
c37e0f16
CP		 4184 ShellPrintEx (-1, -1,\r
4185 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
5d73d92f 4186 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4187 );\r
c37e0f16
CP		 4188 ShellPrintEx (-1, -1,\r
4189 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
5d73d92f 4190 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4191 );\r
c37e0f16
CP		 4192 ShellPrintEx (-1, -1,\r
4193 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
5d73d92f 4194 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4195 );\r
c37e0f16
CP		 4196 ShellPrintEx (-1, -1,\r
4197 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
5d73d92f 4198 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4199 );\r
4200 return EFI_SUCCESS;\r
4201}\r
4202\r
a1d4bfcc 4203/**\r
4204 Print out information of the device link status information.\r
4205\r
4206 @param[in] PciExpressCap The pointer to the structure about the device.\r
4207\r
4208 @retval EFI_SUCCESS The operation was successful.\r
4209**/\r
5d73d92f 4210EFI_STATUS\r
4211ExplainPcieLinkStatus (\r
4212 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4213 )\r
5d73d92f 4214{\r
4215 UINT16 PcieLinkStatus;\r
541ddf44 4216 CHAR16 *CurLinkSpeed;\r
5d73d92f 4217\r
4218 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4219 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4220 case 1:\r
541ddf44 4221 CurLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4222 break;\r
4223 case 2:\r
541ddf44
CP		 4224 CurLinkSpeed = L"5.0 GT/s";\r
4225 break;\r
4226 case 3:\r
4227 CurLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4228 break;\r
4229 default:\r
541ddf44 4230 CurLinkSpeed = L"Reserved";\r
5d73d92f 4231 break;\r
4232 }\r
c37e0f16
CP		 4233 ShellPrintEx (-1, -1,\r
4234 L" Current Link Speed(3:0): %E%s%N\r\n",\r
541ddf44 4235 CurLinkSpeed\r
5d73d92f 4236 );\r
c37e0f16
CP		 4237 ShellPrintEx (-1, -1,\r
4238 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4239 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4240 );\r
c37e0f16
CP		 4241 ShellPrintEx (-1, -1,\r
4242 L" Link Training(11): %E%d%N\r\n",\r
5d73d92f 4243 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4244 );\r
c37e0f16
CP		 4245 ShellPrintEx (-1, -1,\r
4246 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
5d73d92f 4247 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4248 );\r
c37e0f16
CP		 4249 ShellPrintEx (-1, -1,\r
4250 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
5d73d92f 4251 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4252 );\r
c37e0f16
CP		 4253 ShellPrintEx (-1, -1,\r
4254 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
5d73d92f 4255 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4256 );\r
c37e0f16
CP		 4257 ShellPrintEx (-1, -1,\r
4258 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
5d73d92f 4259 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4260 );\r
4261 return EFI_SUCCESS;\r
4262}\r
4263\r
a1d4bfcc 4264/**\r
4265 Print out information of the device slot information.\r
4266\r
4267 @param[in] PciExpressCap The pointer to the structure about the device.\r
4268\r
4269 @retval EFI_SUCCESS The operation was successful.\r
4270**/\r
5d73d92f 4271EFI_STATUS\r
4272ExplainPcieSlotCap (\r
4273 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4274 )\r
5d73d92f 4275{\r
4276 UINT32 PcieSlotCap;\r
4277\r
4278 PcieSlotCap = PciExpressCap->SlotCap;\r
4279\r
c37e0f16
CP		 4280 ShellPrintEx (-1, -1,\r
4281 L" Attention Button Present(0): %E%d%N\r\n",\r
5d73d92f 4282 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4283 );\r
c37e0f16
CP		 4284 ShellPrintEx (-1, -1,\r
4285 L" Power Controller Present(1): %E%d%N\r\n",\r
5d73d92f 4286 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4287 );\r
c37e0f16
CP		 4288 ShellPrintEx (-1, -1,\r
4289 L" MRL Sensor Present(2): %E%d%N\r\n",\r
5d73d92f 4290 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4291 );\r
c37e0f16
CP		 4292 ShellPrintEx (-1, -1,\r
4293 L" Attention Indicator Present(3): %E%d%N\r\n",\r
5d73d92f 4294 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4295 );\r
c37e0f16
CP		 4296 ShellPrintEx (-1, -1,\r
4297 L" Power Indicator Present(4): %E%d%N\r\n",\r
5d73d92f 4298 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4299 );\r
c37e0f16
CP		 4300 ShellPrintEx (-1, -1,\r
4301 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
5d73d92f 4302 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4303 );\r
c37e0f16
CP		 4304 ShellPrintEx (-1, -1,\r
4305 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
5d73d92f 4306 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4307 );\r
c37e0f16
CP		 4308 ShellPrintEx (-1, -1,\r
4309 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
5d73d92f 4310 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4311 );\r
c37e0f16
CP		 4312 ShellPrintEx (-1, -1,\r
4313 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
5d73d92f 4314 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4315 );\r
c37e0f16
CP		 4316 ShellPrintEx (-1, -1,\r
4317 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
5d73d92f 4318 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4319 );\r
c37e0f16
CP		 4320 ShellPrintEx (-1, -1,\r
4321 L" No Command Completed Support(18): %E%d%N\r\n",\r
5d73d92f 4322 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4323 );\r
c37e0f16
CP		 4324 ShellPrintEx (-1, -1,\r
4325 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
5d73d92f 4326 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4327 );\r
4328\r
4329 return EFI_SUCCESS;\r
4330}\r
4331\r
a1d4bfcc 4332/**\r
4333 Print out information of the device slot control information.\r
4334\r
4335 @param[in] PciExpressCap The pointer to the structure about the device.\r
4336\r
4337 @retval EFI_SUCCESS The operation was successful.\r
4338**/\r
5d73d92f 4339EFI_STATUS\r
4340ExplainPcieSlotControl (\r
4341 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4342 )\r
5d73d92f 4343{\r
4344 UINT16 PcieSlotControl;\r
4345\r
4346 PcieSlotControl = PciExpressCap->SlotControl;\r
c37e0f16
CP		 4347 ShellPrintEx (-1, -1,\r
4348 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
5d73d92f 4349 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4350 );\r
c37e0f16
CP		 4351 ShellPrintEx (-1, -1,\r
4352 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
5d73d92f 4353 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4354 );\r
c37e0f16
CP		 4355 ShellPrintEx (-1, -1,\r
4356 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
5d73d92f 4357 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4358 );\r
c37e0f16
CP		 4359 ShellPrintEx (-1, -1,\r
4360 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
5d73d92f 4361 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4362 );\r
c37e0f16
CP		 4363 ShellPrintEx (-1, -1,\r
4364 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
5d73d92f 4365 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4366 );\r
c37e0f16
CP		 4367 ShellPrintEx (-1, -1,\r
4368 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
5d73d92f 4369 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4370 );\r
c37e0f16
CP		 4371 ShellPrintEx (-1, -1,\r
4372 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
5d73d92f 4373 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4374 );\r
c37e0f16
CP		 4375 ShellPrintEx (-1, -1,\r
4376 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
5d73d92f 4377 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4378 );\r
c37e0f16 4379 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
5d73d92f 4380 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
c37e0f16 4381 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
5d73d92f 4382 } else {\r
c37e0f16 4383 ShellPrintEx (-1, -1, L"On%N\r\n");\r
5d73d92f 4384 }\r
c37e0f16
CP		 4385 ShellPrintEx (-1, -1,\r
4386 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
5d73d92f 4387 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4388 );\r
c37e0f16
CP		 4389 ShellPrintEx (-1, -1,\r
4390 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
5d73d92f 4391 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4392 );\r
4393 return EFI_SUCCESS;\r
4394}\r
4395\r
a1d4bfcc 4396/**\r
4397 Print out information of the device slot status information.\r
4398\r
4399 @param[in] PciExpressCap The pointer to the structure about the device.\r
4400\r
4401 @retval EFI_SUCCESS The operation was successful.\r
4402**/\r
5d73d92f 4403EFI_STATUS\r
4404ExplainPcieSlotStatus (\r
4405 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4406 )\r
5d73d92f 4407{\r
4408 UINT16 PcieSlotStatus;\r
4409\r
4410 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4411\r
c37e0f16
CP		 4412 ShellPrintEx (-1, -1,\r
4413 L" Attention Button Pressed(0): %E%d%N\r\n",\r
5d73d92f 4414 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4415 );\r
c37e0f16
CP		 4416 ShellPrintEx (-1, -1,\r
4417 L" Power Fault Detected(1): %E%d%N\r\n",\r
5d73d92f 4418 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4419 );\r
c37e0f16
CP		 4420 ShellPrintEx (-1, -1,\r
4421 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
5d73d92f 4422 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4423 );\r
c37e0f16
CP		 4424 ShellPrintEx (-1, -1,\r
4425 L" Presence Detect Changed(3): %E%d%N\r\n",\r
5d73d92f 4426 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4427 );\r
c37e0f16
CP		 4428 ShellPrintEx (-1, -1,\r
4429 L" Command Completed(4): %E%d%N\r\n",\r
5d73d92f 4430 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4431 );\r
c37e0f16 4432 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
5d73d92f 4433 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
c37e0f16 4434 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
5d73d92f 4435 } else {\r
c37e0f16 4436 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
5d73d92f 4437 }\r
c37e0f16 4438 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
5d73d92f 4439 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
c37e0f16 4440 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
5d73d92f 4441 } else {\r
c37e0f16 4442 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
5d73d92f 4443 }\r
c37e0f16 4444 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
5d73d92f 4445 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
c37e0f16 4446 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
5d73d92f 4447 } else {\r
c37e0f16 4448 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
5d73d92f 4449 }\r
c37e0f16
CP		 4450 ShellPrintEx (-1, -1,\r
4451 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
5d73d92f 4452 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4453 );\r
4454 return EFI_SUCCESS;\r
4455}\r
4456\r
a1d4bfcc 4457/**\r
4458 Print out information of the device root information.\r
4459\r
4460 @param[in] PciExpressCap The pointer to the structure about the device.\r
4461\r
4462 @retval EFI_SUCCESS The operation was successful.\r
4463**/\r
5d73d92f 4464EFI_STATUS\r
4465ExplainPcieRootControl (\r
4466 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4467 )\r
5d73d92f 4468{\r
4469 UINT16 PcieRootControl;\r
4470\r
4471 PcieRootControl = PciExpressCap->RootControl;\r
4472\r
c37e0f16
CP		 4473 ShellPrintEx (-1, -1,\r
4474 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
5d73d92f 4475 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4476 );\r
c37e0f16
CP		 4477 ShellPrintEx (-1, -1,\r
4478 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
5d73d92f 4479 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4480 );\r
c37e0f16
CP		 4481 ShellPrintEx (-1, -1,\r
4482 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
5d73d92f 4483 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4484 );\r
c37e0f16
CP		 4485 ShellPrintEx (-1, -1,\r
4486 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
5d73d92f 4487 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4488 );\r
c37e0f16
CP		 4489 ShellPrintEx (-1, -1,\r
4490 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
5d73d92f 4491 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4492 );\r
4493\r
4494 return EFI_SUCCESS;\r
4495}\r
4496\r
a1d4bfcc 4497/**\r
4498 Print out information of the device root capability information.\r
4499\r
4500 @param[in] PciExpressCap The pointer to the structure about the device.\r
4501\r
4502 @retval EFI_SUCCESS The operation was successful.\r
4503**/\r
5d73d92f 4504EFI_STATUS\r
4505ExplainPcieRootCap (\r
4506 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4507 )\r
5d73d92f 4508{\r
4509 UINT16 PcieRootCap;\r
4510\r
4511 PcieRootCap = PciExpressCap->RsvdP;\r
4512\r
c37e0f16
CP		 4513 ShellPrintEx (-1, -1,\r
4514 L" CRS Software Visibility(0): %E%d%N\r\n",\r
5d73d92f 4515 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4516 );\r
4517\r
4518 return EFI_SUCCESS;\r
4519}\r
4520\r
a1d4bfcc 4521/**\r
4522 Print out information of the device root status information.\r
4523\r
4524 @param[in] PciExpressCap The pointer to the structure about the device.\r
4525\r
4526 @retval EFI_SUCCESS The operation was successful.\r
4527**/\r
5d73d92f 4528EFI_STATUS\r
4529ExplainPcieRootStatus (\r
4530 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4531 )\r
5d73d92f 4532{\r
4533 UINT32 PcieRootStatus;\r
4534\r
4535 PcieRootStatus = PciExpressCap->RootStatus;\r
4536\r
c37e0f16
CP		 4537 ShellPrintEx (-1, -1,\r
4538 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
5d73d92f 4539 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4540 );\r
c37e0f16
CP		 4541 ShellPrintEx (-1, -1,\r
4542 L" PME Status(16): %E%d%N\r\n",\r
5d73d92f 4543 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4544 );\r
c37e0f16
CP		 4545 ShellPrintEx (-1, -1,\r
4546 L" PME Pending(17): %E%d%N\r\n",\r
5d73d92f 4547 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4548 );\r
4549 return EFI_SUCCESS;\r
4550}\r
4551\r
a1d4bfcc 4552/**\r
4553 Display Pcie device structure.\r
4554\r
4555 @param[in] IoDev The pointer to the root pci protocol.\r
4556 @param[in] Address The Address to start at.\r
4557 @param[in] CapabilityPtr The offset from the address to start.\r
4558**/\r
5d73d92f 4559EFI_STATUS\r
4560PciExplainPciExpress (\r
4561 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4562 IN UINT64 Address,\r
4563 IN UINT8 CapabilityPtr\r
4564 )\r
4565{\r
4566\r
4567 PCIE_CAP_STURCTURE PciExpressCap;\r
4568 EFI_STATUS Status;\r
4569 UINT64 CapRegAddress;\r
4570 UINT8 Bus;\r
4571 UINT8 Dev;\r
4572 UINT8 Func;\r
4573 UINT8 *ExRegBuffer;\r
4574 UINTN ExtendRegSize;\r
4575 UINT64 Pciex_Address;\r
4576 UINT8 DevicePortType;\r
4577 UINTN Index;\r
4578 UINT8 *RegAddr;\r
4579 UINTN RegValue;\r
4580\r
4581 CapRegAddress = Address + CapabilityPtr;\r
4582 IoDev->Pci.Read (\r
4583 IoDev,\r
4584 EfiPciWidthUint32,\r
4585 CapRegAddress,\r
4586 sizeof (PciExpressCap) / sizeof (UINT32),\r
4587 &PciExpressCap\r
4588 );\r
4589\r
4590 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4591\r
c37e0f16 4592 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
5d73d92f 4593\r
4594 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4595 if (ShellGetExecutionBreakFlag()) {\r
4596 goto Done;\r
4597 }\r
4598 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4599 switch (PcieExplainList[Index].Width) {\r
4600 case FieldWidthUINT8:\r
4601 RegValue = *(UINT8 *) RegAddr;\r
4602 break;\r
4603 case FieldWidthUINT16:\r
4604 RegValue = *(UINT16 *) RegAddr;\r
4605 break;\r
4606 case FieldWidthUINT32:\r
4607 RegValue = *(UINT32 *) RegAddr;\r
4608 break;\r
4609 default:\r
4610 RegValue = 0;\r
4611 break;\r
4612 }\r
4613 ShellPrintHiiEx(-1, -1, NULL,\r
4614 PcieExplainList[Index].Token,\r
4615 gShellDebug1HiiHandle,\r
4616 PcieExplainList[Index].Offset,\r
4617 RegValue\r
4618 );\r
4619 if (PcieExplainList[Index].Func == NULL) {\r
4620 continue;\r
4621 }\r
4622 switch (PcieExplainList[Index].Type) {\r
4623 case PcieExplainTypeLink:\r
4624 //\r
4625 // Link registers should not be used by\r
4626 // a) Root Complex Integrated Endpoint\r
4627 // b) Root Complex Event Collector\r
4628 //\r
4629 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4630 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4631 continue;\r
4632 }\r
4633 break;\r
4634 case PcieExplainTypeSlot:\r
4635 //\r
4636 // Slot registers are only valid for\r
4637 // a) Root Port of PCI Express Root Complex\r
4638 // b) Downstream Port of PCI Express Switch\r
4639 // and when SlotImplemented bit is set in PCIE cap register.\r
4640 //\r
4641 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4642 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4643 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4644 continue;\r
4645 }\r
4646 break;\r
4647 case PcieExplainTypeRoot:\r
4648 //\r
4649 // Root registers are only valid for\r
4650 // Root Port of PCI Express Root Complex\r
4651 //\r
4652 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4653 continue;\r
4654 }\r
4655 break;\r
4656 default:\r
4657 break;\r
4658 }\r
4659 PcieExplainList[Index].Func (&PciExpressCap);\r
4660 }\r
4661\r
4662 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4663 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4664 Func = (UINT8) (RShiftU64 (Address, 8));\r
4665\r
4666 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4667\r
4668 ExtendRegSize = 0x1000 - 0x100;\r
4669\r
3737ac2b 4670 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 4671\r
4672 //\r
4673 // PciRootBridgeIo protocol should support pci express extend space IO\r
4674 // (Begins at offset 0x100)\r
4675 //\r
4676 Status = IoDev->Pci.Read (\r
4677 IoDev,\r
4678 EfiPciWidthUint32,\r
4679 Pciex_Address,\r
4680 (ExtendRegSize) / sizeof (UINT32),\r
4681 (VOID *) (ExRegBuffer)\r
4682 );\r
4683 if (EFI_ERROR (Status)) {\r
4684 FreePool ((VOID *) ExRegBuffer);\r
4685 return EFI_UNSUPPORTED;\r
4686 }\r
4687 //\r
4688 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4689 //\r
c37e0f16 4690 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
5d73d92f 4691\r
d8f8021c 4692 if (ExRegBuffer != NULL) {\r
4693 DumpHex (\r
4694 2,\r
4695 0x100,\r
4696 ExtendRegSize,\r
4697 (VOID *) (ExRegBuffer)\r
4698 );\r
5d73d92f 4699\r
d8f8021c 4700 FreePool ((VOID *) ExRegBuffer);\r
4701 }\r
5d73d92f 4702\r
4703Done:\r
4704 return EFI_SUCCESS;\r
4705}\r
EFI Development Kit II mirror for PVE