-//\r
-// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>\r
-// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-#include <Chipset/AArch64.h>\r
-#include <Library/PcdLib.h>\r
-#include <AsmMacroIoLibV8.h>\r
-\r
-/*\r
- This is the stack constructed by the exception handler (low address to high address).\r
- X0 to FAR makes up the EFI_SYSTEM_CONTEXT for AArch64.\r
-\r
- UINT64 X0; 0x000\r
- UINT64 X1; 0x008\r
- UINT64 X2; 0x010\r
- UINT64 X3; 0x018\r
- UINT64 X4; 0x020\r
- UINT64 X5; 0x028\r
- UINT64 X6; 0x030\r
- UINT64 X7; 0x038\r
- UINT64 X8; 0x040\r
- UINT64 X9; 0x048\r
- UINT64 X10; 0x050\r
- UINT64 X11; 0x058\r
- UINT64 X12; 0x060\r
- UINT64 X13; 0x068\r
- UINT64 X14; 0x070\r
- UINT64 X15; 0x078\r
- UINT64 X16; 0x080\r
- UINT64 X17; 0x088\r
- UINT64 X18; 0x090\r
- UINT64 X19; 0x098\r
- UINT64 X20; 0x0a0\r
- UINT64 X21; 0x0a8\r
- UINT64 X22; 0x0b0\r
- UINT64 X23; 0x0b8\r
- UINT64 X24; 0x0c0\r
- UINT64 X25; 0x0c8\r
- UINT64 X26; 0x0d0\r
- UINT64 X27; 0x0d8\r
- UINT64 X28; 0x0e0\r
- UINT64 FP; 0x0e8 // x29 - Frame Pointer\r
- UINT64 LR; 0x0f0 // x30 - Link Register\r
- UINT64 SP; 0x0f8 // x31 - Stack Pointer\r
-\r
- // FP/SIMD Registers. 128bit if used as Q-regs.\r
- UINT64 V0[2]; 0x100\r
- UINT64 V1[2]; 0x110\r
- UINT64 V2[2]; 0x120\r
- UINT64 V3[2]; 0x130\r
- UINT64 V4[2]; 0x140\r
- UINT64 V5[2]; 0x150\r
- UINT64 V6[2]; 0x160\r
- UINT64 V7[2]; 0x170\r
- UINT64 V8[2]; 0x180\r
- UINT64 V9[2]; 0x190\r
- UINT64 V10[2]; 0x1a0\r
- UINT64 V11[2]; 0x1b0\r
- UINT64 V12[2]; 0x1c0\r
- UINT64 V13[2]; 0x1d0\r
- UINT64 V14[2]; 0x1e0\r
- UINT64 V15[2]; 0x1f0\r
- UINT64 V16[2]; 0x200\r
- UINT64 V17[2]; 0x210\r
- UINT64 V18[2]; 0x220\r
- UINT64 V19[2]; 0x230\r
- UINT64 V20[2]; 0x240\r
- UINT64 V21[2]; 0x250\r
- UINT64 V22[2]; 0x260\r
- UINT64 V23[2]; 0x270\r
- UINT64 V24[2]; 0x280\r
- UINT64 V25[2]; 0x290\r
- UINT64 V26[2]; 0x2a0\r
- UINT64 V27[2]; 0x2b0\r
- UINT64 V28[2]; 0x2c0\r
- UINT64 V29[2]; 0x2d0\r
- UINT64 V30[2]; 0x2e0\r
- UINT64 V31[2]; 0x2f0\r
-\r
- // System Context\r
- UINT64 ELR; 0x300 // Exception Link Register\r
- UINT64 SPSR; 0x308 // Saved Processor Status Register\r
- UINT64 FPSR; 0x310 // Floating Point Status Register\r
- UINT64 ESR; 0x318 // Exception syndrome register\r
- UINT64 FAR; 0x320 // Fault Address Register\r
- UINT64 Padding;0x328 // Required for stack alignment\r
-*/\r
-\r
-GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
-GCC_ASM_EXPORT(CommonExceptionEntry)\r
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
-GCC_ASM_EXPORT(CommonCExceptionHandler)\r
-\r
-.text\r
-\r
-#define GP_CONTEXT_SIZE (32 * 8)\r
-#define FP_CONTEXT_SIZE (32 * 16)\r
-#define SYS_CONTEXT_SIZE ( 6 * 8) // 5 SYS regs + Alignment requirement (ie: the stack must be aligned on 0x10)\r
-\r
-// Cannot str x31 directly\r
-#define ALL_GP_REGS \\r
- REG_PAIR (x0, x1, 0x000, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x2, x3, 0x010, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x4, x5, 0x020, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x6, x7, 0x030, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x8, x9, 0x040, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x10, x11, 0x050, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x12, x13, 0x060, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x14, x15, 0x070, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x16, x17, 0x080, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x18, x19, 0x090, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x20, x21, 0x0a0, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x22, x23, 0x0b0, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x24, x25, 0x0c0, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x26, x27, 0x0d0, GP_CONTEXT_SIZE); \\r
- REG_PAIR (x28, x29, 0x0e0, GP_CONTEXT_SIZE); \\r
- REG_ONE (x30, 0x0f0, GP_CONTEXT_SIZE);\r
-\r
-// In order to save the SP we need to put it somewhere else first.\r
-// STR only works with XZR/WZR directly\r
-#define SAVE_SP \\r
- add x1, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE); \\r
- REG_ONE (x1, 0x0f8, GP_CONTEXT_SIZE);\r
-\r
-#define ALL_FP_REGS \\r
- REG_PAIR (q0, q1, 0x000, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q2, q3, 0x020, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q4, q5, 0x040, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q6, q7, 0x060, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q8, q9, 0x080, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q10, q11, 0x0a0, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q12, q13, 0x0c0, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q14, q15, 0x0e0, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q16, q17, 0x100, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q18, q19, 0x120, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q20, q21, 0x140, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q22, q23, 0x160, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q24, q25, 0x180, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q26, q27, 0x1a0, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q28, q29, 0x1c0, FP_CONTEXT_SIZE); \\r
- REG_PAIR (q30, q31, 0x1e0, FP_CONTEXT_SIZE);\r
-\r
-#define ALL_SYS_REGS \\r
- REG_PAIR (x1, x2, 0x000, SYS_CONTEXT_SIZE); \\r
- REG_PAIR (x3, x4, 0x010, SYS_CONTEXT_SIZE); \\r
- REG_ONE (x5, 0x020, SYS_CONTEXT_SIZE);\r
-\r
-//\r
-// This code gets copied to the ARM vector table\r
-// VectorTableStart - VectorTableEnd gets copied\r
-//\r
-VECTOR_BASE(ExceptionHandlersStart)\r
-\r
-//\r
-// Current EL with SP0 : 0x0 - 0x180\r
-//\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)\r
-ASM_PFX(SynchronousExceptionSP0):\r
- b ASM_PFX(SynchronousExceptionEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)\r
-ASM_PFX(IrqSP0):\r
- b ASM_PFX(IrqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)\r
-ASM_PFX(FiqSP0):\r
- b ASM_PFX(FiqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)\r
-ASM_PFX(SErrorSP0):\r
- b ASM_PFX(SErrorEntry)\r
-\r
-//\r
-// Current EL with SPx: 0x200 - 0x380\r
-//\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)\r
-ASM_PFX(SynchronousExceptionSPx):\r
- b ASM_PFX(SynchronousExceptionEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)\r
-ASM_PFX(IrqSPx):\r
- b ASM_PFX(IrqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)\r
-ASM_PFX(FiqSPx):\r
- b ASM_PFX(FiqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)\r
-ASM_PFX(SErrorSPx):\r
- b ASM_PFX(SErrorEntry)\r
-\r
-//\r
-// Lower EL using AArch64 : 0x400 - 0x580\r
-//\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)\r
-ASM_PFX(SynchronousExceptionA64):\r
- b ASM_PFX(SynchronousExceptionEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)\r
-ASM_PFX(IrqA64):\r
- b ASM_PFX(IrqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)\r
-ASM_PFX(FiqA64):\r
- b ASM_PFX(FiqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)\r
-ASM_PFX(SErrorA64):\r
- b ASM_PFX(SErrorEntry)\r
-\r
-//\r
-// Lower EL using AArch32 : 0x600 - 0x780\r
-//\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)\r
-ASM_PFX(SynchronousExceptionA32):\r
- b ASM_PFX(SynchronousExceptionEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)\r
-ASM_PFX(IrqA32):\r
- b ASM_PFX(IrqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)\r
-ASM_PFX(FiqA32):\r
- b ASM_PFX(FiqEntry)\r
-\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)\r
-ASM_PFX(SErrorA32):\r
- b ASM_PFX(SErrorEntry)\r
-\r
-VECTOR_END(ExceptionHandlersStart)\r
-\r
-#undef REG_PAIR\r
-#undef REG_ONE\r
-#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-\r
-ASM_PFX(SynchronousExceptionEntry):\r
- // Move the stackpointer so we can reach our structure with the str instruction.\r
- sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-\r
- // Save all the General regs before touching x0 and x1.\r
- // This does not save r31(SP) as it is special. We do that later.\r
- ALL_GP_REGS\r
-\r
- // Record the type of exception that occurred.\r
- mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
-\r
- // Jump to our general handler to deal with all the common parts and process the exception.\r
- ldr x1, ASM_PFX(CommonExceptionEntry)\r
- br x1\r
-\r
-ASM_PFX(IrqEntry):\r
- sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
- ALL_GP_REGS\r
- mov x0, #EXCEPT_AARCH64_IRQ\r
- ldr x1, ASM_PFX(CommonExceptionEntry)\r
- br x1\r
-\r
-ASM_PFX(FiqEntry):\r
- sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
- ALL_GP_REGS\r
- mov x0, #EXCEPT_AARCH64_FIQ\r
- ldr x1, ASM_PFX(CommonExceptionEntry)\r
- br x1\r
-\r
-ASM_PFX(SErrorEntry):\r
- sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
- ALL_GP_REGS\r
- mov x0, #EXCEPT_AARCH64_SERROR\r
- ldr x1, ASM_PFX(CommonExceptionEntry)\r
- br x1\r
-\r
-\r
-//\r
-// This gets patched by the C code that patches in the vector table\r
-//\r
-.align 3\r
-ASM_PFX(CommonExceptionEntry):\r
- .8byte ASM_PFX(AsmCommonExceptionEntry)\r
-\r
-ASM_PFX(ExceptionHandlersEnd):\r
-\r
-\r
-\r
-//\r
-// This code runs from CpuDxe driver loaded address. It is patched into\r
-// CommonExceptionEntry.\r
-//\r
-ASM_PFX(AsmCommonExceptionEntry):\r
- /* NOTE:\r
- We have to break up the save code because the immediate value to be used\r
- with the SP is too big to do it all in one step so we need to shuffle the SP\r
- along as we go. (we only have 9bits of immediate to work with) */\r
-\r
- // Save the current Stack pointer before we start modifying it.\r
- SAVE_SP\r
-\r
- // Preserve the stack pointer we came in with before we modify it\r
- EL1_OR_EL2(x1)\r
-1:mrs x1, elr_el1 // Exception Link Register\r
- mrs x2, spsr_el1 // Saved Processor Status Register 32bit\r
- mrs x3, fpsr // Floating point Status Register 32bit\r
- mrs x4, esr_el1 // EL1 Exception syndrome register 32bit\r
- mrs x5, far_el1 // EL1 Fault Address Register\r
- b 3f\r
-\r
-2:mrs x1, elr_el2 // Exception Link Register\r
- mrs x2, spsr_el2 // Saved Processor Status Register 32bit\r
- mrs x3, fpsr // Floating point Status Register 32bit\r
- mrs x4, esr_el2 // EL2 Exception syndrome register 32bit\r
- mrs x5, far_el2 // EL2 Fault Address Register\r
-\r
- // Adjust SP to save next set\r
-3:add sp, sp, #FP_CONTEXT_SIZE\r
-\r
- // Push FP regs to Stack.\r
- ALL_FP_REGS\r
-\r
- // Adjust SP to save next set\r
- add sp, sp, #SYS_CONTEXT_SIZE\r
-\r
- // Save the SYS regs\r
- ALL_SYS_REGS\r
-\r
- // Point to top of struct after all regs saved\r
- sub sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-\r
- // x0 still holds the exception type.\r
- // Set x1 to point to the top of our struct on the Stack\r
- mov x1, sp\r
-\r
-// CommonCExceptionHandler (\r
-// IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
-// IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
-// )\r
-\r
- // Call the handler as defined above\r
-\r
- // For now we spin in the handler if we received an abort of some kind.\r
- // We do not try to recover.\r
- bl ASM_PFX(CommonCExceptionHandler) // Call exception handler\r
-\r
-\r
-// Defines for popping from stack\r
-\r
-#undef REG_PAIR\r
-#undef REG_ONE\r
-#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) ldp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-\r
- //\r
- // Disable interrupt(IRQ and FIQ) before restoring context,\r
- // or else the context will be corrupted by interrupt reentrance.\r
- // Interrupt mask will be restored from spsr by hardware when we call eret\r
- //\r
- msr daifset, #3\r
- isb\r
-\r
- // Adjust SP to pop system registers\r
- add sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
- ALL_SYS_REGS\r
-\r
- EL1_OR_EL2(x6)\r
-1:msr elr_el1, x1 // Exception Link Register\r
- msr spsr_el1,x2 // Saved Processor Status Register 32bit\r
- msr fpsr, x3 // Floating point Status Register 32bit\r
- msr esr_el1, x4 // EL1 Exception syndrome register 32bit\r
- msr far_el1, x5 // EL1 Fault Address Register\r
- b 3f\r
-2:msr elr_el2, x1 // Exception Link Register\r
- msr spsr_el2,x2 // Saved Processor Status Register 32bit\r
- msr fpsr, x3 // Floating point Status Register 32bit\r
- msr esr_el2, x4 // EL2 Exception syndrome register 32bit\r
- msr far_el2, x5 // EL2 Fault Address Register\r
-\r
-3:// pop all regs and return from exception.\r
- sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
- ALL_GP_REGS\r
-\r
- // Adjust SP to pop next set\r
- add sp, sp, #FP_CONTEXT_SIZE\r
- // Pop FP regs to Stack.\r
- ALL_FP_REGS\r
-\r
- // Adjust SP to be where we started from when we came into the handler.\r
- // The handler can not change the SP.\r
- add sp, sp, #SYS_CONTEXT_SIZE\r
-\r
- eret\r
-\r
-#undef REG_PAIR\r
-#undef REG_ONE\r