SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Reference(s):\r
- - ACPI 6.2 Specification - Errata A, September 2017\r
+ - ACPI 6.3 Specification - January 2019\r
+ - ARM Architecture Reference Manual ARMv8 (D.a)\r
**/\r
\r
#include <Library/PrintLib.h>\r
#include <Library/UefiLib.h>\r
#include "AcpiParser.h"\r
+#include "AcpiView.h"\r
+#include "PpttParser.h"\r
\r
// Local variables\r
STATIC CONST UINT8* ProcessorTopologyStructureType;\r
STATIC ACPI_DESCRIPTION_HEADER_INFO AcpiHdrInfo;\r
\r
/**\r
- An ACPI_PARSER array describing the ACPI PPTT Table.\r
+ This function validates the Cache Type Structure (Type 1) 'Number of sets'\r
+ field.\r
+\r
+ @param [in] Ptr Pointer to the start of the field data.\r
+ @param [in] Context Pointer to context specific information e.g. this\r
+ could be a pointer to the ACPI table header.\r
**/\r
-STATIC CONST ACPI_PARSER PpttParser[] = {\r
- PARSE_ACPI_HEADER (&AcpiHdrInfo)\r
-};\r
+STATIC\r
+VOID\r
+EFIAPI\r
+ValidateCacheNumberOfSets (\r
+ IN UINT8* Ptr,\r
+ IN VOID* Context\r
+ )\r
+{\r
+ UINT32 NumberOfSets;\r
+ NumberOfSets = *(UINT32*)Ptr;\r
+\r
+ if (NumberOfSets == 0) {\r
+ IncrementErrorCount ();\r
+ Print (L"\nERROR: Cache number of sets must be greater than 0");\r
+ return;\r
+ }\r
+\r
+#if defined(MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)\r
+ if (NumberOfSets > PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX) {\r
+ IncrementErrorCount ();\r
+ Print (\r
+ L"\nERROR: When ARMv8.3-CCIDX is implemented the maximum cache number of "\r
+ L"sets must be less than or equal to %d",\r
+ PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX\r
+ );\r
+ return;\r
+ }\r
+\r
+ if (NumberOfSets > PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX) {\r
+ IncrementWarningCount ();\r
+ Print (\r
+ L"\nWARNING: Without ARMv8.3-CCIDX, the maximum cache number of sets "\r
+ L"must be less than or equal to %d. Ignore this message if "\r
+ L"ARMv8.3-CCIDX is implemented",\r
+ PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX\r
+ );\r
+ return;\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+/**\r
+ This function validates the Cache Type Structure (Type 1) 'Associativity'\r
+ field.\r
+\r
+ @param [in] Ptr Pointer to the start of the field data.\r
+ @param [in] Context Pointer to context specific information e.g. this\r
+ could be a pointer to the ACPI table header.\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+ValidateCacheAssociativity (\r
+ IN UINT8* Ptr,\r
+ IN VOID* Context\r
+ )\r
+{\r
+ UINT8 Associativity;\r
+ Associativity = *(UINT8*)Ptr;\r
+\r
+ if (Associativity == 0) {\r
+ IncrementErrorCount ();\r
+ Print (L"\nERROR: Cache associativity must be greater than 0");\r
+ return;\r
+ }\r
+}\r
\r
/**\r
This function validates the Cache Type Structure (Type 1) Line size field.\r
UINT16 LineSize;\r
LineSize = *(UINT16*)Ptr;\r
\r
- if ((LineSize < 16) || (LineSize > 2048)) {\r
+ if ((LineSize < PPTT_ARM_CACHE_LINE_SIZE_MIN) ||\r
+ (LineSize > PPTT_ARM_CACHE_LINE_SIZE_MAX)) {\r
IncrementErrorCount ();\r
Print (\r
- L"\nERROR: The cache line size must be between 16 and 2048 bytes"\r
- L" on ARM Platforms."\r
+ L"\nERROR: The cache line size must be between %d and %d bytes"\r
+ L" on ARM Platforms.",\r
+ PPTT_ARM_CACHE_LINE_SIZE_MIN,\r
+ PPTT_ARM_CACHE_LINE_SIZE_MAX\r
);\r
return;\r
}\r
}\r
}\r
\r
+/**\r
+ An ACPI_PARSER array describing the ACPI PPTT Table.\r
+**/\r
+STATIC CONST ACPI_PARSER PpttParser[] = {\r
+ PARSE_ACPI_HEADER (&AcpiHdrInfo)\r
+};\r
+\r
/**\r
An ACPI_PARSER array describing the processor topology structure header.\r
**/\r
{L"Flags", 4, 4, L"0x%x", NULL, NULL, NULL, NULL},\r
{L"Next Level of Cache", 4, 8, L"0x%x", NULL, NULL, NULL, NULL},\r
{L"Size", 4, 12, L"0x%x", NULL, NULL, NULL, NULL},\r
- {L"Number of sets", 4, 16, L"%d", NULL, NULL, NULL, NULL},\r
- {L"Associativity", 1, 20, L"%d", NULL, NULL, NULL, NULL},\r
+ {L"Number of sets", 4, 16, L"%d", NULL, NULL, ValidateCacheNumberOfSets, NULL},\r
+ {L"Associativity", 1, 20, L"%d", NULL, NULL, ValidateCacheAssociativity, NULL},\r
{L"Attributes", 1, 21, L"0x%x", NULL, NULL, ValidateCacheAttributes, NULL},\r
{L"Line size", 2, 22, L"%d", NULL, NULL, ValidateCacheLineSize, NULL}\r
};\r
--- /dev/null
+/** @file\r
+ Header file for PPTT parser\r
+\r
+ Copyright (c) 2019, ARM Limited. All rights reserved.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Reference(s):\r
+ - ARM Architecture Reference Manual ARMv8 (D.a)\r
+**/\r
+\r
+#ifndef PPTT_PARSER_H_\r
+#define PPTT_PARSER_H_\r
+\r
+#if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)\r
+\r
+/// Cache parameters allowed by the architecture with\r
+/// ARMv8.3-CCIDX (Cache extended number of sets)\r
+/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0001\r
+#define PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX (1 << 24)\r
+#define PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX (1 << 21)\r
+\r
+/// Cache parameters allowed by the architecture without\r
+/// ARMv8.3-CCIDX (Cache extended number of sets)\r
+/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0000\r
+#define PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX (1 << 15)\r
+#define PPTT_ARM_CACHE_ASSOCIATIVITY_MAX (1 << 10)\r
+\r
+/// Common cache parameters\r
+/// Derived from CCSIDR_EL1\r
+/// The LineSize is represented by bits 2:0\r
+/// (Log2(Number of bytes in cache line)) - 4 is used to represent\r
+/// the LineSize bits.\r
+#define PPTT_ARM_CACHE_LINE_SIZE_MAX (1 << 11)\r
+#define PPTT_ARM_CACHE_LINE_SIZE_MIN (1 << 4)\r
+\r
+#endif // if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)\r
+\r
+#endif // PPTT_PARSER_H_\r