MdePkg/BaseLib: add support for PVALIDATE instruction

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The PVALIDATE instruction validates or rescinds validation of a guest
page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
bits OF, ZF, AF, PF and SF are set based on this return code. If the
instruction completed succesfully, the rFLAGS bit CF indicates if the
contents of the RMP entry were changed or not.

For more information about the instruction see AMD APM volume 3.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7253997a6f8c36fd69c73dd9fa5f9808495c7e36..a2cd134bea9a865b8cfe206cff42ec786b6983b0 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4813,6 +4813,56 @@ SpeculationBarrier (
   VOID\r
   );\r
 \r
+#if defined (MDE_CPU_X64)\r
+//\r
+// The page size for the PVALIDATE instruction\r
+//\r
+typedef enum {\r
+  PvalidatePageSize4K = 0,\r
+  PvalidatePageSize2MB,\r
+} PVALIDATE_PAGE_SIZE;\r
+\r
+//\r
+// PVALIDATE Return Code.\r
+//\r
+#define PVALIDATE_RET_SUCCESS         0\r
+#define PVALIDATE_RET_FAIL_INPUT      1\r
+#define PVALIDATE_RET_SIZE_MISMATCH   6\r
+\r
+//\r
+// The PVALIDATE instruction did not make any changes to the RMP entry.\r
+//\r
+#define PVALIDATE_RET_NO_RMPUPDATE    255\r
+\r
+/**\r
+ Execute a PVALIDATE instruction to validate or to rescinds validation of a guest\r
+ page's RMP entry.\r
+\r
+ The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.\r
+\r
+ The function is available on X64.\r
+\r
+ @param[in]    PageSize         The page size to use.\r
+ @param[in]    Validate         If TRUE, validate the guest virtual address\r
+                                otherwise invalidate the guest virtual address.\r
+ @param[in]    Address          The guest virtual address.\r
+\r
+ @retval PVALIDATE_RET_SUCCESS        The PVALIDATE instruction succeeded, and\r
+                                      updated the RMP entry.\r
+ @retval PVALIDATE_RET_NO_RMPUPDATE   The PVALIDATE instruction succeeded, but\r
+                                      did not update the RMP entry.\r
+ @return                              Failure code from the PVALIDATE\r
+                                      instruction.\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmPvalidate (\r
+  IN   PVALIDATE_PAGE_SIZE     PageSize,\r
+  IN   BOOLEAN                 Validate,\r
+  IN   PHYSICAL_ADDRESS        Address\r
+  );\r
+#endif\r
+\r
 \r
 #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
 ///\r

diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index 527f71e9eb4d34ab9e14d24640f898364e1272bb..528bb3385609854feffa42ee0743b00d00e79f33 100644 (file)
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -33,6 +33,14 @@
     DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8\r
 %endmacro\r
 \r
+;\r
+; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.\r
+; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753\r
+;\r
+%macro PVALIDATE       0\r
+    DB 0xF2, 0x0F, 0x01, 0xFF\r
+%endmacro\r
+\r
 ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.\r
 ; For example, to define a structure called mytype containing a longword,\r
 ; a word, a byte and a string of bytes, you might code\r

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea2ae779c799b3ef3083b2555a99ff..89a52f72c08a5cc2da39b37b239001fda01e8f61 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -317,6 +317,7 @@
   X64/GccInlinePriv.c | GCC\r
   X64/EnableDisableInterrupts.nasm\r
   X64/DisablePaging64.nasm\r
+  X64/Pvalidate.nasm\r
   X64/RdRand.nasm\r
   X64/XGetBv.nasm\r
   X64/XSetBv.nasm\r

diff --git a/MdePkg/Library/BaseLib/X64/Pvalidate.nasm b/MdePkg/Library/BaseLib/X64/Pvalidate.nasm
new file mode 100644 (file)
index 0000000..a7d1779
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/Pvalidate.nasm
@@ -0,0 +1,42 @@
+;-----------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2021, AMD. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;-----------------------------------------------------------------------------\r
+\r
+%include "Nasm.inc"\r
+\r
+    SECTION .text\r
+\r
+;-----------------------------------------------------------------------------\r
+;  UINT32\r
+;  EFIAPI\r
+;  AsmPvalidate (\r
+;    IN   UINT32              PageSize\r
+;    IN   UINT32              Validate,\r
+;    IN   UINT64              Address\r
+;    )\r
+;-----------------------------------------------------------------------------\r
+global ASM_PFX(AsmPvalidate)\r
+ASM_PFX(AsmPvalidate):\r
+  mov     rax, r8\r
+\r
+  PVALIDATE\r
+\r
+  ; Save the carry flag.\r
+  setc    dl\r
+\r
+  ; The PVALIDATE instruction returns the status in rax register.\r
+  cmp     rax, 0\r
+  jne     PvalidateExit\r
+\r
+  ; Check the carry flag to determine if RMP entry was updated.\r
+  cmp     dl, 0\r
+  je      PvalidateExit\r
+\r
+  ; Return the PVALIDATE_RET_NO_RMPUPDATE.\r
+  mov     rax, 255\r
+\r
+PvalidateExit:\r
+  ret\r