Just like EhciDxe, do not reset host controller when debug capability is enabled...

Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index 3e578975adbae67404f1606ae04cebdf9d578fe4..8debc4c18c34c4c7a0dc4749ee84a3f9b54277bc 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -164,6 +164,11 @@ XhcReset (
   // Flow through, same behavior as Host Controller Reset
   //
   case EFI_USB_HC_RESET_HOST_CONTROLLER:
   // Flow through, same behavior as Host Controller Reset
   //
   case EFI_USB_HC_RESET_HOST_CONTROLLER:

+    if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
+        ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
+      Status = EFI_SUCCESS;
+      goto ON_EXIT;
+    }

     //
     // Host Controller must be Halt when Reset it
     //
     //
     // Host Controller must be Halt when Reset it
     //


@@ -1755,7 +1760,8 @@ XhcCreateUsbHc (
 
   ExtCapReg            = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
   Xhc->ExtCapRegBase   = ExtCapReg << 2;
 
   ExtCapReg            = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
   Xhc->ExtCapRegBase   = ExtCapReg << 2;

-  Xhc->UsbLegSupOffset = XhcGetLegSupCapAddr (Xhc);
+  Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+  Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);

 
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
 
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));


@@ -1764,6 +1770,7 @@ XhcCreateUsbHc (
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
   DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));

+  DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));

 
   //
   // Create AsyncRequest Polling Timer
 
   //
   // Create AsyncRequest Polling Timer

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
index fab6a7296311d3f3f6cec4f64be0e47eaba7949a..1eb0d0e176bb4970583da0c7fdac8898defe8b00 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
@@ -231,6 +231,7 @@ struct _USB_XHCI_INSTANCE {
   UINTN                     *ScratchEntryMap;\r
   UINT32                    ExtCapRegBase;\r
   UINT32                    UsbLegSupOffset;\r
   UINTN                     *ScratchEntryMap;\r
   UINT32                    ExtCapRegBase;\r
   UINT32                    UsbLegSupOffset;\r

+  UINT32                    DebugCapSupOffset;\r

   UINT64                    *DCBAA;\r
   VOID                      *DCBAAMap;\r
   UINT32                    MaxSlotsEn;\r
   UINT64                    *DCBAA;\r
   VOID                      *DCBAAMap;\r
   UINT32                    MaxSlotsEn;\r

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 9d50ef824261acc357812e33a911eec017bea09b..c863f22d250d512c98f85981462f3cf5bec9d9b3 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -571,16 +571,18 @@ XhcClearBiosOwnership (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Calculate the XHCI legacy support capability register offset.\r
+  Calculate the offset of the XHCI capability.\r

 \r
   @param  Xhc     The XHCI Instance.\r
 \r
   @param  Xhc     The XHCI Instance.\r

+  @param  CapId   The XHCI Capability ID.\r

 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r
 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r

-XhcGetLegSupCapAddr (\r
-  IN USB_XHCI_INSTANCE    *Xhc\r
+XhcGetCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE    *Xhc,\r
+  IN UINT8                CapId\r

   )\r
 {\r
   UINT32 ExtCapOffset;\r
   )\r
 {\r
   UINT32 ExtCapOffset;\r


@@ -594,7 +596,7 @@ XhcGetLegSupCapAddr (
     // Check if the extended capability register's capability id is USB Legacy Support.\r
     //\r
     Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
     // Check if the extended capability register's capability id is USB Legacy Support.\r
     //\r
     Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r

-    if ((Data & 0xFF) == 0x1) {\r
+    if ((Data & 0xFF) == CapId) {\r

       return ExtCapOffset;\r
     }\r
     //\r
       return ExtCapOffset;\r
     }\r
     //\r


@@ -660,6 +662,8 @@ XhcResetHC (
 {\r
   EFI_STATUS              Status;\r
 \r
 {\r
   EFI_STATUS              Status;\r
 \r

+  Status = EFI_SUCCESS;\r
+\r

   DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
   //\r
   // Host can only be reset when it is halt. If not so, halt it\r
   DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
   //\r
   // Host can only be reset when it is halt. If not so, halt it\r


@@ -672,8 +676,12 @@ XhcResetHC (
     }\r
   }\r
 \r
     }\r
   }\r
 \r

-  XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
-  Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
+      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
+    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  }\r
+\r

   return Status;\r
 }\r
 \r
   return Status;\r
 }\r
 \r

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index eea468bbd78026aa85186a3c1db9dd5ffccb7c69..20a5510bfec9f714a3579ea221e50c9318b47682 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -29,6 +29,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define USB_HUB_CLASS_CODE          0x09\r
 #define USB_HUB_SUBCLASS_CODE       0x00\r
 \r
 #define USB_HUB_CLASS_CODE          0x09\r
 #define USB_HUB_SUBCLASS_CODE       0x00\r
 \r

+#define XHC_CAP_USB_LEGACY          0x01\r
+#define XHC_CAP_USB_DEBUG           0x0A\r
+\r

 //============================================//\r
 //           XHCI register offset             //\r
 //============================================//\r
 //============================================//\r
 //           XHCI register offset             //\r
 //============================================//\r


@@ -67,6 +70,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
 #define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
 \r
 #define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
 #define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
 \r

+//\r
+// Debug registers offset\r
+//\r
+#define XHC_DC_DCCTRL                      0x20\r
+\r

 #define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
 #define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
 \r
 #define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
 #define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
 \r


@@ -447,6 +455,21 @@ XhcClearRuntimeRegBit (
   IN UINT32               Bit\r
   );\r
 \r
   IN UINT32               Bit\r
   );\r
 \r

+/**\r
+  Read XHCI extended capability register.\r
+\r
+  @param  Xhc          The XHCI Instance.\r
+  @param  Offset       The offset of the extended capability register.\r
+\r
+  @return The register content read\r
+\r
+**/\r
+UINT32\r
+XhcReadExtCapReg (\r
+  IN  USB_XHCI_INSTANCE   *Xhc,\r
+  IN  UINT32              Offset\r
+  );\r
+\r

 /**\r
   Whether the XHCI host controller is halted.\r
 \r
 /**\r
   Whether the XHCI host controller is halted.\r
 \r


@@ -524,16 +547,18 @@ XhcRunHC (
   );\r
 \r
 /**\r
   );\r
 \r
 /**\r

-  Calculate the XHCI legacy support capability register offset.\r
+  Calculate the offset of the XHCI capability.\r

 \r
   @param  Xhc     The XHCI Instance.\r
 \r
   @param  Xhc     The XHCI Instance.\r

+  @param  CapId   The XHCI Capability ID.\r

 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r
 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r

-XhcGetLegSupCapAddr (\r
-  IN USB_XHCI_INSTANCE    *Xhc\r
+XhcGetCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE    *Xhc,\r
+  IN UINT8                CapId\r

   );\r
 \r
 #endif\r
   );\r
 \r
 #endif\r