MdeModulePkg/NvmExpressDxe: comments update to meet implementation

Cc: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Wu, Hao A <hao.a.wu@intel.com>
Reviewed-by: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h
index 21c6255caac26cca81928b68e43a06998680b2b1..6cbef3e380d42448fceba0b0165a70e802f66d69 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
   NVM Express specification.\r
 \r
-  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -101,13 +101,11 @@ struct _NVME_CONTROLLER_PRIVATE_DATA {
   NVME_ADMIN_CONTROLLER_DATA          *ControllerData;\r
 \r
   //\r
-  // 6 x 4kB aligned buffers will be carved out of this buffer.\r
+  // 4 x 4kB aligned buffers will be carved out of this buffer.\r
   // 1st 4kB boundary is the start of the admin submission queue.\r
-  // 2nd 4kB boundary is the start of the I/O submission queue #1.\r
-  // 3rd 4kB boundary is the start of the admin completion queue.\r
-  // 4th 4kB boundary is the start of the I/O completion queue #1.\r
-  // 5th 4kB boundary is the start of the first PRP list page.\r
-  // 6th 4kB boundary is the start of the second PRP list page.\r
+  // 2nd 4kB boundary is the start of the admin completion queue.\r
+  // 3rd 4kB boundary is the start of I/O submission queue #1.\r
+  // 4th 4kB boundary is the start of I/O completion queue #1.\r
   //\r
   UINT8                               *Buffer;\r
   UINT8                               *BufferPciAddr;\r