NASM wants this code to specify a size.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
@@:\r
mov ecx, [ebp + 24]\r
jecxz @F\r
- pop [ecx]\r
+ pop DWORD [ecx]\r
@@:\r
mov ecx, [ebp + 28]\r
jecxz @F\r
@@:\r
mov ecx, [ebp + 28]\r
jecxz @F\r
- pop [ecx]\r
+ pop DWORD [ecx]\r
@@:\r
mov eax, [ebp + 12]\r
leave\r
;------------------------------------------------------------------------------\r
InternalX86EnablePaging64 PROC\r
cli\r
- mov [esp], @F ; offset for far retf, seg is the 1st arg\r
+ mov DWORD PTR [esp], @F ; offset for far retf, seg is the 1st arg\r
mov eax, cr4\r
or al, (1 SHL 5)\r
mov cr4, eax ; enable PAE\r
; );\r
;------------------------------------------------------------------------------\r
SetJump PROC\r
- push [esp + 4]\r
+ push DWORD [esp + 4]\r
call InternalAssertJumpBuffer ; To validate JumpBuffer\r
pop ecx\r
pop ecx ; ecx <- return address\r