#\r
\r
[Binaries.Ia32]\r
- RAW|ResetVector.ia32.raw|*\r
+ RAW|IA32/ResetVector.ia32.raw|*\r
\r
[Binaries.X64]\r
- RAW|ResetVector.x64.raw|*\r
+ RAW|X64/PageTable2M/ResetVector.x64.raw|*\r
\r
[UserExtensions.TianoCore."ExtraFiles"]\r
ResetVectorExtra.uni\r
--- /dev/null
+## @file\r
+# Reset Vector binary\r
+#\r
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ResetVector\r
+ MODULE_UNI_FILE = ResetVector.uni\r
+ FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.1\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Binaries.Ia32]\r
+ RAW|IA32/ResetVector.ia32.raw|*\r
+\r
+[Binaries.X64]\r
+ RAW|X64/PageTable1G/ResetVector.x64.raw|*\r
+\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+ ResetVectorExtra.uni\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
\r
-import glob\r
import os\r
import subprocess\r
import sys\r
\r
+PAGE_TABLE_2M = 'PageTable2M'\r
+PAGE_TABLE_1G = 'PageTable1G'\r
+FILE_FORMAT = '.raw'\r
+ALL_RAW_FORMAT = '*' + FILE_FORMAT\r
+IA32 = 'IA32'\r
+X64 = 'X64'\r
+\r
+# Pre-Define a Macros for Page Table\r
+PAGE_TABLES = {\r
+ PAGE_TABLE_2M : "PAGE_TABLE_2M",\r
+ PAGE_TABLE_1G : "PAGE_TABLE_1G"\r
+}\r
+\r
def RunCommand(commandLine):\r
- #print ' '.join(commandLine)\r
return subprocess.call(commandLine)\r
\r
-for filename in glob.glob(os.path.join('Bin', '*.raw')):\r
- os.remove(filename)\r
+# Check for all raw binaries and delete them\r
+for root, dirs, files in os.walk('Bin'):\r
+ for file in files:\r
+ if file.endswith(FILE_FORMAT):\r
+ os.remove(os.path.join(root, file))\r
\r
for arch in ('ia32', 'x64'):\r
for debugType in (None, 'port80', 'serial'):\r
- output = os.path.join('Bin', 'ResetVector')\r
- output += '.' + arch\r
- if debugType is not None:\r
- output += '.' + debugType\r
- output += '.raw'\r
- commandLine = (\r
- 'nasm',\r
- '-D', 'ARCH_%s' % arch.upper(),\r
- '-D', 'DEBUG_%s' % str(debugType).upper(),\r
- '-o', output,\r
- 'Vtf0.nasmb',\r
- )\r
- print(f"Command : {' '.join(commandLine)}")\r
- ret = RunCommand(commandLine)\r
- if ret != 0:\r
- print(f"something went wrong while executing {commandLine[-1]}")\r
- sys.exit()\r
- print('\tASM\t' + output)\r
-\r
- commandLine = (\r
- 'python',\r
- 'Tools/FixupForRawSection.py',\r
- output,\r
- )\r
- print('\tFIXUP\t' + output)\r
- ret = RunCommand(commandLine)\r
- if ret != 0: sys.exit(ret)\r
+ for pageTable in PAGE_TABLES.keys():\r
+ ret = True\r
+ if arch.lower() == X64.lower():\r
+ directory = os.path.join('Bin', X64, pageTable)\r
+ else:\r
+ directory = os.path.join('Bin', IA32)\r
+\r
+ # output raw binary name with arch type\r
+ fileName = 'ResetVector' + '.' + arch\r
+\r
+ if debugType is not None:\r
+ fileName += '.' + debugType\r
+ fileName += FILE_FORMAT\r
+\r
+ output = os.path.join(directory, fileName)\r
+\r
+ # if the directory not exists then create it\r
+ if not os.path.isdir(directory):\r
+ os.makedirs(directory)\r
+\r
+ # Prepare the command to execute the nasmb\r
+ commandLine = (\r
+ 'nasm',\r
+ '-D', 'ARCH_%s' % arch.upper(),\r
+ '-D', 'DEBUG_%s' % str(debugType).upper(),\r
+ '-D', PAGE_TABLES[pageTable].upper(),\r
+ '-o', output,\r
+ 'Vtf0.nasmb',\r
+ )\r
+\r
+ print(f"Command : {' '.join(commandLine)}")\r
+\r
+ try:\r
+ ret = RunCommand(commandLine)\r
+ except FileNotFoundError:\r
+ print("NASM not found")\r
+ except:\r
+ pass\r
+\r
+ if ret != 0:\r
+ print(f"something went wrong while executing {commandLine[-1]}")\r
+ sys.exit()\r
+ print('\tASM\t' + output)\r
+\r
+ commandLine = (\r
+ 'python',\r
+ 'Tools/FixupForRawSection.py',\r
+ output,\r
+ )\r
+ print('\tFIXUP\t' + output)\r
+ ret = RunCommand(commandLine)\r
+ if ret != 0: sys.exit(ret)\r
\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Definitions of Page Table Entry for the reset vector module\r
+;\r
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%define PAGE_PRESENT 0x01\r
+%define PAGE_READ_WRITE 0x02\r
+%define PAGE_USER_SUPERVISOR 0x04\r
+%define PAGE_WRITE_THROUGH 0x08\r
+%define PAGE_CACHE_DISABLE 0x010\r
+%define PAGE_ACCESSED 0x020\r
+%define PAGE_DIRTY 0x040\r
+%define PAGE_SIZE 0x080\r
+%define PAGE_GLOBAL 0x0100\r
+%define PAGE_2M_PAT 0x01000\r
+\r
=== HOW TO BUILD VTF0 ===\r
\r
Dependencies:\r
-* Python 2.5~2.7\r
+* Python 3 or newer\r
* Nasm 2.03 or newer\r
\r
To rebuild the VTF0 binaries:\r
\r
%include "PostCodes.inc"\r
\r
+%include "PageTables.inc"\r
+\r
%ifdef ARCH_X64\r
-%include "X64/PageTables.asm"\r
+ %ifdef PAGE_TABLE_1G\r
+ %include "X64/PageTables1G.asm"\r
+ %else\r
+ %include "X64/PageTables2M.asm"\r
+ %endif\r
%endif\r
\r
%ifdef DEBUG_PORT80\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)\r
-;\r
-; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 64\r
-\r
-%define ALIGN_TOP_TO_4K_FOR_PAGING\r
-\r
-%define PAGE_PRESENT 0x01\r
-%define PAGE_READ_WRITE 0x02\r
-%define PAGE_USER_SUPERVISOR 0x04\r
-%define PAGE_WRITE_THROUGH 0x08\r
-%define PAGE_CACHE_DISABLE 0x010\r
-%define PAGE_ACCESSED 0x020\r
-%define PAGE_DIRTY 0x040\r
-%define PAGE_PAT 0x080\r
-%define PAGE_GLOBAL 0x0100\r
-%define PAGE_2M_MBO 0x080\r
-%define PAGE_2M_PAT 0x01000\r
-\r
-%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r
- PAGE_ACCESSED + \\r
- PAGE_DIRTY + \\r
- PAGE_READ_WRITE + \\r
- PAGE_PRESENT)\r
-\r
-%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
- PAGE_READ_WRITE + \\r
- PAGE_PRESENT)\r
-\r
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)\r
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))\r
-\r
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \\r
- PAGE_PDP_ATTR)\r
-%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)\r
-\r
-TopLevelPageDirectory:\r
-\r
- ;\r
- ; Top level Page Directory Pointers (1 * 512GB entry)\r
- ;\r
- DQ PDP(0x1000)\r
-\r
-\r
- ;\r
- ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r
- ;\r
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0\r
-\r
- DQ PDP(0x2000)\r
- DQ PDP(0x3000)\r
- DQ PDP(0x4000)\r
- DQ PDP(0x5000)\r
-\r
- ;\r
- ; Page Table Entries (2048 * 2MB entries => 4GB)\r
- ;\r
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0\r
-\r
-%assign i 0\r
-%rep 0x800\r
- DQ PTE_2MB(i)\r
- %assign i i+1\r
-%endrep\r
-\r
-EndOfPageTables:\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)\r
+;\r
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+; Linear-Address Translation to a 1-GByte Page\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 64\r
+\r
+%define ALIGN_TOP_TO_4K_FOR_PAGING\r
+\r
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
+ PAGE_READ_WRITE + \\r
+ PAGE_PRESENT)\r
+\r
+%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \\r
+ PAGE_READ_WRITE + \\r
+ PAGE_DIRTY + \\r
+ PAGE_PRESENT + \\r
+ PAGE_SIZE)\r
+\r
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)\r
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))\r
+\r
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \\r
+ PAGE_PDP_ATTR)\r
+\r
+%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)\r
+\r
+ALIGN 16\r
+\r
+TopLevelPageDirectory:\r
+\r
+ ;\r
+ ; Top level Page Directory Pointers (1 * 512GB entry)\r
+ ;\r
+ DQ PDP(0x1000)\r
+\r
+ TIMES 0x1000-PGTBLS_OFFSET($) DB 0\r
+ ;\r
+ ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)\r
+ ;\r
+%assign i 0\r
+%rep 512\r
+ DQ PDP_1G(i)\r
+ %assign i i+1\r
+%endrep\r
+ TIMES 0x2000-PGTBLS_OFFSET($) DB 0\r
+\r
+EndOfPageTables:\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)\r
+;\r
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 64\r
+\r
+%define ALIGN_TOP_TO_4K_FOR_PAGING\r
+\r
+%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \\r
+ PAGE_ACCESSED + \\r
+ PAGE_DIRTY + \\r
+ PAGE_READ_WRITE + \\r
+ PAGE_PRESENT)\r
+\r
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
+ PAGE_READ_WRITE + \\r
+ PAGE_PRESENT)\r
+\r
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)\r
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))\r
+\r
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \\r
+ PAGE_PDP_ATTR)\r
+%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)\r
+\r
+TopLevelPageDirectory:\r
+\r
+ ;\r
+ ; Top level Page Directory Pointers (1 * 512GB entry)\r
+ ;\r
+ DQ PDP(0x1000)\r
+\r
+\r
+ ;\r
+ ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r
+ ;\r
+ TIMES 0x1000-PGTBLS_OFFSET($) DB 0\r
+\r
+ DQ PDP(0x2000)\r
+ DQ PDP(0x3000)\r
+ DQ PDP(0x4000)\r
+ DQ PDP(0x5000)\r
+\r
+ ;\r
+ ; Page Table Entries (2048 * 2MB entries => 4GB)\r
+ ;\r
+ TIMES 0x2000-PGTBLS_OFFSET($) DB 0\r
+\r
+%assign i 0\r
+%rep 0x800\r
+ DQ PTE_2MB(i)\r
+ %assign i i+1\r
+%endrep\r
+\r
+EndOfPageTables:\r
"DscPath": "UefiCpuPkg.dsc",\r
"IgnoreInf": [\r
"UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf",\r
- "UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf"\r
+ "UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf",\r
+ "UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf"\r
]\r
},\r
"HostUnitTestDscCompleteCheck": {\r
projects / mirror_edk2.git / commitdiff