Implement an accessor function for the ID_MMFR0 system register, which
contains information about the VMSA implementation. We will need this
to access the number of shareability levels and the nature of their
implementations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18894
6f19259b-4bc3-4df7-8a09-
765794883524
IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
);\r
\r
IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmReadIdMmfr0 (\r
+ VOID\r
+ );\r
+\r
#endif // __ARM_V7_LIB_H__\r
\r
#endif // __ARM_V7_LIB_H__\r
\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
GCC_ASM_EXPORT (ArmReadIdPfr1)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
GCC_ASM_EXPORT (ArmReadIdPfr1)\r
+GCC_ASM_EXPORT (ArmReadIdMmfr0)\r
\r
.set DC_ON, (0x1<<2)\r
.set IC_ON, (0x1<<12)\r
\r
.set DC_ON, (0x1<<2)\r
.set IC_ON, (0x1<<12)\r
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
bx lr\r
\r
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
bx lr\r
\r
+ASM_PFX(ArmReadIdMmfr0):\r
+ mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register\r
+ bx lr\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
EXPORT ArmReadIdPfr1\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
EXPORT ArmReadIdPfr1\r
+ EXPORT ArmReadIdMmfr0\r
\r
AREA ArmV7Support, CODE, READONLY\r
PRESERVE8\r
\r
AREA ArmV7Support, CODE, READONLY\r
PRESERVE8\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
bx lr\r
\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
bx lr\r
\r
+ArmReadIdMmfr0\r
+ mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
+ bx lr\r
+\r