Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15708
6f19259b-4bc3-4df7-8a09-
765794883524
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
\r
// Hypervisor Configuration Register\r
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
\r
// Hypervisor Configuration Register\r
-#define ARM_HCR_FMO BIT3\r
-#define ARM_HCR_IMO BIT4\r
-#define ARM_HCR_AMO BIT5\r
-#define ARM_HCR_TGE BIT27\r
+#define ARM_HCR_FMO BIT3\r
+#define ARM_HCR_IMO BIT4\r
+#define ARM_HCR_AMO BIT5\r
+#define ARM_HCR_TSC BIT19\r
+#define ARM_HCR_TGE BIT27\r
\r
// AArch64 Exception Level\r
#define AARCH64_EL3 0xC\r
\r
// AArch64 Exception Level\r
#define AARCH64_EL3 0xC\r