MdeModulePkg\Bus\Ata\AtaAtapiPassThru: don't set PxSACT bit when issuing command

Setting a bit in the PxSACT register for a command in the command list indicates
to the controller that the command list slot contains a native queued command (NCQ).
This can cause problems with some controllers (one such controller is the Marvell 9128).
Since NCQ commands are not used, don't set the PxACT register for commands issued.

Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: Chris Ruffin <chris.ruffin@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16536 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index 186d40c062ac7e8c3745783ce1fa5b870b8afdf1..4d1b5848a550939bb7c9273a5350ae1da418b833 100644 (file)
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -1340,10 +1340,6 @@ AhciStartCommand (
   //\r
   // Setting the command\r
   //\r
-  Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;\r
-  AhciAndReg (PciIo, Offset, 0);\r
-  AhciOrReg (PciIo, Offset, CmdSlotBit);\r
-\r
   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
   AhciAndReg (PciIo, Offset, 0);\r
   AhciOrReg (PciIo, Offset, CmdSlotBit);\r