--- /dev/null
+## @file
+# Automate the process of building the various reset vector types
+#
+# Copyright (c) 2009, Intel Corporation
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+import glob
+import os
+import subprocess
+import sys
+
+def RunCommand(commandLine):
+ #print ' '.join(commandLine)
+ return subprocess.call(commandLine)
+
+for filename in glob.glob(os.path.join('Bin', '*.raw')):
+ os.remove(filename)
+
+for arch in ('ia32', 'x64'):
+ for debugType in (None, 'port80', 'serial'):
+ output = os.path.join('Bin', 'ResetVector')
+ output += '.' + arch
+ if debugType is not None:
+ output += '.' + debugType
+ output += '.raw'
+ commandLine = (
+ 'nasm',
+ '-D', 'ARCH_%s' % arch.upper(),
+ '-D', 'DEBUG_%s' % str(debugType).upper(),
+ '-o', output,
+ 'ResetVectorCode.asm',
+ )
+ ret = RunCommand(commandLine)
+ print '\tASM\t' + output
+ if ret != 0: sys.exit(ret)
+
+ commandLine = (
+ 'python',
+ 'Tools/FixupForRawSection.py',
+ output,
+ )
+ print '\tFIXUP\t' + output
+ ret = RunCommand(commandLine)
+ if ret != 0: sys.exit(ret)
+
;------------------------------------------------------------------------------\r
+; @file\r
+; Common macros used in the ResetVector VTF module.\r
;\r
; Copyright (c) 2008, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; CommonMacros.inc\r
-;\r
-; Abstract:\r
-;\r
-; Common macros used in the ResetVector VTF module.\r
-;\r
;------------------------------------------------------------------------------\r
\r
%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)\r
%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)\r
\r
-%macro callEdx 1\r
- mov edx, ADDR_OF(%%returnLabel)\r
- jmp %1\r
-%%returnLabel:\r
-%endmacro\r
-\r
%macro OneTimeCall 1\r
jmp %1\r
%1 %+ OneTimerCallReturn:\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Debug disabled\r
+;\r
+; Copyright (c) 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 16\r
+\r
+%macro debugInitialize 0\r
+ ;\r
+ ; No initialization is required\r
+ ;\r
+%endmacro\r
+\r
+%macro debugShowPostCode 1\r
+%endmacro\r
+\r
;------------------------------------------------------------------------------\r
+; @file\r
+; Transition from 16 bit real mode into 32 bit flat protected mode\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; 16RealTo32Flat.asm\r
-;\r
-; Abstract:\r
-;\r
-; Transition from 16 bit real mode into 32 bit flat protected mode\r
-;\r
;------------------------------------------------------------------------------\r
\r
%define SEC_DEFAULT_CR0 0x40000023\r
\r
BITS 16\r
\r
-to32BitFlat:\r
+;\r
+; Modified: EAX, EBX\r
+;\r
+TransitionFromReal16To32BitFlat:\r
\r
- writeToSerialPort '1'\r
- writeToSerialPort '6'\r
- writeToSerialPort ' '\r
+ debugShowPostCode POSTCODE_16BIT_MODE\r
\r
cli\r
\r
mov eax, SEC_DEFAULT_CR0\r
mov cr0, eax\r
\r
-; mov eax, cr0\r
-; or al, 1\r
-; mov cr0, eax\r
-\r
jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere)\r
BITS 32\r
jumpTo32BitAndLandHere:\r
mov eax, SEC_DEFAULT_CR4\r
mov cr4, eax\r
\r
- writeToSerialPort '3'\r
- writeToSerialPort '2'\r
- writeToSerialPort ' '\r
+ debugShowPostCode POSTCODE_32BIT_MODE\r
\r
- mov ax, LINEAR_SEL\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax\r
+ mov ax, LINEAR_SEL\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
\r
- jmp TransitionFrom16RealTo32FlatComplete\r
+ OneTimeCallRet TransitionFromReal16To32BitFlat\r
\r
ALIGN 2\r
\r
GDT_BASE:\r
; null descriptor\r
NULL_SEL equ $-GDT_BASE\r
- dw 0 ; limit 15:0\r
- dw 0 ; base 15:0\r
- db 0 ; base 23:16\r
- db 0 ; type\r
- db 0 ; limit 19:16, flags\r
- db 0 ; base 31:24\r
+ dw 0 ; limit 15:0\r
+ dw 0 ; base 15:0\r
+ db 0 ; base 23:16\r
+ db 0 ; type\r
+ db 0 ; limit 19:16, flags\r
+ db 0 ; base 31:24\r
\r
; linear data segment descriptor\r
LINEAR_SEL equ $-GDT_BASE\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 092h ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
\r
; linear code segment descriptor\r
LINEAR_CODE_SEL equ $-GDT_BASE\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 09Ah ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
\r
; system data segment descriptor\r
SYS_DATA_SEL equ $-GDT_BASE\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 092h ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
\r
; system code segment descriptor\r
SYS_CODE_SEL equ $-GDT_BASE\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 09Ah ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
\r
; spare segment descriptor\r
LINEAR_CODE64_SEL equ $-GDT_BASE\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
+ DW -1 ; LimitLow\r
+ DW 0 ; BaseLow\r
+ DB 0 ; BaseMid\r
DB 9bh\r
- DB 0afh ; LimitHigh (CS.L=1, CS.D=0)\r
- DB 0 ; BaseHigh\r
+ DB 0afh ; LimitHigh (CS.L=1, CS.D=0)\r
+ DB 0 ; BaseHigh\r
\r
; spare segment descriptor\r
SPARE4_SEL equ $-GDT_BASE\r
- dw 0 ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 0 ; present, ring 0, data, expand-up, writable\r
- db 0 ; page-granular, 32-bit\r
- db 0\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
\r
; spare segment descriptor\r
SPARE5_SEL equ $-GDT_BASE\r
- dw 0 ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 0 ; present, ring 0, data, expand-up, writable\r
- db 0 ; page-granular, 32-bit\r
- db 0\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
\r
GDT_END:\r
\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; 16-bit initialization code\r
+;\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+BITS 16\r
+\r
+;\r
+; @param[out] DI 'BP' to indicate boot-strap processor\r
+;\r
+EarlyBspInitReal16:\r
+ mov di, 'BP'\r
+ jmp short Main16\r
+\r
+;\r
+; @param[out] DI 'AP' to indicate application processor\r
+;\r
+EarlyApInitReal16:\r
+ mov di, 'AP'\r
+ jmp short Main16\r
+\r
+;\r
+; Modified: EAX\r
+;\r
+; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)\r
+; @param[out] ESP Initial value of the EAX register (BIST: Built-in Self Test)\r
+;\r
+EarlyInit16:\r
+ ;\r
+ ; ESP - Initial value of the EAX register (BIST: Built-in Self Test)\r
+ ;\r
+ mov esp, eax\r
+\r
+ debugInitialize\r
+\r
+ OneTimeCallRet EarlyInit16\r
+\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2008, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; Reset-16Bit-old-tools.asm\r
-;\r
-; Abstract:\r
-;\r
-; First code exectuted by processor after resetting.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 16\r
-\r
-earlyInit_Real16:\r
-\r
- jmp real16InitSerialPort\r
-real16SerialPortInitReturn:\r
-\r
- jmp to32BitFlat\r
-\r
-ALIGN 16\r
-\r
-;\r
-; Junk data. Old GenFv tool will modify data here.\r
-;\r
- DQ 0, 0\r
-\r
-;\r
-; Reset Vector\r
-;\r
-; This is where the processor will begin execution\r
-;\r
- jmp short earlyInit_Real16\r
-\r
-;\r
-; Junk data. Old GenFv tool will modify data here.\r
-;\r
-ALIGN 16\r
-\r
-fourGigabytes:\r
-\r
;------------------------------------------------------------------------------\r
+; @file\r
+; First code exectuted by processor after resetting.\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; Reset-16Bit-vft0.asm\r
-;\r
-; Abstract:\r
-;\r
-; First code exectuted by processor after resetting.\r
-;\r
;------------------------------------------------------------------------------\r
\r
-BITS 16\r
-\r
-earlyInit_Real16:\r
+BITS 16\r
\r
- jmp real16InitSerialPort\r
-real16SerialPortInitReturn:\r
+ALIGN 16\r
\r
- jmp to32BitFlat\r
+applicationProcessorEntryPoint:\r
+;\r
+; Application Processors entry point\r
+;\r
+; GenFv generates code aligned on a 4k boundary which will jump to this\r
+; location. (0xffffffe0) This allows the Local APIC Startup IPI to be\r
+; used to wake up the application processors.\r
+;\r
+ jmp short EarlyApInitReal16\r
\r
-ALIGN 16\r
+ALIGN 8\r
\r
- DD 0, 0, 0\r
+ DD 0\r
\r
;\r
; The VTF signature\r
; any fixups.\r
;\r
vtfSignature:\r
- DB 'V', 'T', 'F', 0\r
+ DB 'V', 'T', 'F', 0\r
+\r
+ALIGN 16\r
\r
+resetVector:\r
;\r
; Reset Vector\r
;\r
; This is where the processor will begin execution\r
;\r
- jmp short earlyInit_Real16\r
+ wbinvd\r
+ jmp short EarlyBspInitReal16\r
\r
-ALIGN 16\r
+ALIGN 16\r
\r
fourGigabytes:\r
\r
;------------------------------------------------------------------------------\r
+; @file\r
+; Transition from 32 bit flat protected mode into 64 bit flat protected mode\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; 32FlatTo64Flat.asm\r
-;\r
-; Abstract:\r
-;\r
-; Transition from 32 bit flat protected mode into 64 bit flat protected mode\r
-;\r
;------------------------------------------------------------------------------\r
\r
BITS 32\r
\r
+;\r
+; Modified: EAX\r
+;\r
Transition32FlatTo64Flat:\r
\r
mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)\r
BITS 64\r
jumpTo64BitAndLandHere:\r
\r
- writeToSerialPort '6'\r
- writeToSerialPort '4'\r
- writeToSerialPort ' '\r
+ debugShowPostCode POSTCODE_64BIT_MODE\r
\r
OneTimeCallRet Transition32FlatTo64Flat\r
\r
;------------------------------------------------------------------------------\r
+; @file\r
+; Search for the Boot Firmware Volume (BFV) base address\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; SearchForBfvBase.asm\r
-;\r
-; Abstract:\r
-;\r
-; Search for the Boot FV Base Address\r
-;\r
;------------------------------------------------------------------------------\r
\r
;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \\r
BITS 32\r
\r
;\r
-; Input:\r
-; None\r
+; Modified: EAX, EBX\r
+; Preserved: EDI, ESP\r
;\r
-; Output:\r
-; EBP - BFV Base Address\r
-;\r
-; Modified:\r
-; EAX, EBX\r
+; @param[out] EBP Address of Boot Firmware Volume (BFV)\r
;\r
Flat32SearchForBfvBase:\r
\r
xor eax, eax\r
searchingForBfvHeaderLoop:\r
+ ;\r
+ ; We check for a firmware volume at every 4KB address in the top 16MB\r
+ ; just below 4GB. (Addresses at 0xffHHH000 where H is any hex digit.)\r
+ ;\r
sub eax, 0x1000\r
- cmp eax, 0xff800000\r
+ cmp eax, 0xff000000\r
jb searchedForBfvHeaderButNotFound\r
\r
;\r
jmp searchedForBfvHeaderAndItWasFound\r
\r
searchedForBfvHeaderButNotFound:\r
- writeToSerialPort '!'\r
- xor eax, eax\r
+ ;\r
+ ; Hang if the SEC entry point was not found\r
+ ;\r
+ debugShowPostCode POSTCODE_BFV_NOT_FOUND\r
\r
-searchedForBfvHeaderAndItWasFound:\r
+ ;\r
+ ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed\r
+ ; for debugging purposes.\r
+ ;\r
+ mov eax, 0xBFBFBFBF\r
mov ebp, eax\r
+ jmp $\r
\r
- writeToSerialPort 'B'\r
- writeToSerialPort 'F'\r
- writeToSerialPort 'V'\r
- writeToSerialPort ' '\r
+searchedForBfvHeaderAndItWasFound:\r
+ mov ebp, eax\r
\r
- or ebp, ebp\r
- jz $\r
+ debugShowPostCode POSTCODE_BFV_FOUND\r
\r
OneTimeCallRet Flat32SearchForBfvBase\r
\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2008, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SearchForSecAndPeiEntry.asm\r
-;\r
-; Abstract:\r
-;\r
-; Search for the SEC Core and PEI Core entry points\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 32\r
-\r
-%define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
-%define EFI_FV_FILETYPE_PEI_CORE 0x04\r
-\r
-;\r
-; Input:\r
-; EBP - BFV Base Address\r
-;\r
-; Output:\r
-; ESI - SEC Core Entry Point Address (or 0 if not found)\r
-; EDI - PEI Core Entry Point Address (or 0 if not found)\r
-;\r
-; Modified:\r
-; EAX, EBX, ECX\r
-;\r
-Flat32SearchForSecAndPeiEntries:\r
-\r
- ;\r
- ; Initialize EBP and ESI to 0\r
- ;\r
- xor ebx, ebx\r
- mov esi, ebx\r
- mov edi, ebx\r
-\r
- ;\r
- ; Pass over the BFV header\r
- ;\r
- mov eax, ebp\r
- mov bx, [ebp + 0x30]\r
- add eax, ebx\r
- jc doneSeachingForSecAndPeiEntries\r
-\r
- jmp searchingForFfsFileHeaderLoop\r
-\r
-moveForwardWhileSearchingForFfsFileHeaderLoop:\r
- ;\r
- ; Make forward progress in the search\r
- ;\r
- inc eax\r
- jc doneSeachingForSecAndPeiEntries\r
-\r
-searchingForFfsFileHeaderLoop:\r
- test eax, eax\r
- jz doneSeachingForSecAndPeiEntries\r
-\r
- ;\r
- ; Ensure 8 byte alignment\r
- ;\r
- add eax, 7\r
- jc doneSeachingForSecAndPeiEntries\r
- and al, 0xf8\r
-\r
- ;\r
- ; Look to see if there is an FFS file at eax\r
- ;\r
- mov bl, [eax + 0x17]\r
- test bl, 0x20\r
- jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
- mov ecx, [eax + 0x14]\r
- and ecx, 0x00ffffff\r
- or ecx, ecx\r
- jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
-; jmp $\r
- add ecx, eax\r
- jz jumpSinceWeFoundTheLastFfsFile\r
- jc moveForwardWhileSearchingForFfsFileHeaderLoop\r
-jumpSinceWeFoundTheLastFfsFile:\r
-\r
- ;\r
- ; There seems to be a valid file at eax\r
- ;\r
- mov bl, [eax + 0x12] ; BL - File Type\r
- cmp bl, EFI_FV_FILETYPE_PEI_CORE\r
- je fileTypeIsPeiCore\r
- cmp bl, EFI_FV_FILETYPE_SECURITY_CORE\r
- jne readyToTryFfsFileAtEcx\r
-\r
-fileTypeIsSecCore:\r
- callEdx GetEntryPointOfFfsFileReturnEdx\r
- test eax, eax\r
- jz readyToTryFfsFileAtEcx\r
-\r
- mov esi, eax\r
- jmp readyToTryFfsFileAtEcx\r
-\r
-fileTypeIsPeiCore:\r
- callEdx GetEntryPointOfFfsFileReturnEdx\r
- test eax, eax\r
- jz readyToTryFfsFileAtEcx\r
-\r
- mov edi, eax\r
-\r
-readyToTryFfsFileAtEcx:\r
- mov eax, ecx\r
- jmp searchingForFfsFileHeaderLoop\r
-\r
-doneSeachingForSecAndPeiEntries:\r
-\r
- test esi, esi\r
- jnz secCoreEntryPointWasFound\r
- writeToSerialPort '!'\r
-secCoreEntryPointWasFound:\r
- writeToSerialPort 'S'\r
- writeToSerialPort 'E'\r
- writeToSerialPort 'C'\r
- writeToSerialPort ' '\r
-\r
- test edi, edi\r
- jnz peiCoreEntryPointWasFound\r
- writeToSerialPort '!'\r
-peiCoreEntryPointWasFound:\r
- writeToSerialPort 'P'\r
- writeToSerialPort 'E'\r
- writeToSerialPort 'I'\r
- writeToSerialPort ' '\r
-\r
- OneTimeCallRet Flat32SearchForSecAndPeiEntries\r
-\r
-\r
-%define EFI_SECTION_PE32 0x10\r
-\r
-;\r
-; Input:\r
-; EAX - Start of FFS file\r
-; ECX - End of FFS file\r
-;\r
-; Output:\r
-; EAX - Entry point of PE32 (or 0 if not found)\r
-;\r
-; Modified:\r
-; EBX\r
-;\r
-GetEntryPointOfFfsFileReturnEdx:\r
- test eax, eax\r
- jz getEntryPointOfFfsFileErrorReturn\r
- add eax, 0x18 ; EAX = Start of section\r
-\r
-getEntryPointOfFfsFileLoopForSections:\r
- cmp eax, ecx\r
- jae getEntryPointOfFfsFileErrorReturn\r
-\r
- cmp byte [eax + 3], EFI_SECTION_PE32\r
- je getEntryPointOfFfsFileFoundPe32Section\r
-\r
- ;\r
- ; The section type was not PE32, so move to next section\r
- ;\r
- mov ebx, dword [eax]\r
- and ebx, 0x00ffffff\r
- add eax, ebx\r
- jc getEntryPointOfFfsFileErrorReturn\r
-\r
- ;\r
- ; Ensure that FFS section is 32-bit aligned\r
- ;\r
- add eax, 3\r
- jc getEntryPointOfFfsFileErrorReturn\r
- and al, 0xfc\r
- jmp getEntryPointOfFfsFileLoopForSections\r
-\r
-getEntryPointOfFfsFileFoundPe32Section:\r
- add eax, 4 ; EAX = Start of PE32 image\r
-\r
- mov ebx, eax\r
- cmp word [eax], 'MZ'\r
- jne thereIsNotAnMzSignature\r
- movzx ebx, word [eax + 0x3c]\r
- add ebx, eax\r
-thereIsNotAnMzSignature:\r
-\r
- ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)\r
- cmp word [ebx], 'VZ'\r
- jne thereIsNoVzSignature\r
- ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
- ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +\r
- ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
- add eax, [ebx + 0x8]\r
- add eax, 0x28\r
- movzx ebx, word [ebx + 0x6]\r
- sub eax, ebx\r
- jmp getEntryPointOfFfsFileReturn\r
-\r
-thereIsNoVzSignature:\r
-\r
- ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)\r
- cmp dword [ebx], `PE\x00\x00`\r
- jne getEntryPointOfFfsFileErrorReturn\r
-\r
- ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
- ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));\r
- add eax, [ebx + 0x4 + 0x14 + 0x10]\r
- jmp getEntryPointOfFfsFileReturn\r
-\r
-getEntryPointOfFfsFileErrorReturn:\r
- mov eax, 0\r
-\r
-getEntryPointOfFfsFileReturn:\r
- jmp edx\r
-\r
-\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Search for the SEC Core entry point\r
+;\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 32\r
+\r
+%define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
+\r
+;\r
+; Modified: EAX, EBX, ECX, EDX\r
+; Preserved: EDI, EBP, ESP\r
+;\r
+; @param[in] EBP Address of Boot Firmware Volume (BFV)\r
+; @param[out] ESI SEC Core Entry Point Address\r
+;\r
+Flat32SearchForSecEntryPoint:\r
+\r
+ ;\r
+ ; Initialize EBP and ESI to 0\r
+ ;\r
+ xor ebx, ebx\r
+ mov esi, ebx\r
+\r
+ ;\r
+ ; Pass over the BFV header\r
+ ;\r
+ mov eax, ebp\r
+ mov bx, [ebp + 0x30]\r
+ add eax, ebx\r
+ jc secEntryPointWasNotFound\r
+\r
+ jmp searchingForFfsFileHeaderLoop\r
+\r
+moveForwardWhileSearchingForFfsFileHeaderLoop:\r
+ ;\r
+ ; Make forward progress in the search\r
+ ;\r
+ inc eax\r
+ jc secEntryPointWasNotFound\r
+\r
+searchingForFfsFileHeaderLoop:\r
+ test eax, eax\r
+ jz secEntryPointWasNotFound\r
+\r
+ ;\r
+ ; Ensure 8 byte alignment\r
+ ;\r
+ add eax, 7\r
+ jc secEntryPointWasNotFound\r
+ and al, 0xf8\r
+\r
+ ;\r
+ ; Look to see if there is an FFS file at eax\r
+ ;\r
+ mov bl, [eax + 0x17]\r
+ test bl, 0x20\r
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
+ mov ecx, [eax + 0x14]\r
+ and ecx, 0x00ffffff\r
+ or ecx, ecx\r
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
+ add ecx, eax\r
+ jz jumpSinceWeFoundTheLastFfsFile\r
+ jc moveForwardWhileSearchingForFfsFileHeaderLoop\r
+jumpSinceWeFoundTheLastFfsFile:\r
+\r
+ ;\r
+ ; There seems to be a valid file at eax\r
+ ;\r
+ cmp byte [eax + 0x12], EFI_FV_FILETYPE_SECURITY_CORE ; Check File Type\r
+ jne readyToTryFfsFileAtEcx\r
+\r
+fileTypeIsSecCore:\r
+ OneTimeCall GetEntryPointOfFfsFile\r
+ test eax, eax\r
+ jnz doneSeachingForSecEntryPoint\r
+\r
+readyToTryFfsFileAtEcx:\r
+ ;\r
+ ; Try the next FFS file at ECX\r
+ ;\r
+ mov eax, ecx\r
+ jmp searchingForFfsFileHeaderLoop\r
+\r
+secEntryPointWasNotFound:\r
+ xor eax, eax\r
+\r
+doneSeachingForSecEntryPoint:\r
+ mov esi, eax\r
+\r
+ test esi, esi\r
+ jnz secCoreEntryPointWasFound\r
+\r
+secCoreEntryPointWasNotFound:\r
+ ;\r
+ ; Hang if the SEC entry point was not found\r
+ ;\r
+ debugShowPostCode POSTCODE_SEC_NOT_FOUND\r
+ jz $\r
+\r
+secCoreEntryPointWasFound:\r
+ debugShowPostCode POSTCODE_SEC_FOUND\r
+\r
+ OneTimeCallRet Flat32SearchForSecEntryPoint\r
+\r
+%define EFI_SECTION_PE32 0x10\r
+\r
+;\r
+; Input:\r
+; EAX - Start of FFS file\r
+; ECX - End of FFS file\r
+;\r
+; Output:\r
+; EAX - Entry point of PE32 (or 0 if not found)\r
+;\r
+; Modified:\r
+; EBX\r
+;\r
+GetEntryPointOfFfsFile:\r
+ test eax, eax\r
+ jz getEntryPointOfFfsFileErrorReturn\r
+ add eax, 0x18 ; EAX = Start of section\r
+\r
+getEntryPointOfFfsFileLoopForSections:\r
+ cmp eax, ecx\r
+ jae getEntryPointOfFfsFileErrorReturn\r
+\r
+ cmp byte [eax + 3], EFI_SECTION_PE32\r
+ je getEntryPointOfFfsFileFoundPe32Section\r
+\r
+ ;\r
+ ; The section type was not PE32, so move to next section\r
+ ;\r
+ mov ebx, dword [eax]\r
+ and ebx, 0x00ffffff\r
+ add eax, ebx\r
+ jc getEntryPointOfFfsFileErrorReturn\r
+\r
+ ;\r
+ ; Ensure that FFS section is 32-bit aligned\r
+ ;\r
+ add eax, 3\r
+ jc getEntryPointOfFfsFileErrorReturn\r
+ and al, 0xfc\r
+ jmp getEntryPointOfFfsFileLoopForSections\r
+\r
+getEntryPointOfFfsFileFoundPe32Section:\r
+ add eax, 4 ; EAX = Start of PE32 image\r
+\r
+ mov ebx, eax\r
+ cmp word [eax], 'MZ'\r
+ jne thereIsNotAnMzSignature\r
+ movzx ebx, word [eax + 0x3c]\r
+ add ebx, eax\r
+thereIsNotAnMzSignature:\r
+\r
+ ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)\r
+ cmp word [ebx], 'VZ'\r
+ jne thereIsNoVzSignature\r
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
+ ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +\r
+ ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
+ add eax, [ebx + 0x8]\r
+ add eax, 0x28\r
+ movzx ebx, word [ebx + 0x6]\r
+ sub eax, ebx\r
+ jmp getEntryPointOfFfsFileReturn\r
+\r
+thereIsNoVzSignature:\r
+\r
+ ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)\r
+ cmp dword [ebx], `PE\x00\x00`\r
+ jne getEntryPointOfFfsFileErrorReturn\r
+\r
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
+ ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));\r
+ add eax, [ebx + 0x4 + 0x14 + 0x10]\r
+ jmp getEntryPointOfFfsFileReturn\r
+\r
+getEntryPointOfFfsFileErrorReturn:\r
+ mov eax, 0\r
+\r
+getEntryPointOfFfsFileReturn:\r
+ OneTimeCallRet GetEntryPointOfFfsFile\r
+\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2008, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; JumpToSec.asm\r
-;\r
-; Abstract:\r
-;\r
-; Jump from the reset vector binary to SEC\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 32\r
-\r
-TransitionFrom16RealTo32FlatComplete:\r
-\r
- OneTimeCall Flat32SearchForBfvBase\r
-\r
- OneTimeCall Flat32SearchForSecAndPeiEntries\r
-\r
- ;\r
- ; ESI - SEC Core entry point\r
- ; EDI - PEI Core entry point\r
- ; EBP - Start of BFV\r
- ;\r
- ; Jump to SEC Core entry point\r
- ;\r
-\r
-%ifdef ARCH_IA32\r
-\r
- jmp esi\r
-\r
-%else\r
-\r
- OneTimeCall Transition32FlatTo64Flat\r
-BITS 64\r
-\r
- mov rax, 0x00000000ffffffff\r
- and rsi, rax\r
- and rdi, rax\r
- and rbp, rax\r
- ;\r
- ; RSI - SEC Core entry point\r
- ; RDI - PEI Core entry point\r
- ; RBP - Start of BFV\r
- ;\r
- ; Jump to SEC Core entry point\r
- ;\r
-\r
- jmp rsi\r
-\r
-%endif\r
-\r
-\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Main routine of the pre-SEC code up through the jump into SEC\r
+;\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+BITS 16\r
+\r
+;\r
+; Modified: EBX, ECX, EDX, EBP\r
+;\r
+; @param[in,out] RAX/EAX Initial value of the EAX register\r
+; (BIST: Built-in Self Test)\r
+; @param[in,out] DI 'BP': boot-strap processor, or\r
+; 'AP': application processor\r
+; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV)\r
+;\r
+; @return None This routine jumps to SEC and does not return\r
+;\r
+Main16:\r
+ OneTimeCall EarlyInit16\r
+\r
+ ;\r
+ ; Transition the processor from 16-bit real mode to 32-bit flat mode\r
+ ;\r
+ OneTimeCall TransitionFromReal16To32BitFlat\r
+\r
+BITS 32\r
+\r
+ ;\r
+ ; Search for the Boot Firmware Volume (BFV)\r
+ ;\r
+ OneTimeCall Flat32SearchForBfvBase\r
+\r
+ ;\r
+ ; EBP - Start of BFV\r
+ ;\r
+\r
+ ;\r
+ ; Search for the SEC entry point\r
+ ;\r
+ OneTimeCall Flat32SearchForSecEntryPoint\r
+\r
+ ;\r
+ ; ESI - SEC Core entry point\r
+ ; EBP - Start of BFV\r
+ ;\r
+\r
+%ifdef ARCH_IA32\r
+\r
+ ;\r
+ ; Restore initial EAX value into the EAX register\r
+ ;\r
+ mov eax, esp\r
+\r
+ ;\r
+ ; Jump to the 32-bit SEC entry point\r
+ ;\r
+ jmp esi\r
+\r
+%else\r
+\r
+ ;\r
+ ; Transition the processor from 32-bit flat mode to 64-bit flat mode\r
+ ;\r
+ OneTimeCall Transition32FlatTo64Flat\r
+\r
+BITS 64\r
+\r
+ ;\r
+ ; Some values were calculated in 32-bit mode. Make sure the upper\r
+ ; 32-bits of 64-bit registers are zero for these values.\r
+ ;\r
+ mov rax, 0x00000000ffffffff\r
+ and rsi, rax\r
+ and rbp, rax\r
+ and rsp, rax\r
+\r
+ ;\r
+ ; RSI - SEC Core entry point\r
+ ; RBP - Start of BFV\r
+ ;\r
+\r
+ ;\r
+ ; Restore initial EAX value into the RAX register\r
+ ;\r
+ mov rax, rsp\r
+\r
+ ;\r
+ ; Jump to the 64-bit SEC entry point\r
+ ;\r
+ jmp rsi\r
+\r
+%endif\r
+\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Port 0x80 debug support macros\r
+;\r
+; Copyright (c) 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 16\r
+\r
+%macro debugInitialize 0\r
+ ;\r
+ ; No initialization is required\r
+ ;\r
+%endmacro\r
+\r
+%macro debugShowPostCode 1\r
+ mov al, %1\r
+ out 0x80, al\r
+%endmacro\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; Definitions of POST CODES for the reset vector module\r
+;\r
+; Copyright (c) 2009, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%define POSTCODE_16BIT_MODE 0x16\r
+%define POSTCODE_32BIT_MODE 0x32\r
+%define POSTCODE_64BIT_MODE 0x64\r
+\r
+%define POSTCODE_BFV_NOT_FOUND 0xb0\r
+%define POSTCODE_BFV_FOUND 0xb1\r
+\r
+%define POSTCODE_SEC_NOT_FOUND 0xf0\r
+%define POSTCODE_SEC_FOUND 0xf1\r
+\r
;------------------------------------------------------------------------------\r
+; @file\r
+; This file includes all other code files to assemble the reset vector code\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; ResetVectorCode.asm\r
-;\r
-; Abstract:\r
-;\r
-; Create code for VTF raw section.\r
-;\r
;------------------------------------------------------------------------------\r
\r
%ifdef ARCH_IA32\r
%endif\r
\r
%include "CommonMacros.inc"\r
-%include "SerialDebug.asm"\r
+\r
+%include "PostCodes.inc"\r
+\r
+%ifdef DEBUG_NONE\r
+ %include "DebugDisabled.asm"\r
+%elifdef DEBUG_PORT80\r
+ %include "Port80Debug.asm"\r
+%elifdef DEBUG_SERIAL\r
+ %include "SerialDebug.asm"\r
+%else\r
+ %error "No debug type was specified."\r
+%endif\r
+\r
%include "Ia32/SearchForBfvBase.asm"\r
-%include "Ia32/SearchForSecAndPeiEntries.asm"\r
-%include "JumpToSec.asm"\r
-%include "Ia16/16RealTo32Flat.asm"\r
+%include "Ia32/SearchForSecEntry.asm"\r
\r
%ifdef ARCH_X64\r
%include "Ia32/32FlatTo64Flat.asm"\r
%endif\r
\r
+%include "Ia16/16RealTo32Flat.asm"\r
+%include "Ia16/Init16.asm"\r
+\r
+%include "Main.asm"\r
+\r
%include "Ia16/ResetVectorVtf0.asm"\r
\r
;------------------------------------------------------------------------------\r
+; @file\r
+; Serial port debug support macros\r
;\r
-; Copyright (c) 2008, Intel Corporation\r
+; Copyright (c) 2008 - 2009, Intel Corporation\r
; All rights reserved. This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
-; Module Name:\r
-;\r
-; SerialDebug.asm\r
-;\r
-; Abstract:\r
-;\r
-; Serial port support macros\r
-;\r
;------------------------------------------------------------------------------\r
\r
-BITS 16\r
-\r
;//---------------------------------------------\r
;// UART Register Offsets\r
;//---------------------------------------------\r
out dx, al\r
%endmacro\r
\r
-%macro writeToSerialPort 1\r
+%macro debugShowCharacter 1\r
waitForSerialTxReady\r
outToSerialPort 0, %1\r
%endmacro\r
\r
-real16InitSerialPort:\r
+%macro debugShowHexDigit 1\r
+ %if (%1 < 0xa)\r
+ debugShowCharacter BYTE ('0' + (%1))\r
+ %else\r
+ debugShowCharacter BYTE ('a' + ((%1) - 0xa))\r
+ %endif\r
+%endmacro\r
+\r
+%macro debugNewline 0\r
+ debugShowCharacter `\r`\r
+ debugShowCharacter `\n`\r
+%endmacro\r
+\r
+%macro debugShowPostCode 1\r
+ debugShowHexDigit (((%1) >> 4) & 0xf)\r
+ debugShowHexDigit ((%1) & 0xf)\r
+ debugNewline\r
+%endmacro\r
+\r
+BITS 16\r
+\r
+%macro debugInitialize 0\r
+ jmp real16InitDebug\r
+real16InitDebugReturn:\r
+%endmacro\r
+\r
+real16InitDebug:\r
;\r
; Set communications format\r
;\r
;\r
outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r
\r
- jmp real16SerialPortInitReturn\r
+ jmp real16InitDebugReturn\r
\r
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