UefiCpuPkg/PiSmmCpuDxeSmm: remove DBs from SmmRelocationSemaphoreComplete32()

(1) SmmRelocationSemaphoreComplete32() runs in 32-bit mode, so wrap it in
    a (BITS 32 ... BITS 64) bracket.

(2) SmmRelocationSemaphoreComplete32() currently compiles to:

> 000002AE  C6050000000001    mov byte [dword 0x0],0x1
> 000002B5  FF2500000000      jmp dword [dword 0x0]

    where the first instruction is patched with the contents of
    "mRebasedFlag" (so that (*mRebasedFlag) is set to 1), and the second
    instruction is patched with the address of
    "mSmmRelocationOriginalAddress" (so that we jump to
    "mSmmRelocationOriginalAddress").

    In its current form the first instruction could not be patched with
    PatchInstructionX86(), given that the operand to patch is not encoded
    in the trailing bytes of the instruction. Therefore, adopt an
    EAX-based version, inspired by both the IA32 and X64 variants of
    SmmRelocationSemaphoreComplete():

> 000002AE  50                push eax
> 000002AF  B800000000        mov eax,0x0
> 000002B4  C60001            mov byte [eax],0x1
> 000002B7  58                pop eax
> 000002B8  FF2500000000      jmp dword [dword 0x0]

    Here both instructions can be patched with PatchInstructionX86(), and
    the DBs can be replaced with native NASM syntax.

(3) Turn the "mRebasedFlagAddr32" and "mSmmRelocationOriginalAddressPtr32"
    variables into markers that suit PatchInstructionX86().

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 6dbcb086aa4dbadcf949ee2f0ff26f4cf589aea5..87f595ddb8c3e432537bd50369cea492a4f169e5 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -15,8 +15,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r

-extern  UINT32    mSmmRelocationOriginalAddressPtr32;\r
-extern  UINT32    mRebasedFlagAddr32;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32;\r

 \r
 UINTN             mSmmRelocationOriginalAddress;\r
 volatile BOOLEAN  *mRebasedFlag;\r
 \r
 UINTN             mSmmRelocationOriginalAddress;\r
 volatile BOOLEAN  *mRebasedFlag;\r


@@ -49,7 +49,11 @@ SemaphoreHook (
   UINTN                 TempValue;\r
 \r
   mRebasedFlag       = RebasedFlag;\r
   UINTN                 TempValue;\r
 \r
   mRebasedFlag       = RebasedFlag;\r

-  mRebasedFlagAddr32 = (UINT32)(UINTN)mRebasedFlag;\r
+  PatchInstructionX86 (\r
+    gPatchRebasedFlagAddr32,\r
+    (UINT32)(UINTN)mRebasedFlag,\r
+    4\r
+    );\r

 \r
   CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
   mSmmRelocationOriginalAddress = HookReturnFromSmm (\r
 \r
   CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
   mSmmRelocationOriginalAddress = HookReturnFromSmm (\r


@@ -63,5 +67,9 @@ SemaphoreHook (
   // Use temp value to fix ICC complier warning\r
   //\r
   TempValue = (UINTN)&mSmmRelocationOriginalAddress;\r
   // Use temp value to fix ICC complier warning\r
   //\r
   TempValue = (UINTN)&mSmmRelocationOriginalAddress;\r

-  mSmmRelocationOriginalAddressPtr32 = (UINT32)TempValue;\r
+  PatchInstructionX86 (\r
+    gPatchSmmRelocationOriginalAddressPtr32,\r
+    (UINT32)TempValue,\r
+    4\r
+    );\r

 }\r
 }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index eae14c0549f0d9a04a7d59bfe113845f62232ea2..0b0c3f28e53fa04c7733dee48ddd6704fdb10686 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -29,8 +29,8 @@ global ASM_PFX(gPatchSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
 global ASM_PFX(gcSmmInitTemplate)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
 global ASM_PFX(gcSmmInitTemplate)\r

-global ASM_PFX(mRebasedFlagAddr32)\r
-global ASM_PFX(mSmmRelocationOriginalAddressPtr32)\r
+global ASM_PFX(gPatchRebasedFlagAddr32)\r
+global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)\r

 \r
 %define LONG_MODE_CS 0x38\r
 \r
 \r
 %define LONG_MODE_CS 0x38\r
 \r


@@ -125,20 +125,18 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
 ;\r
 ; Semaphore code running in 32-bit mode\r
 ;\r
 ;\r
 ; Semaphore code running in 32-bit mode\r
 ;\r

+BITS 32\r

 global ASM_PFX(SmmRelocationSemaphoreComplete32)\r
 ASM_PFX(SmmRelocationSemaphoreComplete32):\r
 global ASM_PFX(SmmRelocationSemaphoreComplete32)\r
 ASM_PFX(SmmRelocationSemaphoreComplete32):\r

-    ;\r
-    ; mov byte ptr [], 1\r
-    ;\r
-    db      0xc6, 0x5\r
-ASM_PFX(mRebasedFlagAddr32): dd 0\r
-    db      1\r
-    ;\r
-    ; jmp dword ptr []\r
-    ;\r
-    db      0xff, 0x25\r
-ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
+    push    eax\r
+    mov     eax, strict dword 0                ; source operand will be patched\r
+ASM_PFX(gPatchRebasedFlagAddr32):\r
+    mov     byte [eax], 1\r
+    pop     eax\r
+    jmp     dword [dword 0]                    ; destination will be patched\r
+ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):\r

 \r
 \r

+BITS 64\r

 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
 ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
     lea    rax, [@LongMode]\r
 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
 ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
     lea    rax, [@LongMode]\r