+/** @file\r
+ CPU DXE Module.\r
+\r
+ Copyright (c) 2008 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CpuDxe.h"\r
+\r
+//\r
+// Global Variables\r
+//\r
+IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };\r
+\r
+EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];\r
+BOOLEAN InterruptState = FALSE;\r
+EFI_HANDLE mCpuHandle = NULL;\r
+BOOLEAN mIsFlushingGCD;\r
+UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;\r
+UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
+UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
+\r
+FIXED_MTRR mFixedMtrrTable[] = {\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX64K_00000,\r
+ 0,\r
+ 0x10000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX16K_80000,\r
+ 0x80000,\r
+ 0x4000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r
+ 0xA0000,\r
+ 0x4000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r
+ 0xC0000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r
+ 0xC8000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r
+ 0xD0000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r
+ 0xD8000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r
+ 0xE0000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r
+ 0xE8000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r
+ 0xF0000,\r
+ 0x1000\r
+ },\r
+ {\r
+ MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r
+ 0xF8000,\r
+ 0x1000\r
+ },\r
+};\r
+\r
+\r
+EFI_CPU_ARCH_PROTOCOL gCpu = {\r
+ CpuFlushCpuDataCache,\r
+ CpuEnableInterrupt,\r
+ CpuDisableInterrupt,\r
+ CpuGetInterruptState,\r
+ CpuInit,\r
+ CpuRegisterInterruptHandler,\r
+ CpuGetTimerValue,\r
+ CpuSetMemoryAttributes,\r
+ 1, // NumberOfTimers\r
+ 4 // DmaBufferAlignment\r
+};\r
+\r
+//\r
+// Error code flag indicating whether or not an error code will be\r
+// pushed on the stack if an exception occurs.\r
+//\r
+// 1 means an error code will be pushed, otherwise 0\r
+//\r
+// bit 0 - exception 0\r
+// bit 1 - exception 1\r
+// etc.\r
+//\r
+UINT32 mErrorCodeFlag = 0x00027d00;\r
+\r
+//\r
+// CPU Arch Protocol Functions\r
+//\r
+\r
+\r
+/**\r
+ Common exception handler.\r
+\r
+ @param InterruptType Exception type\r
+ @param SystemContext EFI_SYSTEM_CONTEXT\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CommonExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
+ )\r
+{\r
+#if defined (MDE_CPU_IA32)\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "!!!! IA32 Exception Type - %08x !!!!\n",\r
+ InterruptType\r
+ ));\r
+ if (mErrorCodeFlag & (1 << InterruptType)) {\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "ExceptionData - %08x\n",\r
+ SystemContext.SystemContextIa32->ExceptionData\r
+ ));\r
+ }\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",\r
+ SystemContext.SystemContextIa32->Cs,\r
+ SystemContext.SystemContextIa32->Eip,\r
+ SystemContext.SystemContextIa32->Eflags,\r
+ SystemContext.SystemContextIa32->Ss\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",\r
+ SystemContext.SystemContextIa32->Ds,\r
+ SystemContext.SystemContextIa32->Es,\r
+ SystemContext.SystemContextIa32->Fs,\r
+ SystemContext.SystemContextIa32->Gs\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",\r
+ SystemContext.SystemContextIa32->Eax,\r
+ SystemContext.SystemContextIa32->Ebx,\r
+ SystemContext.SystemContextIa32->Ecx,\r
+ SystemContext.SystemContextIa32->Edx\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",\r
+ SystemContext.SystemContextIa32->Esp,\r
+ SystemContext.SystemContextIa32->Ebp,\r
+ SystemContext.SystemContextIa32->Esi,\r
+ SystemContext.SystemContextIa32->Edi\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",\r
+ SystemContext.SystemContextIa32->Gdtr[0],\r
+ SystemContext.SystemContextIa32->Gdtr[1],\r
+ SystemContext.SystemContextIa32->Idtr[0],\r
+ SystemContext.SystemContextIa32->Idtr[1]\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "LDT - %08x, TR - %08x\n",\r
+ SystemContext.SystemContextIa32->Ldtr,\r
+ SystemContext.SystemContextIa32->Tr\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",\r
+ SystemContext.SystemContextIa32->Cr0,\r
+ SystemContext.SystemContextIa32->Cr2,\r
+ SystemContext.SystemContextIa32->Cr3,\r
+ SystemContext.SystemContextIa32->Cr4\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",\r
+ SystemContext.SystemContextIa32->Dr0,\r
+ SystemContext.SystemContextIa32->Dr1,\r
+ SystemContext.SystemContextIa32->Dr2,\r
+ SystemContext.SystemContextIa32->Dr3\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "DR6 - %08x, DR7 - %08x\n",\r
+ SystemContext.SystemContextIa32->Dr6,\r
+ SystemContext.SystemContextIa32->Dr7\r
+ ));\r
+#elif defined (MDE_CPU_X64)\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "!!!! X64 Exception Type - %016lx !!!!\n",\r
+ (UINT64)InterruptType\r
+ ));\r
+ if (mErrorCodeFlag & (1 << InterruptType)) {\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "ExceptionData - %016lx\n",\r
+ SystemContext.SystemContextX64->ExceptionData\r
+ ));\r
+ }\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "RIP - %016lx, RFL - %016lx\n",\r
+ SystemContext.SystemContextX64->Rip,\r
+ SystemContext.SystemContextX64->Rflags\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",\r
+ SystemContext.SystemContextX64->Rax,\r
+ SystemContext.SystemContextX64->Rcx,\r
+ SystemContext.SystemContextX64->Rdx\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",\r
+ SystemContext.SystemContextX64->Rbx,\r
+ SystemContext.SystemContextX64->Rsp,\r
+ SystemContext.SystemContextX64->Rbp\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "RSI - %016lx, RDI - %016lx\n",\r
+ SystemContext.SystemContextX64->Rsi,\r
+ SystemContext.SystemContextX64->Rdi\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "R8 - %016lx, R9 - %016lx, R10 - %016lx\n",\r
+ SystemContext.SystemContextX64->R8,\r
+ SystemContext.SystemContextX64->R9,\r
+ SystemContext.SystemContextX64->R10\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",\r
+ SystemContext.SystemContextX64->R11,\r
+ SystemContext.SystemContextX64->R12,\r
+ SystemContext.SystemContextX64->R13\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "R14 - %016lx, R15 - %016lx\n",\r
+ SystemContext.SystemContextX64->R14,\r
+ SystemContext.SystemContextX64->R15\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",\r
+ SystemContext.SystemContextX64->Cs,\r
+ SystemContext.SystemContextX64->Ds,\r
+ SystemContext.SystemContextX64->Es,\r
+ SystemContext.SystemContextX64->Fs,\r
+ SystemContext.SystemContextX64->Gs,\r
+ SystemContext.SystemContextX64->Ss\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",\r
+ SystemContext.SystemContextX64->Gdtr[0],\r
+ SystemContext.SystemContextX64->Gdtr[1],\r
+ SystemContext.SystemContextX64->Idtr[0],\r
+ SystemContext.SystemContextX64->Idtr[1]\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "LDT - %016lx, TR - %016lx\n",\r
+ SystemContext.SystemContextX64->Ldtr,\r
+ SystemContext.SystemContextX64->Tr\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",\r
+ SystemContext.SystemContextX64->Cr0,\r
+ SystemContext.SystemContextX64->Cr2,\r
+ SystemContext.SystemContextX64->Cr3\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "CR4 - %016lx, CR8 - %016lx\n",\r
+ SystemContext.SystemContextX64->Cr4,\r
+ SystemContext.SystemContextX64->Cr8\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",\r
+ SystemContext.SystemContextX64->Dr0,\r
+ SystemContext.SystemContextX64->Dr1,\r
+ SystemContext.SystemContextX64->Dr2\r
+ ));\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",\r
+ SystemContext.SystemContextX64->Dr3,\r
+ SystemContext.SystemContextX64->Dr6,\r
+ SystemContext.SystemContextX64->Dr7\r
+ ));\r
+#else\r
+#error CPU type not supported for exception information dump!\r
+#endif\r
+\r
+ //\r
+ // Hang the system with CpuSleep so the processor will enter a lower power\r
+ // state.\r
+ //\r
+ while (TRUE) {\r
+ CpuSleep ();\r
+ };\r
+}\r
+\r
+\r
+/**\r
+ Flush CPU data cache. If the instruction cache is fully coherent\r
+ with all DMA operations then function can just return EFI_SUCCESS.\r
+\r
+ @param This Protocol instance structure\r
+ @param Start Physical address to start flushing from.\r
+ @param Length Number of bytes to flush. Round up to chipset\r
+ granularity.\r
+ @param FlushType Specifies the type of flush operation to perform.\r
+\r
+ @retval EFI_SUCCESS If cache was flushed\r
+ @retval EFI_UNSUPPORTED If flush type is not supported.\r
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuFlushCpuDataCache (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS Start,\r
+ IN UINT64 Length,\r
+ IN EFI_CPU_FLUSH_TYPE FlushType\r
+ )\r
+{\r
+ if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r
+ AsmWbinvd ();\r
+ return EFI_SUCCESS;\r
+ } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r
+ AsmInvd ();\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+ @param This Protocol instance structure\r
+\r
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU\r
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuEnableInterrupt (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
+ )\r
+{\r
+ EnableInterrupts ();\r
+\r
+ InterruptState = TRUE;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+ @param This Protocol instance structure\r
+\r
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuDisableInterrupt (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
+ )\r
+{\r
+ DisableInterrupts ();\r
+\r
+ InterruptState = FALSE;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Return the state of interrupts.\r
+\r
+ @param This Protocol instance structure\r
+ @param State Pointer to the CPU's current interrupt state\r
+\r
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
+ @retval EFI_INVALID_PARAMETER State is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuGetInterruptState (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ OUT BOOLEAN *State\r
+ )\r
+{\r
+ if (State == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *State = InterruptState;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Generates an INIT to the CPU.\r
+\r
+ @param This Protocol instance structure\r
+ @param InitType Type of CPU INIT to perform\r
+\r
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
+ seen.\r
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.\r
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuInit (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_CPU_INIT_TYPE InitType\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ Registers a function to be called from the CPU interrupt handler.\r
+\r
+ @param This Protocol instance structure\r
+ @param InterruptType Defines which interrupt to hook. IA-32\r
+ valid range is 0x00 through 0xFF\r
+ @param InterruptHandler A pointer to a function of type\r
+ EFI_CPU_INTERRUPT_HANDLER that is called\r
+ when a processor interrupt occurs. A null\r
+ pointer is an error condition.\r
+\r
+ @retval EFI_SUCCESS If handler installed or uninstalled.\r
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
+ for InterruptType was previously installed.\r
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
+ InterruptType was not previously installed.\r
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
+ is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuRegisterInterruptHandler (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+ )\r
+{\r
+ if (InterruptType < 0 || InterruptType > 0xff) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {\r
+ return EFI_ALREADY_STARTED;\r
+ }\r
+\r
+ ExternalVectorTable[InterruptType] = InterruptHandler;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Returns a timer value from one of the CPU's internal timers. There is no\r
+ inherent time interval between ticks but is a function of the CPU frequency.\r
+\r
+ @param This - Protocol instance structure.\r
+ @param TimerIndex - Specifies which CPU timer is requested.\r
+ @param TimerValue - Pointer to the returned timer value.\r
+ @param TimerPeriod - A pointer to the amount of time that passes\r
+ in femtoseconds (10-15) for each increment\r
+ of TimerValue. If TimerValue does not\r
+ increment at a predictable rate, then 0 is\r
+ returned. The amount of time that has\r
+ passed between two calls to GetTimerValue()\r
+ can be calculated with the formula\r
+ (TimerValue2 - TimerValue1) * TimerPeriod.\r
+ This parameter is optional and may be NULL.\r
+\r
+ @retval EFI_SUCCESS - If the CPU timer count was returned.\r
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuGetTimerValue (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN UINT32 TimerIndex,\r
+ OUT UINT64 *TimerValue,\r
+ OUT UINT64 *TimerPeriod OPTIONAL\r
+ )\r
+{\r
+ if (TimerValue == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (TimerIndex != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *TimerValue = AsmReadTsc ();\r
+\r
+ if (TimerPeriod != NULL) {\r
+ //\r
+ // BugBug: Hard coded. Don't know how to do this generically\r
+ //\r
+ *TimerPeriod = 1000000000;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Set memory cacheability attributes for given range of memeory.\r
+\r
+ @param This Protocol instance structure\r
+ @param BaseAddress Specifies the start address of the\r
+ memory range\r
+ @param Length Specifies the length of the memory range\r
+ @param Attributes The memory cacheability for the memory range\r
+\r
+ @retval EFI_SUCCESS If the cacheability of that memory range is\r
+ set successfully\r
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done\r
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
+ such as Length = 0\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuSetMemoryAttributes (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ RETURN_STATUS Status;\r
+ MTRR_MEMORY_CACHE_TYPE CacheType;\r
+\r
+ DEBUG((EFI_D_ERROR, "CpuAp: SetMemorySpaceAttributes(BA=%08x, Len=%08x, Attr=%08x)\n", BaseAddress, Length, Attributes));\r
+\r
+ //\r
+ // If this function is called because GCD SetMemorySpaceAttributes () is called\r
+ // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r
+ // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r
+ // to avoid unnecessary computing.\r
+ //\r
+ if (mIsFlushingGCD) {\r
+ DEBUG((EFI_D_ERROR, " Flushing GCD\n"));\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ switch (Attributes) {\r
+ case EFI_MEMORY_UC:\r
+ CacheType = CacheUncacheable;\r
+ break;\r
+\r
+ case EFI_MEMORY_WC:\r
+ CacheType = CacheWriteCombining;\r
+ break;\r
+\r
+ case EFI_MEMORY_WT:\r
+ CacheType = CacheWriteThrough;\r
+ break;\r
+\r
+ case EFI_MEMORY_WP:\r
+ CacheType = CacheWriteProtected;\r
+ break;\r
+\r
+ case EFI_MEMORY_WB:\r
+ CacheType = CacheWriteBack;\r
+ break;\r
+\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ //\r
+ // call MTRR libary function\r
+ //\r
+ DEBUG((EFI_D_ERROR, " MtrrSetMemoryAttribute()\n"));\r
+ Status = MtrrSetMemoryAttribute(\r
+ BaseAddress,\r
+ Length,\r
+ CacheType\r
+ );\r
+\r
+ MtrrDebugPrintAllMtrrs ();\r
+\r
+ return (EFI_STATUS) Status;\r
+}\r
+\r
+/**\r
+ Initializes the valid bits mask and valid address mask for MTRRs.\r
+\r
+ This function initializes the valid bits mask and valid address mask for MTRRs.\r
+\r
+**/\r
+VOID\r
+InitializeMtrrMask (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINT8 PhysicalAddressBits;\r
+\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+\r
+ if (RegEax >= 0x80000008) {\r
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
+\r
+ PhysicalAddressBits = (UINT8) RegEax;\r
+\r
+ mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
+ mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
+ } else {\r
+ mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
+ mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
+ }\r
+}\r
+\r
+/**\r
+ Gets GCD Mem Space type from MTRR Type\r
+\r
+ This function gets GCD Mem Space type from MTRR Type\r
+\r
+ @param MtrrAttribute MTRR memory type\r
+\r
+ @return GCD Mem Space type\r
+\r
+**/\r
+UINT64\r
+GetMemorySpaceAttributeFromMtrrType (\r
+ IN UINT8 MtrrAttributes\r
+ )\r
+{\r
+ switch (MtrrAttributes) {\r
+ case MTRR_CACHE_UNCACHEABLE:\r
+ return EFI_MEMORY_UC;\r
+ case MTRR_CACHE_WRITE_COMBINING:\r
+ return EFI_MEMORY_WC;\r
+ case MTRR_CACHE_WRITE_THROUGH:\r
+ return EFI_MEMORY_WT;\r
+ case MTRR_CACHE_WRITE_PROTECTED:\r
+ return EFI_MEMORY_WP;\r
+ case MTRR_CACHE_WRITE_BACK:\r
+ return EFI_MEMORY_WB;\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ Searches memory descriptors covered by given memory range.\r
+\r
+ This function searches into the Gcd Memory Space for descriptors\r
+ (from StartIndex to EndIndex) that contains the memory range\r
+ specified by BaseAddress and Length.\r
+\r
+ @param MemorySpaceMap Gcd Memory Space Map as array.\r
+ @param NumberOfDescriptors Number of descriptors in map.\r
+ @param BaseAddress BaseAddress for the requested range.\r
+ @param Length Length for the requested range.\r
+ @param StartIndex Start index into the Gcd Memory Space Map.\r
+ @param EndIndex End index into the Gcd Memory Space Map.\r
+\r
+ @retval EFI_SUCCESS Search successfully.\r
+ @retval EFI_NOT_FOUND The requested descriptors does not exist.\r
+\r
+**/\r
+EFI_STATUS\r
+SearchGcdMemorySpaces (\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ OUT UINTN *StartIndex,\r
+ OUT UINTN *EndIndex\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ *StartIndex = 0;\r
+ *EndIndex = 0;\r
+ for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
+ if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
+ BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ *StartIndex = Index;\r
+ }\r
+ if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
+ BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ *EndIndex = Index;\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+ Sets the attributes for a specified range in Gcd Memory Space Map.\r
+\r
+ This function sets the attributes for a specified range in\r
+ Gcd Memory Space Map.\r
+\r
+ @param MemorySpaceMap Gcd Memory Space Map as array\r
+ @param NumberOfDescriptors Number of descriptors in map\r
+ @param BaseAddress BaseAddress for the range\r
+ @param Length Length for the range\r
+ @param Attributes Attributes to set\r
+\r
+ @retval EFI_SUCCESS Memory attributes set successfully\r
+ @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r
+\r
+**/\r
+EFI_STATUS\r
+SetGcdMemorySpaceAttributes (\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN StartIndex;\r
+ UINTN EndIndex;\r
+ EFI_PHYSICAL_ADDRESS RegionStart;\r
+ UINT64 RegionLength;\r
+\r
+ //\r
+ // Get all memory descriptors covered by the memory range\r
+ //\r
+ Status = SearchGcdMemorySpaces (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ BaseAddress,\r
+ Length,\r
+ &StartIndex,\r
+ &EndIndex\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Go through all related descriptors and set attributes accordingly\r
+ //\r
+ for (Index = StartIndex; Index <= EndIndex; Index++) {\r
+ if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
+ continue;\r
+ }\r
+ //\r
+ // Calculate the start and end address of the overlapping range\r
+ //\r
+ if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
+ RegionStart = BaseAddress;\r
+ } else {\r
+ RegionStart = MemorySpaceMap[Index].BaseAddress;\r
+ }\r
+ if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ RegionLength = BaseAddress + Length - RegionStart;\r
+ } else {\r
+ RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
+ }\r
+ //\r
+ // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
+ //\r
+ gDS->SetMemorySpaceAttributes (\r
+ RegionStart,\r
+ RegionLength,\r
+ (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
+ );\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Refreshes the GCD Memory Space attributes according to MTRRs.\r
+\r
+ This function refreshes the GCD Memory Space attributes according to MTRRs.\r
+\r
+**/\r
+VOID\r
+RefreshGcdMemoryAttributes (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN SubIndex;\r
+ UINT64 RegValue;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ UINT64 Length;\r
+ UINT64 Attributes;\r
+ UINT64 CurrentAttributes;\r
+ UINT8 MtrrType;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
+ UINT64 DefaultAttributes;\r
+ VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+ MTRR_FIXED_SETTINGS MtrrFixedSettings;\r
+\r
+// mIsFlushingGCD = TRUE;\r
+ mIsFlushingGCD = FALSE;\r
+ MemorySpaceMap = NULL;\r
+\r
+ //\r
+ // Initialize the valid bits mask and valid address mask for MTRRs\r
+ //\r
+ InitializeMtrrMask ();\r
+\r
+ //\r
+ // Get the memory attribute of variable MTRRs\r
+ //\r
+ MtrrGetMemoryAttributeInVariableMtrr (\r
+ mValidMtrrBitsMask,\r
+ mValidMtrrAddressMask,\r
+ VariableMtrr\r
+ );\r
+\r
+ //\r
+ // Get the memory space map from GCD\r
+ //\r
+ Status = gDS->GetMemorySpaceMap (\r
+ &NumberOfDescriptors,\r
+ &MemorySpaceMap\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);\r
+\r
+ //\r
+ // Set default attributes to all spaces.\r
+ //\r
+ for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
+ if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
+ continue;\r
+ }\r
+ gDS->SetMemorySpaceAttributes (\r
+ MemorySpaceMap[Index].BaseAddress,\r
+ MemorySpaceMap[Index].Length,\r
+ (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r
+ (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r
+ );\r
+ }\r
+\r
+ //\r
+ // Go for variable MTRRs with WB attribute\r
+ //\r
+ for (Index = 0; Index < FIRMWARE_VARIABLE_MTRR_NUMBER; Index++) {\r
+ if (VariableMtrr[Index].Valid &&\r
+ VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ VariableMtrr[Index].BaseAddress,\r
+ VariableMtrr[Index].Length,\r
+ EFI_MEMORY_WB\r
+ );\r
+ }\r
+ }\r
+ //\r
+ // Go for variable MTRRs with Non-WB attribute\r
+ //\r
+ for (Index = 0; Index < FIRMWARE_VARIABLE_MTRR_NUMBER; Index++) {\r
+ if (VariableMtrr[Index].Valid &&\r
+ VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {\r
+ Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ VariableMtrr[Index].BaseAddress,\r
+ VariableMtrr[Index].Length,\r
+ Attributes\r
+ );\r
+ }\r
+ }\r
+\r
+ //\r
+ // Go for fixed MTRRs\r
+ //\r
+ Attributes = 0;\r
+ BaseAddress = 0;\r
+ Length = 0;\r
+ MtrrGetFixedMtrr (&MtrrFixedSettings);\r
+ for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
+ RegValue = MtrrFixedSettings.Mtrr[Index];\r
+ //\r
+ // Check for continuous fixed MTRR sections\r
+ //\r
+ for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r
+ MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r
+ CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r
+ if (Length == 0) {\r
+ //\r
+ // A new MTRR attribute begins\r
+ //\r
+ Attributes = CurrentAttributes;\r
+ } else {\r
+ //\r
+ // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r
+ //\r
+ if (CurrentAttributes != Attributes) {\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ BaseAddress,\r
+ Length,\r
+ Attributes\r
+ );\r
+ BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r
+ Length = 0;\r
+ Attributes = CurrentAttributes;\r
+ }\r
+ }\r
+ Length += mFixedMtrrTable[Index].Length;\r
+ }\r
+ }\r
+ //\r
+ // Handle the last fixed MTRR region\r
+ //\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ BaseAddress,\r
+ Length,\r
+ Attributes\r
+ );\r
+\r
+ //\r
+ // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r
+ //\r
+ if (MemorySpaceMap != NULL) {\r
+ FreePool (MemorySpaceMap);\r
+ }\r
+\r
+ mIsFlushingGCD = FALSE;\r
+}\r
+\r
+\r
+/**\r
+ Initialize Interrupt Descriptor Table for interrupt handling.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+InitInterruptDescriptorTable (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *IdtPtrAlignmentBuffer;\r
+ IA32_DESCRIPTOR *IdtPtr;\r
+ UINTN Index;\r
+ UINTN CurrentHandler;\r
+\r
+ SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);\r
+\r
+ //\r
+ // Intialize IDT\r
+ //\r
+ CurrentHandler = (UINTN)AsmIdtVector00;\r
+ for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++, CurrentHandler += 0x08) {\r
+ gIdtTable[Index].Bits.OffsetLow = (UINT16)CurrentHandler;\r
+ gIdtTable[Index].Bits.Selector = AsmReadCs();\r
+ gIdtTable[Index].Bits.Reserved_0 = 0;\r
+ gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
+ gIdtTable[Index].Bits.OffsetHigh = (UINT16)(CurrentHandler >> 16);\r
+#if defined (MDE_CPU_X64)\r
+ gIdtTable[Index].Bits.OffsetUpper = (UINT32)(CurrentHandler >> 32);\r
+ gIdtTable[Index].Bits.Reserved_1 = 0;\r
+#endif\r
+ }\r
+\r
+ //\r
+ // Load IDT Pointer\r
+ //\r
+ IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);\r
+ IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);\r
+ IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));\r
+ IdtPtr->Limit = sizeof (gIdtTable) - 1;\r
+ AsmWriteIdtr (IdtPtr);\r
+ FreePool (IdtPtrAlignmentBuffer);\r
+\r
+ //\r
+ // Initialize Exception Handlers\r
+ //\r
+ for (Index = 0; Index < 32; Index++) {\r
+ Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Set the pointer to the array of C based exception handling routines.\r
+ //\r
+ InitializeExternalVectorTablePtr (ExternalVectorTable);\r
+\r
+}\r
+\r
+\r
+/**\r
+ Initialize the state information for the CPU Architectural Protocol.\r
+\r
+ @param ImageHandle Image handle this driver.\r
+ @param SystemTable Pointer to the System Table.\r
+\r
+ @retval EFI_SUCCESS Thread can be successfully created\r
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
+ @retval EFI_DEVICE_ERROR Cannot create the thread\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpu (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Make sure interrupts are disabled\r
+ //\r
+ DisableInterrupts ();\r
+\r
+ //\r
+ // Init GDT for DXE\r
+ //\r
+ InitGlobalDescriptorTable ();\r
+\r
+ //\r
+ // Setup IDT pointer, IDT and interrupt entry points\r
+ //\r
+ InitInterruptDescriptorTable ();\r
+\r
+ //\r
+ // Install CPU Architectural Protocol\r
+ //\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &mCpuHandle,\r
+ &gEfiCpuArchProtocolGuid, &gCpu,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Refresh GCD memory space map according to MTRR value.\r
+ //\r
+ RefreshGcdMemoryAttributes ();\r
+\r
+ return Status;\r
+}\r
+\r