VOID\r
);\r
\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheToPoU (\r
- VOID\r
- );\r
-\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
}\r
}\r
\r
-\r
-VOID\r
-AArch64PoUDataCacheOperation (\r
- IN AARCH64_CACHE_OPERATION DataCacheOperation\r
- )\r
-{\r
- UINTN SavedInterruptState;\r
-\r
- SavedInterruptState = ArmGetInterruptState ();\r
- ArmDisableInterrupts ();\r
-\r
- AArch64PerformPoUDataCacheOperation (DataCacheOperation);\r
-\r
- ArmDrainWriteBuffer ();\r
-\r
- if (SavedInterruptState) {\r
- ArmEnableInterrupts ();\r
- }\r
-}\r
-\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
ArmDrainWriteBuffer ();\r
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheToPoU (\r
- VOID\r
- )\r
-{\r
- ArmDrainWriteBuffer ();\r
- AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
-}\r
\r
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);\r
\r
-\r
-VOID\r
-AArch64PerformPoUDataCacheOperation (\r
- IN AARCH64_CACHE_OPERATION DataCacheOperation\r
- );\r
-\r
VOID\r
AArch64AllDataCachesOperation (\r
IN AARCH64_CACHE_OPERATION DataCacheOperation\r
GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
-GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
// right to ease the access to CSSELR and the Set/Way operation.\r
cbz x3, L_Finished // No need to clean if LoC is 0\r
mov x10, #0 // Start clean at cache level 0\r
- b Loop1\r
-\r
-ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
-// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack. - The stack must always be quad-word aligned\r
- str x30, [sp, #-16]!\r
- mov x1, x0 // Save Function call in x1\r
- mrs x6, clidr_el1 // Read EL1 CLIDR\r
- and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)\r
- lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the\r
- // right to ease the access to CSSELR and the Set/Way operation.\r
- cbz x3, L_Finished // No need to clean if LoC is 0\r
- mov x10, #0 // Start clean at cache level 0\r
\r
Loop1:\r
add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info\r
}\r
}\r
\r
-\r
-VOID\r
-ArmV7PoUDataCacheOperation (\r
- IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
- )\r
-{\r
- UINTN SavedInterruptState;\r
-\r
- SavedInterruptState = ArmGetInterruptState ();\r
- ArmDisableInterrupts ();\r
-\r
- ArmV7PerformPoUDataCacheOperation (DataCacheOperation);\r
-\r
- ArmDrainWriteBuffer ();\r
-\r
- if (SavedInterruptState) {\r
- ArmEnableInterrupts ();\r
- }\r
-}\r
-\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
ArmDrainWriteBuffer ();\r
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheToPoU (\r
- VOID\r
- )\r
-{\r
- ArmDrainWriteBuffer ();\r
- ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
-}\r
\r
typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);\r
\r
-\r
-VOID\r
-ArmV7PerformPoUDataCacheOperation (\r
- IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
- );\r
-\r
VOID\r
ArmV7AllDataCachesOperation (\r
IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
GCC_ASM_EXPORT (ArmSetLowVectors)\r
GCC_ASM_EXPORT (ArmSetHighVectors)\r
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
-GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
-ASM_PFX(ArmV7PerformPoUDataCacheOperation):\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 @ Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
- ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU)\r
- mov R3, R3, LSR #26 @ Cache level value (naturally aligned)\r
- beq Finished2\r
- mov R10, #0\r
-\r
-Loop4:\r
- add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
- mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 @ get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip2 @ no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb @ isb to sync the change to the CacheSizeID reg\r
- mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #0x7 @ extract the line length field\r
- add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
- clz R5, R4 @ R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
-\r
-Loop5:\r
- mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
-\r
-Loop6:\r
- orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 @ factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 @ decrement the way number\r
- bge Loop6\r
- subs R7, R7, #1 @ decrement the index\r
- bge Loop5\r
-Skip2:\r
- add R10, R10, #2 @ increment the cache number\r
- cmp R3, R10\r
- bgt Loop4\r
-\r
-Finished2:\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
ASM_PFX(ArmDataMemoryBarrier):\r
dmb\r
bx LR\r
EXPORT ArmSetLowVectors\r
EXPORT ArmSetHighVectors\r
EXPORT ArmV7AllDataCachesOperation\r
- EXPORT ArmV7PerformPoUDataCacheOperation\r
EXPORT ArmDataMemoryBarrier\r
EXPORT ArmDataSynchronizationBarrier\r
EXPORT ArmInstructionSynchronizationBarrier\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
-ArmV7PerformPoUDataCacheOperation\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 ; Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
- ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)\r
- mov R3, R3, LSR #26 ; Cache level value (naturally aligned)\r
- beq Finished2\r
- mov R10, #0\r
-\r
-Loop4\r
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 ; get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip2 ; no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb ; isb to sync the change to the CacheSizeID reg\r
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #&7 ; extract the line length field\r
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
- clz R5, R4 ; R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
-\r
-Loop5\r
- mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
-\r
-Loop6\r
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 ; factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 ; decrement the way number\r
- bge Loop6\r
- subs R7, R7, #1 ; decrement the index\r
- bge Loop5\r
-Skip2\r
- add R10, R10, #2 ; increment the cache number\r
- cmp R3, R10\r
- bgt Loop4\r
-\r
-Finished2\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
ArmDataMemoryBarrier\r
dmb\r
bx LR\r
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