]> git.proxmox.com Git - mirror_edk2.git/commitdiff
ArmPkg: Add isb when setting SCR
authorEvan Lloyd <evan.lloyd@arm.com>
Wed, 3 Feb 2016 17:07:47 +0000 (17:07 +0000)
committerLeif Lindholm <leif.lindholm@linaro.org>
Wed, 3 Feb 2016 18:42:21 +0000 (18:42 +0000)
Some updates to SCR can cause a problem which manifests as an undefined opcode exception.
This may be when a speculative secure instruction fetch happens after the NS bit is set.
An isb is required to make the register change take effect fully.

Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

index 28db98b417c32a815e4920914f489e1076fbcc60..50faef4ed0b9750aac29956e36bb532da7f2be28 100644 (file)
@@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr):
 \r
 ASM_PFX(ArmWriteScr):\r
   msr     scr_el3, x0            // Secure configuration register EL3\r
+  isb\r
   ret\r
 \r
 ASM_PFX(ArmWriteMVBar):\r
index 59f991885995dfc754ee6f2961eae962b0a6ee1b..085f08bfda8cc425f6e43f3ee7a49e191db8f914 100644 (file)
@@ -147,6 +147,7 @@ ASM_PFX(ArmReadScr):
 \r
 ASM_PFX(ArmWriteScr):\r
   mcr     p15, 0, r0, c1, c1, 0\r
+  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmReadHVBar):\r
index bdd862a96acb836065a3e78a92b4bdf364887dc1..228d7c8fc147e4e036dee9dabd7fc0f43b2a0fcc 100644 (file)
 \r
  RVCT_ASM_EXPORT ArmWriteScr\r
   mcr     p15, 0, r0, c1, c1, 0\r
+  isb\r
   bx      lr\r
 \r
  RVCT_ASM_EXPORT ArmReadHVBar\r