OvmfPkg/PlatformPei: provide 10 * 4KB of PCI IO Port space on Q35

This can accommodate 10 bridges (including root bridges, PCIe upstream and
downstream ports, etc -- see
<https://bugzilla.redhat.com/show_bug.cgi?id=1333238#c12> for more
details).

10 is not a whole lot, but closer to the architectural limit of 15 than
our current 4, so it can be considered a stop-gap solution until all
guests manage to migrate to virtio-1.0, and no longer need PCI IO BARs
behind PCIe downstream ports.

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index b03b577013beb39456e03aaed797a9d8d940e20f..75f7480ac726e4a8a3f71a26825dba7abc7adacc 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -244,6 +244,16 @@ MemMapInitialization (
         EfiReservedMemoryType);\r
     }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+    //\r
+    // On Q35, the IO Port space is available for PCI resource allocations from\r
+    // 0x6000 up.\r
+    //\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      PciIoBase = 0x6000;\r
+      PciIoSize = 0xA000;\r
+      ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
+    }\r
   }\r
 \r
   //\r