OvmfPkg/IndustryStandard: increase vertical whitespace in Q35 macro defs

In a subsequent patch, we'll introduce new DRAM controller macros in
"Q35MchIch9.h". Their names are too long for the currently available
vertical whitespace, so increase the latter first.

There is no functional change in this patch ("git show -b" displays
nothing).

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Message-Id: <20200129214412.2361-3-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 2ac16f19c62eca4a56473c1ccf6fdc5eef32da12..80379c223a1cf4a2af1bd8e32c0c42f408727033 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -27,56 +27,56 @@
 //\r
 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r
 //\r
 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r

-#define MCH_EXT_TSEG_MB       0x50\r
-#define MCH_EXT_TSEG_MB_QUERY   0xFFFF\r
-\r
-#define MCH_GGC               0x52\r
-#define MCH_GGC_IVD             BIT1\r
-\r
-#define MCH_PCIEXBAR_LOW      0x60\r
-#define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF\r
-#define MCH_PCIEXBAR_BUS_FF     0\r
-#define MCH_PCIEXBAR_EN         BIT0\r
-\r
-#define MCH_PCIEXBAR_HIGH     0x64\r
-#define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
-\r
-#define MCH_PAM0              0x90\r
-#define MCH_PAM1              0x91\r
-#define MCH_PAM2              0x92\r
-#define MCH_PAM3              0x93\r
-#define MCH_PAM4              0x94\r
-#define MCH_PAM5              0x95\r
-#define MCH_PAM6              0x96\r
-\r
-#define MCH_SMRAM             0x9D\r
-#define MCH_SMRAM_D_LCK         BIT4\r
-#define MCH_SMRAM_G_SMRAME      BIT3\r
-\r
-#define MCH_ESMRAMC           0x9E\r
-#define MCH_ESMRAMC_H_SMRAME    BIT7\r
-#define MCH_ESMRAMC_E_SMERR     BIT6\r
-#define MCH_ESMRAMC_SM_CACHE    BIT5\r
-#define MCH_ESMRAMC_SM_L1       BIT4\r
-#define MCH_ESMRAMC_SM_L2       BIT3\r
-#define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)\r
-#define MCH_ESMRAMC_TSEG_8MB    BIT2\r
-#define MCH_ESMRAMC_TSEG_2MB    BIT1\r
-#define MCH_ESMRAMC_TSEG_1MB    0\r
-#define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)\r
-#define MCH_ESMRAMC_T_EN        BIT0\r
-\r
-#define MCH_GBSM              0xA4\r
-#define MCH_GBSM_MB_SHIFT       20\r
-\r
-#define MCH_BGSM              0xA8\r
-#define MCH_BGSM_MB_SHIFT       20\r
-\r
-#define MCH_TSEGMB            0xAC\r
-#define MCH_TSEGMB_MB_SHIFT     20\r
-\r
-#define MCH_TOLUD             0xB0\r
-#define MCH_TOLUD_MB_SHIFT      4\r
+#define MCH_EXT_TSEG_MB           0x50\r
+#define MCH_EXT_TSEG_MB_QUERY       0xFFFF\r
+\r
+#define MCH_GGC                   0x52\r
+#define MCH_GGC_IVD                 BIT1\r
+\r
+#define MCH_PCIEXBAR_LOW          0x60\r
+#define MCH_PCIEXBAR_LOWMASK        0x0FFFFFFF\r
+#define MCH_PCIEXBAR_BUS_FF         0\r
+#define MCH_PCIEXBAR_EN             BIT0\r
+\r
+#define MCH_PCIEXBAR_HIGH         0x64\r
+#define MCH_PCIEXBAR_HIGHMASK       0xFFFFFFF0\r
+\r
+#define MCH_PAM0                  0x90\r
+#define MCH_PAM1                  0x91\r
+#define MCH_PAM2                  0x92\r
+#define MCH_PAM3                  0x93\r
+#define MCH_PAM4                  0x94\r
+#define MCH_PAM5                  0x95\r
+#define MCH_PAM6                  0x96\r
+\r
+#define MCH_SMRAM                 0x9D\r
+#define MCH_SMRAM_D_LCK             BIT4\r
+#define MCH_SMRAM_G_SMRAME          BIT3\r
+\r
+#define MCH_ESMRAMC               0x9E\r
+#define MCH_ESMRAMC_H_SMRAME        BIT7\r
+#define MCH_ESMRAMC_E_SMERR         BIT6\r
+#define MCH_ESMRAMC_SM_CACHE        BIT5\r
+#define MCH_ESMRAMC_SM_L1           BIT4\r
+#define MCH_ESMRAMC_SM_L2           BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT        (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_TSEG_8MB        BIT2\r
+#define MCH_ESMRAMC_TSEG_2MB        BIT1\r
+#define MCH_ESMRAMC_TSEG_1MB        0\r
+#define MCH_ESMRAMC_TSEG_MASK       (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_T_EN            BIT0\r
+\r
+#define MCH_GBSM                  0xA4\r
+#define MCH_GBSM_MB_SHIFT           20\r
+\r
+#define MCH_BGSM                  0xA8\r
+#define MCH_BGSM_MB_SHIFT           20\r
+\r
+#define MCH_TSEGMB                0xAC\r
+#define MCH_TSEGMB_MB_SHIFT         20\r
+\r
+#define MCH_TOLUD                 0xB0\r
+#define MCH_TOLUD_MB_SHIFT          4\r

 \r
 //\r
 // B/D/F/Type: 0/0x1f/0/PCI\r
 \r
 //\r
 // B/D/F/Type: 0/0x1f/0/PCI\r