UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD

AMD does not support MSR_IA32_MISC_ENABLE.  Accessing that register
causes and exception on AMD processors.  If Execution Disable is
supported, but if the processor is an AMD processor, skip manipulating
MSR_IA32_MISC_ENABLE[34] XD Disable bit.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Message-Id: <20200622131825.1352-5-Garrett.Kirkendall@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index f96de9bdeb433026cb5bc77c2090c26481dd7224..167f5e14dbd4c822e7b330aff77c49d694bb1523 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,6 @@
 ;------------------------------------------------------------------------------ ;\r
 ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack)
 global ASM_PFX(gPatchSmbase)\r
 extern ASM_PFX(mXdSupported)\r
 global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
 extern ASM_PFX(gSmiHandlerIdtr)\r
 \r
 extern ASM_PFX(mCetSupported)\r
@@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3):
 ASM_PFX(gPatchXdSupported):\r
     cmp     al, 0\r
     jz      @SkipXd\r
+\r
+; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
+    mov     al, strict byte 1           ; source operand may be patched\r
+ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
+    cmp     al, 1\r
+    jz      MsrIa32MiscEnableSupported\r
+\r
+; MSR_IA32_MISC_ENABLE not supported\r
+    xor     edx, edx\r
+    push    edx                         ; don't try to restore the XD Disable bit just before RSM\r
+    jmp     EnableNxe\r
+\r
 ;\r
 ; Check XD disable bit\r
 ;\r
+MsrIa32MiscEnableSupported:\r
     mov     ecx, MSR_IA32_MISC_ENABLE\r
     rdmsr\r
     push    edx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
-    jz      .5\r
+    jz      EnableNxe\r
     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set\r
     wrmsr\r
-.5:\r
+EnableNxe:\r
     mov     ecx, MSR_EFER\r
     rdmsr\r
     or      ax, MSR_EFER_XD             ; enable NXE\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index c47b5573e366bf5e8b4f56e9496d0e739d605e41..d7ed9ab7a770df24ce1e868dc2236e32db906b37 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -2,7 +2,7 @@
 Enable SMM profile.\r
 \r
 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>\r
 \r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -1015,6 +1015,13 @@ CheckFeatureSupported (
       mXdSupported = FALSE;\r
       PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);\r
     }\r
+\r
+    if (StandardSignatureIsAuthenticAMD ()) {\r
+      //\r
+      // AMD processors do not support MSR_IA32_MISC_ENABLE\r
+      //\r
+      PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1);\r
+    }\r
   }\r
 \r
   if (mBtsSupported) {\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
index 43f6935cf9dc448588f5a6e39a604969e9facec5..993360a8a8c150739fe21b06ea4940045936639d 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
@@ -2,6 +2,7 @@
 SMM profile internal header file.\r
 \r
 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/UefiRuntimeServicesTableLib.h>\r
 #include <Library/DxeServicesTableLib.h>\r
 #include <Library/CpuLib.h>\r
+#include <Library/UefiCpuLib.h>\r
 #include <IndustryStandard/Acpi.h>\r
 \r
 #include "SmmProfileArch.h"\r
@@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;
 extern UINTN                     gSmiExceptionHandlers[];\r
 extern BOOLEAN                   mXdSupported;\r
 X86_ASSEMBLY_PATCH_LABEL         gPatchXdSupported;\r
+X86_ASSEMBLY_PATCH_LABEL         gPatchMsrIa32MiscEnableSupported;\r
 extern UINTN                     *mPFEntryCount;\r
 extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
 extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 8bfba55b5d082dcb9b51f257c832f2aff425f345..0e154e5db9490640a809808bb2506065f7e4d1be 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,6 @@
 ;------------------------------------------------------------------------------ ;\r
 ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 global ASM_PFX(gPatchSmbase)\r
 extern ASM_PFX(mXdSupported)\r
 global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
 global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmiCr3)\r
 global ASM_PFX(gPatch5LevelPagingNeeded)\r
@@ -152,18 +154,32 @@ SkipEnable5LevelPaging:
 ASM_PFX(gPatchXdSupported):\r
     cmp     al, 0\r
     jz      @SkipXd\r
+\r
+; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
+    mov     al, strict byte 1           ; source operand may be patched\r
+ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
+    cmp     al, 1\r
+    jz      MsrIa32MiscEnableSupported\r
+\r
+; MSR_IA32_MISC_ENABLE not supported\r
+    sub     esp, 4\r
+    xor     rdx, rdx\r
+    push    rdx                         ; don't try to restore the XD Disable bit just before RSM\r
+    jmp     EnableNxe\r
+\r
 ;\r
 ; Check XD disable bit\r
 ;\r
+MsrIa32MiscEnableSupported:\r
     mov     ecx, MSR_IA32_MISC_ENABLE\r
     rdmsr\r
     sub     esp, 4\r
     push    rdx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
-    jz      .0\r
+    jz      EnableNxe\r
     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set\r
     wrmsr\r
-.0:\r
+EnableNxe:\r
     mov     ecx, MSR_EFER\r
     rdmsr\r
     or      ax, MSR_EFER_XD            ; enable NXE\r