Feature PCDs cannot be used in assembly files.
The PcdStandalone PCD is needed in one of the assembly file of the
ArmPlatformPkg/PrePi module.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11952
6f19259b-4bc3-4df7-8a09-
765794883524
15 files changed:
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
[PcdsFeatureFlag.common]
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
[PcdsFeatureFlag.common]
- gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE|BOOLEAN|0x00000001
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
[PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
[PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
+ gArmPlatformTokenSpaceGuid.PcdStandalone|0|UINT32|0x00000001
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
# Stack for CPU Cores in Secure Mode
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
# Stack for CPU Cores in Secure Mode
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE\r
\r
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE\r
\r
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
- \r
- gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE\r
\r
!if $(EDK2_SKIP_PEICORE) == 1\r
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE\r
\r
!if $(EDK2_SKIP_PEICORE) == 1\r
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE\r
#\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000\r
\r
#\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000\r
\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone|1\r
+ \r
# Stack for CPU Cores in Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World\r
# Stack for CPU Cores in Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
-
- gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
!if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
!if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
#
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
#
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
+ gArmPlatformTokenSpaceGuid.PcdStandalone|1
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
# Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
# Stacks for MPCores in Secure World
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdStandalone
+ gArmPlatformTokenSpaceGuid.PcdStandalone
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
-!if $(EDK2_ARMVE_STANDALONE) == 1
- gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
-!endif
-
!if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
!endif
!if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
!endif
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
+!if $(EDK2_ARMVE_STANDALONE) == 1
+ gArmPlatformTokenSpaceGuid.PcdStandalone|1
+!endif
+
# Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores
# Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdStandalone
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+
gArmTokenSpaceGuid.PcdL2x0ControllerBase
gArmTokenSpaceGuid.PcdL2x0ControllerBase
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
\r
[FixedPcd]\r
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
\r
[FixedPcd]\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
//\r
// Initialize the System Memory (DRAM)\r
//\r
//\r
// Initialize the System Memory (DRAM)\r
//\r
- if (FeaturePcdGet(PcdStandalone)) {\r
+ if (PcdGet32 (PcdStandalone)) {\r
// In case of a standalone version, the DRAM is already initialized\r
ArmPlatformInitializeSystemMemory();\r
}\r
// In case of a standalone version, the DRAM is already initialized\r
ArmPlatformInitializeSystemMemory();\r
}\r
//\r
// Declare the UEFI memory to PEI\r
//\r
//\r
// Declare the UEFI memory to PEI\r
//\r
- if (FeaturePcdGet(PcdStandalone)) {\r
+ if (PcdGet32 (PcdStandalone)) {\r
// In case of standalone UEFI, we set the UEFI memory region at the top of the DRAM\r
UefiMemoryBase = SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize);\r
} else {\r
// In case of standalone UEFI, we set the UEFI memory region at the top of the DRAM\r
UefiMemoryBase = SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize);\r
} else {\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFdSize\r
\r
gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFdSize\r
\r
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
- if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+ if (!PcdGet32(PcdStandalone)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
}\r
// Sending SGI to all the Secondary CPU interfaces\r
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
}\r
[Ppis]\r
gEfiTemporaryRamSupportPpiGuid\r
\r
[Ppis]\r
gEfiTemporaryRamSupportPpiGuid\r
\r
-[FeaturePcd]\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
- \r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
[Ppis]\r
gEfiTemporaryRamSupportPpiGuid\r
\r
[Ppis]\r
gEfiTemporaryRamSupportPpiGuid\r
\r
-[FeaturePcd]\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
- \r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
- if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
+ if (FeaturePcdGet(PcdSkipPeiCore) || !PcdGet32(PcdStandalone)) {
// Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory ();
}
// Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory ();
}
}
// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
}
// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
- if (FeaturePcdGet(PcdStandalone) == FALSE) {
+ if (!PcdGet32(PcdStandalone)) {
if (CoreId == ARM_PRIMARY_CORE) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
if (CoreId == ARM_PRIMARY_CORE) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
SerialPortLib
[FeaturePcd]
SerialPortLib
[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdSkipPeiCore
[FixedPcd]
gArmTokenSpaceGuid.PcdSkipPeiCore
[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport