+/** @file\r
+SMRAM Save State Map Definitions.\r
+\r
+SMRAM Save State Map definitions based on contents of the \r
+Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ Volume 3C, Section 34.4 SMRAM\r
+ Volume 3C, Section 34.5 SMI Handler Execution Environment\r
+ Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
+\r
+and the AMD64 Architecture Programmer's Manual\r
+ Volume 2, Section 10.2 SMM Resources\r
+\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2015, Red Hat, Inc.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
+#define __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
+\r
+#pragma pack (1)\r
+\r
+///\r
+/// 32-bit SMRAM Save State Map\r
+///\r
+typedef struct {\r
+ UINT8 Reserved0[0x200]; // 7c00h\r
+ UINT8 Reserved1[0xf8]; // 7e00h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved2[0x9C]; // 7f08h\r
+ UINT32 IOMemAddr; // 7fa0h\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS; // 7fach\r
+ UINT32 _SS; // 7fb0h\r
+ UINT32 _DS; // 7fb4h\r
+ UINT32 _FS; // 7fb8h\r
+ UINT32 _GS; // 7fbch\r
+ UINT32 Reserved3; // 7fc0h\r
+ UINT32 _TR; // 7fc4h\r
+ UINT32 _DR7; // 7fc8h\r
+ UINT32 _DR6; // 7fcch\r
+ UINT32 _EAX; // 7fd0h\r
+ UINT32 _ECX; // 7fd4h\r
+ UINT32 _EDX; // 7fd8h\r
+ UINT32 _EBX; // 7fdch\r
+ UINT32 _ESP; // 7fe0h\r
+ UINT32 _EBP; // 7fe4h\r
+ UINT32 _ESI; // 7fe8h\r
+ UINT32 _EDI; // 7fech\r
+ UINT32 _EIP; // 7ff0h\r
+ UINT32 _EFLAGS; // 7ff4h\r
+ UINT32 _CR3; // 7ff8h\r
+ UINT32 _CR0; // 7ffch\r
+} QEMU_SMRAM_SAVE_STATE_MAP32;\r
+\r
+///\r
+/// 64-bit SMRAM Save State Map\r
+///\r
+typedef struct {\r
+ UINT8 Reserved0[0x200]; // 7c00h\r
+\r
+ UINT16 _ES; // 7e00h\r
+ UINT16 _ESAccessRights; // 7e02h\r
+ UINT32 _ESLimit; // 7e04h\r
+ UINT64 _ESBase; // 7e08h\r
+\r
+ UINT16 _CS; // 7e10h\r
+ UINT16 _CSAccessRights; // 7e12h\r
+ UINT32 _CSLimit; // 7e14h\r
+ UINT64 _CSBase; // 7e18h\r
+\r
+ UINT16 _SS; // 7e20h\r
+ UINT16 _SSAccessRights; // 7e22h\r
+ UINT32 _SSLimit; // 7e24h\r
+ UINT64 _SSBase; // 7e28h\r
+\r
+ UINT16 _DS; // 7e30h\r
+ UINT16 _DSAccessRights; // 7e32h\r
+ UINT32 _DSLimit; // 7e34h\r
+ UINT64 _DSBase; // 7e38h\r
+\r
+ UINT16 _FS; // 7e40h\r
+ UINT16 _FSAccessRights; // 7e42h\r
+ UINT32 _FSLimit; // 7e44h\r
+ UINT64 _FSBase; // 7e48h\r
+\r
+ UINT16 _GS; // 7e50h\r
+ UINT16 _GSAccessRights; // 7e52h\r
+ UINT32 _GSLimit; // 7e54h\r
+ UINT64 _GSBase; // 7e58h\r
+\r
+ UINT32 _GDTRReserved1; // 7e60h\r
+ UINT16 _GDTRLimit; // 7e64h\r
+ UINT16 _GDTRReserved2; // 7e66h\r
+ UINT64 _GDTRBase; // 7e68h\r
+\r
+ UINT16 _LDTR; // 7e70h\r
+ UINT16 _LDTRAccessRights; // 7e72h\r
+ UINT32 _LDTRLimit; // 7e74h\r
+ UINT64 _LDTRBase; // 7e78h\r
+\r
+ UINT32 _IDTRReserved1; // 7e80h\r
+ UINT16 _IDTRLimit; // 7e84h\r
+ UINT16 _IDTRReserved2; // 7e86h\r
+ UINT64 _IDTRBase; // 7e88h\r
+\r
+ UINT16 _TR; // 7e90h\r
+ UINT16 _TRAccessRights; // 7e92h\r
+ UINT32 _TRLimit; // 7e94h\r
+ UINT64 _TRBase; // 7e98h\r
+\r
+ UINT64 IO_RIP; // 7ea0h\r
+ UINT64 IO_RCX; // 7ea8h\r
+ UINT64 IO_RSI; // 7eb0h\r
+ UINT64 IO_RDI; // 7eb8h\r
+ UINT32 IO_DWord; // 7ec0h\r
+ UINT8 Reserved1[0x04]; // 7ec4h\r
+ UINT8 IORestart; // 7ec8h\r
+ UINT8 AutoHALTRestart; // 7ec9h\r
+ UINT8 Reserved2[0x06]; // 7ecah\r
+\r
+ UINT64 IA32_EFER; // 7ed0h\r
+ UINT64 SVM_Guest; // 7ed8h\r
+ UINT64 SVM_GuestVMCB; // 7ee0h\r
+ UINT64 SVM_GuestVIntr; // 7ee8h\r
+ UINT8 Reserved3[0x0c]; // 7ef0h\r
+\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT32 SMBASE; // 7f00h\r
+\r
+ UINT8 Reserved4[0x1c]; // 7f04h\r
+ UINT64 SVM_GuestPAT; // 7f20h\r
+ UINT64 SVM_HostIA32_EFER; // 7f28h\r
+ UINT64 SVM_HostCR4; // 7f30h\r
+ UINT64 SVM_HostCR3; // 7f38h\r
+ UINT64 SVM_HostCR0; // 7f40h\r
+\r
+ UINT64 _CR4; // 7f48h\r
+ UINT64 _CR3; // 7f50h\r
+ UINT64 _CR0; // 7f58h\r
+ UINT64 _DR7; // 7f60h\r
+ UINT64 _DR6; // 7f68h\r
+ UINT64 _RFLAGS; // 7f70h\r
+ UINT64 _RIP; // 7f78h\r
+ UINT64 _R15; // 7f80h\r
+ UINT64 _R14; // 7f88h\r
+ UINT64 _R13; // 7f90h\r
+ UINT64 _R12; // 7f98h\r
+ UINT64 _R11; // 7fa0h\r
+ UINT64 _R10; // 7fa8h\r
+ UINT64 _R9; // 7fb0h\r
+ UINT64 _R8; // 7fb8h\r
+ UINT64 _RDI; // 7fc0h\r
+ UINT64 _RSI; // 7fc8h\r
+ UINT64 _RBP; // 7fd0h\r
+ UINT64 _RSP; // 7fd8h\r
+ UINT64 _RBX; // 7fe0h\r
+ UINT64 _RDX; // 7fe8h\r
+ UINT64 _RCX; // 7ff0h\r
+ UINT64 _RAX; // 7ff8h\r
+} QEMU_SMRAM_SAVE_STATE_MAP64;\r
+\r
+///\r
+/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
+///\r
+typedef union {\r
+ QEMU_SMRAM_SAVE_STATE_MAP32 x86;\r
+ QEMU_SMRAM_SAVE_STATE_MAP64 x64;\r
+} QEMU_SMRAM_SAVE_STATE_MAP;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
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