+/** @file\r
+ RISC-V Processor supervisor mode trap handler\r
+\r
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include "CpuExceptionHandlerLib.h"\r
+\r
+ .align 3\r
+ .section .entry, "ax", %progbits\r
+ .globl SupervisorModeTrap\r
+SupervisorModeTrap:\r
+ addi sp, sp, -SMODE_TRAP_REGS_SIZE\r
+\r
+ /* Save all general regisers except SP */\r
+ sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)\r
+\r
+ csrr t0, CSR_SSTATUS\r
+ and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)\r
+ sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)\r
+ csrr t0, CSR_SEPC\r
+ sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)\r
+ csrr t0, CSR_SIE\r
+ sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)\r
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)\r
+\r
+ sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)\r
+ sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)\r
+ sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)\r
+ sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)\r
+ sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)\r
+ sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)\r
+ sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)\r
+ sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)\r
+ sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)\r
+ sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)\r
+ sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)\r
+ sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)\r
+ sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)\r
+ sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)\r
+ sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)\r
+ sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)\r
+ sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)\r
+ sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)\r
+ sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)\r
+ sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)\r
+ sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)\r
+ sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)\r
+ sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)\r
+ sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)\r
+ sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)\r
+ sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)\r
+ sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)\r
+ sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)\r
+ sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)\r
+\r
+ /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */\r
+ call RiscVSupervisorModeTrapHandler\r
+\r
+ /* Restore all general regisers except SP */\r
+ ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)\r
+ ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)\r
+ ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)\r
+ ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)\r
+ ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)\r
+ ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)\r
+ ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)\r
+ ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)\r
+ ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)\r
+ ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)\r
+ ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)\r
+ ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)\r
+ ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)\r
+ ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)\r
+ ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)\r
+ ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)\r
+ ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)\r
+ ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)\r
+ ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)\r
+ ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)\r
+ ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)\r
+ ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)\r
+ ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)\r
+ ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)\r
+ ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)\r
+ ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)\r
+ ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)\r
+ ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)\r
+\r
+ ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)\r
+ csrw CSR_SEPC, t0\r
+ ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)\r
+ csrw CSR_SIE, t0\r
+ csrr t0, CSR_SSTATUS\r
+ ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)\r
+ or t0, t0, t1\r
+ csrw CSR_SSTATUS, t0\r
+ ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)\r
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)\r
+ addi sp, sp, SMODE_TRAP_REGS_SIZE\r
+ sret\r