The PMBA_RTE and ACPI_TIMER_OFFSET macros apply equally to both boards,
plus they are triplicated between the various AcpiTimerLib instances.
Define them centrally in "OvmfPlatforms.h".
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17436
6f19259b-4bc3-4df7-8a09-
765794883524
#define OVMF_HOSTBRIDGE_DID \\r
PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)\r
\r
+//\r
+// Common bits in same-purpose registers\r
+//\r
+#define PMBA_RTE BIT0\r
+\r
+//\r
+// Common IO ports relative to the Power Management Base Address\r
+//\r
+#define ACPI_TIMER_OFFSET 0x8\r
+\r
#endif\r
#include <Library/PcdLib.h>\r
#include <OvmfPlatforms.h>\r
\r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE BIT0\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET 0x8\r
-\r
//\r
// Cached ACPI Timer IO Address\r
//\r
#include <Library/PcdLib.h>\r
#include <OvmfPlatforms.h>\r
\r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE BIT0\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET 0x8\r
-\r
/**\r
The constructor function enables ACPI IO space.\r
\r
#include <Library/PciLib.h>\r
#include <OvmfPlatforms.h>\r
\r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE BIT0\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET 0x8\r
-\r
//\r
// Cached ACPI Timer IO Address\r
//\r