Check in definition of PCI CFG2 PPI into OldMdePkg.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2686 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OldMdePkg/Include/Peim/PeiCis.h b/OldMdePkg/Include/Peim/PeiCis.h
index 5bf71eb6b9735345fd4e9e128fad70a82581f51a..67db3875ef876b96e0b72af4ef0667bf59517f1e 100644 (file)
--- a/OldMdePkg/Include/Peim/PeiCis.h
+++ b/OldMdePkg/Include/Peim/PeiCis.h
@@ -51,6 +51,7 @@ typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;
 \r
 \r
 #include <Ppi/CpuIo.h>\r
 \r
 \r
 #include <Ppi/CpuIo.h>\r

+#include <Ppi/PciCfg2.h>\r

 #include <Ppi/PciCfg.h>\r
 \r
 //\r
 #include <Ppi/PciCfg.h>\r
 \r
 //\r

diff --git a/OldMdePkg/Include/Ppi/PciCfg.h b/OldMdePkg/Include/Ppi/PciCfg.h
index 987f54ed43239e1a265818c3de3d6c3c06cdf622..31a8b53fec0e2c03c671516d7a4581c1f200b771 100644 (file)
--- a/OldMdePkg/Include/Ppi/PciCfg.h
+++ b/OldMdePkg/Include/Ppi/PciCfg.h
@@ -32,22 +32,6 @@ typedef struct _EFI_PEI_PCI_CFG_PPI   EFI_PEI_PCI_CFG_PPI;
       (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \\r
     ) & 0x00000000ffffffff\r
 \r
       (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \\r
     ) & 0x00000000ffffffff\r
 \r

-typedef enum {\r
-  EfiPeiPciCfgWidthUint8   = 0,\r
-  EfiPeiPciCfgWidthUint16  = 1,\r
-  EfiPeiPciCfgWidthUint32  = 2,\r
-  EfiPeiPciCfgWidthUint64  = 3,\r
-  EfiPeiPciCfgWidthMaximum\r
-} EFI_PEI_PCI_CFG_PPI_WIDTH;\r
-\r
-typedef struct {\r
-  UINT8 Register;\r
-  UINT8 Function;\r
-  UINT8 Device;\r
-  UINT8 Bus;\r
-  UINT8 Reserved[4];\r
-} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
-\r

 /**\r
   PCI read and write operation.\r
 \r
 /**\r
   PCI read and write operation.\r
 \r

diff --git a/OldMdePkg/Include/Ppi/PciCfg2.h b/OldMdePkg/Include/Ppi/PciCfg2.h
new file mode 100644 (file)
index 0000000..761436f
--- /dev/null
+++ b/OldMdePkg/Include/Ppi/PciCfg2.h
@@ -0,0 +1,158 @@
+/** @file\r
+  This file declares PciCfg PPI used to access PCI configuration space in PEI\r
+\r
+  Copyright (c) 2006 - 2007, Intel Corporation                                                         \r
+  All rights reserved. This program and the accompanying materials                          \r
+  are licensed and made available under the terms and conditions of the BSD License         \r
+  which accompanies this distribution.  The full text of the license may be found at        \r
+  http://opensource.org/licenses/bsd-license.php                                            \r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+\r
+  Module Name:  PciCfg.h\r
+\r
+  @par Revision Reference:\r
+  This PPI is defined in PI\r
+  Version 1.00.\r
+\r
+**/\r
+\r
+#ifndef __PEI_PCI_CFG2_H__\r
+#define __PEI_PCI_CFG2_H__\r
+\r
+\r
+#define EFI_PEI_PCI_CFG2_PPI_GUID \\r
+  { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r
+\r
+\r
+typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;\r
+\r
+#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
+  (((bus) << 24) | \\r
+  ((dev) << 16) | \\r
+  ((func) << 8) | \\r
+  ((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));\r
+\r
+//\r
+// EFI_PEI_PCI_CFG_PPI_WIDTH\r
+//\r
+typedef enum {\r
+  EfiPeiPciCfgWidthUint8  = 0,\r
+  EfiPeiPciCfgWidthUint16 = 1,\r
+  EfiPeiPciCfgWidthUint32 = 2,\r
+  EfiPeiPciCfgWidthUint64 = 3,\r
+  EfiPeiPciCfgWidthMaximum\r
+} EFI_PEI_PCI_CFG_PPI_WIDTH;\r
+\r
+//\r
+// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r
+//\r
+typedef struct {\r
+  UINT8   Register;\r
+  UINT8   Function;\r
+  UINT8   Device;\r
+  UINT8   Bus;\r
+  UINT32  ExtendedRegister;\r
+} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
+\r
+/**\r
+  Reads from or write to a given location in the PCI configuration space.\r
+\r
+  @param  PeiServices     An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+  @param  This            Pointer to local data for the interface.\r
+\r
+  @param  Width           The width of the access. Enumerated in bytes. \r
+                          See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+  @param  Address         The physical address of the access. The format of \r
+                          the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+  @param  Buffer          A pointer to the buffer of data..\r
+\r
+\r
+  @retval EFI_SUCCESS           The function completed successfully.\r
+\r
+  @retval EFI_DEVICE_ERROR      There was a problem with the transaction.\r
+\r
+  @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting the operation at this\r
+                                time.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO) (\r
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,\r
+  IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,\r
+  IN CONST  EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+  IN CONST  UINT64                    Address,\r
+  IN OUT    VOID                      *Buffer\r
+);\r
+\r
+\r
+/**\r
+  PCI read-modify-write operation.\r
+\r
+  @param  PeiServices     An indirect pointer to the PEI Services Table \r
+                          published by the PEI Foundation.\r
+\r
+  @param  This            Pointer to local data for the interface.\r
+\r
+  @param  Width           The width of the access. Enumerated in bytes. Type\r
+                          EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+  @param  Address         The physical address of the access.\r
+\r
+  @param  SetBits         Points to value to bitwise-OR with the read configuration value. \r
+\r
+                          The size of the value is determined by Width.\r
+\r
+  @param  ClearBits       Points to the value to negate and bitwise-AND with the read configuration value. \r
+                          The size of the value is determined by Width.\r
+\r
+\r
+  @retval EFI_SUCCESS           The function completed successfully.\r
+\r
+  @retval EFI_DEVICE_ERROR      There was a problem with the transaction.\r
+\r
+  @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting \r
+                                the operation at this time.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW) (\r
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,\r
+  IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,\r
+  IN CONST  EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+  IN CONST  UINT64                    Address,\r
+  IN CONST  VOID                      *SetBits,\r
+  IN CONST  VOID                      *ClearBits\r
+);\r
+\r
+/**\r
+  @par Ppi Description:\r
+  The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r
+  controllers behind a PCI root bridge controller.\r
+\r
+  @param Read     PCI read services.  See the Read() function description.\r
+\r
+  @param Write    PCI write services.  See the Write() function description.\r
+\r
+  @param Modify   PCI read-modify-write services.  See the Modify() function description.\r
+\r
+  @param Segment  The PCI bus segment which the specified functions will access.\r
+\r
+**/\r
+struct _EFI_PEI_PCI_CFG2_PPI {\r
+  EFI_PEI_PCI_CFG2_PPI_IO  Read;\r
+  EFI_PEI_PCI_CFG2_PPI_IO  Write;\r
+  EFI_PEI_PCI_CFG2_PPI_RW  Modify;\r
+  UINT16                  Segment;\r
+};\r
+\r
+\r
+extern EFI_GUID gEfiPciCfg2PpiGuid;\r
+\r
+#endif\r