UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMM

If XD is supported, then SMM enables it.  The non-SMM execution
environment can choose to enable or disable XD, so the state of
XD must be detected in each SMI and be enabled/restored.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 79b7c90a809be8eb72e54c269a640e0397fda154..185cb3d5935fe92ebf79a785487c392e080a0d69 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1,7 +1,7 @@
 /** @file\r
 SMM MP service implementation\r
 \r
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -1019,6 +1019,7 @@ SmiRendezvous (
   BOOLEAN           BspInProgress;\r
   UINTN             Index;\r
   UINTN             Cr2;\r
+  BOOLEAN           XdDisableFlag;\r
 \r
   //\r
   // Save Cr2 because Page Fault exception in SMM may override its value\r
@@ -1078,9 +1079,14 @@ SmiRendezvous (
     }\r
 \r
     //\r
-    // Try to enable NX\r
+    // Try to enable XD\r
     //\r
+    XdDisableFlag = FALSE;\r
     if (mXdSupported) {\r
+      if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {\r
+        XdDisableFlag = TRUE;\r
+        AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);\r
+      }\r
       ActivateXd ();\r
     }\r
 \r
@@ -1152,7 +1158,6 @@ SmiRendezvous (
         // BSP Handler is always called with a ValidSmi == TRUE\r
         //\r
         BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);\r
-\r
       } else {\r
         APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);\r
       }\r
@@ -1165,6 +1170,13 @@ SmiRendezvous (
     //\r
     while (mSmmMpSyncData->AllCpusInSync) {\r
       CpuPause ();\r
+     }\r
+\r
+    //\r
+    // Restore XD\r
+    //\r
+    if (XdDisableFlag) {\r
+      AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);\r
     }\r
   }\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
index c6ce1f59adda6e84122044198e5db80fbf18c572..5488c148e8bc7502cd484ead4c4c8b9b1a375bcb 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
@@ -21,6 +21,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /// MSR Register Index\r
 ///\r
 #define MSR_IA32_MISC_ENABLE                  0x1A0\r
+#define   B_XD_DISABLE_BIT                    BIT34\r
 \r
 //\r
 // External functions\r