ArmPkg/Library: AArch64 MMU EL1 support

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 2fdfee163ae1293ba753feb2e29dada1af3e4a38..ae22e86fa97a4634f4a6d1176d128c7e1bb136bb 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -536,8 +536,10 @@ ArmConfigureMmu (
   //\r
   // Set TCR that allows us to retrieve T0SZ in the subsequent functions\r
   //\r
   //\r
   // Set TCR that allows us to retrieve T0SZ in the subsequent functions\r
   //\r

-  if ((ArmReadCurrentEL () == AARCH64_EL2) || (ArmReadCurrentEL () == AARCH64_EL3)) {\r
-    //Note: Bits 23 and 31 are reserved bits in TCR_EL2 and TCR_EL3\r
+  // Ideally we will be running at EL2, but should support EL1 as well.\r
+  // UEFI should not run at EL3.\r
+  if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+    //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r

     TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r
 \r
     // Set the Physical Address Size using MaxAddress\r
     TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r
 \r
     // Set the Physical Address Size using MaxAddress\r


@@ -554,12 +556,33 @@ ArmConfigureMmu (
     } else if (MaxAddress < SIZE_256TB) {\r
       TCR |= TCR_PS_256TB;\r
     } else {\r
     } else if (MaxAddress < SIZE_256TB) {\r
       TCR |= TCR_PS_256TB;\r
     } else {\r

-      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU support.\n", MaxAddress));\r
+      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
+      ASSERT (0); // Bigger than 48-bit memory space are not supported\r
+      return RETURN_UNSUPPORTED;\r
+    }\r
+  } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
+    TCR = T0SZ | TCR_TG0_4KB;\r
+\r
+    // Set the Physical Address Size using MaxAddress\r
+    if (MaxAddress < SIZE_4GB) {\r
+      TCR |= TCR_IPS_4GB;\r
+    } else if (MaxAddress < SIZE_64GB) {\r
+      TCR |= TCR_IPS_64GB;\r
+    } else if (MaxAddress < SIZE_1TB) {\r
+      TCR |= TCR_IPS_1TB;\r
+    } else if (MaxAddress < SIZE_4TB) {\r
+      TCR |= TCR_IPS_4TB;\r
+    } else if (MaxAddress < SIZE_16TB) {\r
+      TCR |= TCR_IPS_16TB;\r
+    } else if (MaxAddress < SIZE_256TB) {\r
+      TCR |= TCR_IPS_256TB;\r
+    } else {\r
+      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r

       ASSERT (0); // Bigger than 48-bit memory space are not supported\r
       return RETURN_UNSUPPORTED;\r
     }\r
   } else {\r
       ASSERT (0); // Bigger than 48-bit memory space are not supported\r
       return RETURN_UNSUPPORTED;\r
     }\r
   } else {\r

-    ASSERT (0); // Bigger than 48-bit memory space are not supported\r
+    ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r

     return RETURN_UNSUPPORTED;\r
   }\r
 \r
     return RETURN_UNSUPPORTED;\r
   }\r
 \r