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Commit | Line | Data |
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327d8e4e AJ |
1 | /* |
2 | * OpenPOWER Palmetto BMC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 | 14 | #include "cpu.h" |
327d8e4e | 15 | #include "exec/address-spaces.h" |
12ec8bd5 | 16 | #include "hw/arm/boot.h" |
fca9ca1b | 17 | #include "hw/arm/aspeed.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
327d8e4e | 19 | #include "hw/boards.h" |
93198b6c | 20 | #include "hw/i2c/smbus_eeprom.h" |
044475f3 PMD |
21 | #include "hw/misc/pca9552.h" |
22 | #include "hw/misc/tmp105.h" | |
a27bd6c7 | 23 | #include "hw/qdev-properties.h" |
03dd024f | 24 | #include "qemu/log.h" |
e1ad9bc4 | 25 | #include "sysemu/block-backend.h" |
ece09bee | 26 | #include "sysemu/sysemu.h" |
d769a1da CLG |
27 | #include "hw/loader.h" |
28 | #include "qemu/error-report.h" | |
a9df9622 | 29 | #include "qemu/units.h" |
327d8e4e | 30 | |
74fb1f38 | 31 | static struct arm_boot_info aspeed_board_binfo = { |
b033271f | 32 | .board_id = -1, /* device-tree-only board */ |
327d8e4e AJ |
33 | }; |
34 | ||
ea066d39 | 35 | struct AspeedBoardState { |
ff90606f | 36 | AspeedSoCState soc; |
ad1a9782 | 37 | MemoryRegion ram_container; |
327d8e4e | 38 | MemoryRegion ram; |
ebe31c0a | 39 | MemoryRegion max_ram; |
ea066d39 | 40 | }; |
327d8e4e | 41 | |
ef17f836 | 42 | /* Palmetto hardware value: 0x120CE416 */ |
8da33ef7 CLG |
43 | #define PALMETTO_BMC_HW_STRAP1 ( \ |
44 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ | |
45 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ | |
46 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
47 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
48 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
49 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
50 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
51 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
52 | SCU_HW_STRAP_SPI_WIDTH | \ | |
53 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
54 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
55 | ||
ef17f836 | 56 | /* AST2500 evb hardware value: 0xF100C2E6 */ |
9a7c1750 CLG |
57 | #define AST2500_EVB_HW_STRAP1 (( \ |
58 | AST2500_HW_STRAP1_DEFAULTS | \ | |
59 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
60 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
61 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
62 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
63 | SCU_HW_STRAP_MAC1_RGMII | \ | |
64 | SCU_HW_STRAP_MAC0_RGMII) & \ | |
65 | ~SCU_HW_STRAP_2ND_BOOT_WDT) | |
66 | ||
ef17f836 CLG |
67 | /* Romulus hardware value: 0xF10AD206 */ |
68 | #define ROMULUS_BMC_HW_STRAP1 ( \ | |
69 | AST2500_HW_STRAP1_DEFAULTS | \ | |
70 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
71 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
72 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
73 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
74 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
75 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
76 | ||
aae7a18d AK |
77 | /* Swift hardware value: 0xF11AD206 */ |
78 | #define SWIFT_BMC_HW_STRAP1 ( \ | |
79 | AST2500_HW_STRAP1_DEFAULTS | \ | |
80 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
81 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
82 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
83 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
84 | SCU_H_PLL_BYPASS_EN | \ | |
85 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
86 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
87 | ||
62c2c2eb CLG |
88 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ |
89 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | |
90 | ||
ebe31c0a CLG |
91 | /* |
92 | * The max ram region is for firmwares that scan the address space | |
93 | * with load/store to guess how much RAM the SoC has. | |
94 | */ | |
95 | static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) | |
96 | { | |
97 | return 0; | |
98 | } | |
99 | ||
100 | static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, | |
101 | unsigned size) | |
102 | { | |
103 | /* Discard writes */ | |
104 | } | |
105 | ||
106 | static const MemoryRegionOps max_ram_ops = { | |
107 | .read = max_ram_read, | |
108 | .write = max_ram_write, | |
109 | .endianness = DEVICE_NATIVE_ENDIAN, | |
110 | }; | |
111 | ||
d769a1da CLG |
112 | #define FIRMWARE_ADDR 0x0 |
113 | ||
114 | static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, | |
115 | Error **errp) | |
116 | { | |
117 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); | |
118 | uint8_t *storage; | |
0c7209be CLG |
119 | int64_t size; |
120 | ||
121 | /* The block backend size should have already been 'validated' by | |
122 | * the creation of the m25p80 object. | |
123 | */ | |
124 | size = blk_getlength(blk); | |
125 | if (size <= 0) { | |
126 | error_setg(errp, "failed to get flash size"); | |
127 | return; | |
128 | } | |
d769a1da | 129 | |
0c7209be CLG |
130 | if (rom_size > size) { |
131 | rom_size = size; | |
d769a1da CLG |
132 | } |
133 | ||
134 | storage = g_new0(uint8_t, rom_size); | |
135 | if (blk_pread(blk, 0, storage, rom_size) < 0) { | |
136 | error_setg(errp, "failed to read the initial flash content"); | |
137 | return; | |
138 | } | |
139 | ||
140 | rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); | |
141 | g_free(storage); | |
142 | } | |
143 | ||
74fb1f38 | 144 | static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
e1ad9bc4 CLG |
145 | Error **errp) |
146 | { | |
147 | int i ; | |
148 | ||
149 | for (i = 0; i < s->num_cs; ++i) { | |
150 | AspeedSMCFlash *fl = &s->flashes[i]; | |
151 | DriveInfo *dinfo = drive_get_next(IF_MTD); | |
152 | qemu_irq cs_line; | |
153 | ||
e1ad9bc4 CLG |
154 | fl->flash = ssi_create_slave_no_init(s->spi, flashtype); |
155 | if (dinfo) { | |
156 | qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), | |
157 | errp); | |
158 | } | |
159 | qdev_init_nofail(fl->flash); | |
160 | ||
161 | cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); | |
162 | sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); | |
163 | } | |
164 | } | |
165 | ||
c3ba99f7 CLG |
166 | static void aspeed_board_init(MachineState *machine, |
167 | const AspeedBoardConfig *cfg) | |
327d8e4e | 168 | { |
74fb1f38 | 169 | AspeedBoardState *bmc; |
b033271f | 170 | AspeedSoCClass *sc; |
d769a1da | 171 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); |
ebe31c0a | 172 | ram_addr_t max_ram_size; |
2bea128c | 173 | int i; |
327d8e4e | 174 | |
74fb1f38 | 175 | bmc = g_new0(AspeedBoardState, 1); |
ad1a9782 CLG |
176 | |
177 | memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", | |
178 | UINT32_MAX); | |
179 | ||
1b0ad567 PMD |
180 | object_initialize_child(OBJECT(machine), "soc", &bmc->soc, |
181 | (sizeof(bmc->soc)), cfg->soc_name, &error_abort, | |
182 | NULL); | |
327d8e4e | 183 | |
b033271f CLG |
184 | sc = ASPEED_SOC_GET_CLASS(&bmc->soc); |
185 | ||
19e9cdf0 MAL |
186 | object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", |
187 | &error_abort); | |
c3ba99f7 | 188 | object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", |
87e79af0 | 189 | &error_abort); |
26d5df95 CLG |
190 | object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", |
191 | &error_abort); | |
cc7d44c2 | 192 | object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", |
ece09bee | 193 | &error_abort); |
c4e1f0b4 CLG |
194 | object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), |
195 | "dram", &error_abort); | |
b6e70d1d JS |
196 | if (machine->kernel_filename) { |
197 | /* | |
198 | * When booting with a -kernel command line there is no u-boot | |
199 | * that runs to unlock the SCU. In this case set the default to | |
200 | * be unlocked as the kernel expects | |
201 | */ | |
202 | object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, | |
203 | "hw-prot-key", &error_abort); | |
204 | } | |
327d8e4e AJ |
205 | object_property_set_bool(OBJECT(&bmc->soc), true, "realized", |
206 | &error_abort); | |
207 | ||
de46f5f4 CLG |
208 | /* |
209 | * Allocate RAM after the memory controller has checked the size | |
210 | * was valid. If not, a default value is used. | |
211 | */ | |
19e9cdf0 MAL |
212 | ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", |
213 | &error_abort); | |
de46f5f4 CLG |
214 | |
215 | memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); | |
ad1a9782 | 216 | memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); |
d783d1fe | 217 | memory_region_add_subregion(get_system_memory(), |
54ecafb7 | 218 | sc->memmap[ASPEED_SDRAM], |
ad1a9782 | 219 | &bmc->ram_container); |
de46f5f4 | 220 | |
ebe31c0a CLG |
221 | max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", |
222 | &error_abort); | |
223 | memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, | |
224 | "max_ram", max_ram_size - ram_size); | |
ad1a9782 | 225 | memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); |
ebe31c0a | 226 | |
6a0e947b CLG |
227 | aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); |
228 | aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); | |
74fb1f38 | 229 | |
d769a1da CLG |
230 | /* Install first FMC flash content as a boot rom. */ |
231 | if (drive0) { | |
232 | AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; | |
233 | MemoryRegion *boot_rom = g_new(MemoryRegion, 1); | |
234 | ||
235 | /* | |
236 | * create a ROM region using the default mapping window size of | |
93bf276d CLG |
237 | * the flash module. The window size is 64MB for the AST2400 |
238 | * SoC and 128MB for the AST2500 SoC, which is twice as big as | |
239 | * needed by the flash modules of the Aspeed machines. | |
d769a1da | 240 | */ |
44cf837d | 241 | memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", |
d769a1da CLG |
242 | fl->size, &error_abort); |
243 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | |
244 | boot_rom); | |
245 | write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); | |
246 | } | |
247 | ||
74fb1f38 | 248 | aspeed_board_binfo.ram_size = ram_size; |
54ecafb7 | 249 | aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; |
ece09bee | 250 | aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; |
e1ad9bc4 | 251 | |
2cf6cb50 CLG |
252 | if (cfg->i2c_init) { |
253 | cfg->i2c_init(bmc); | |
254 | } | |
255 | ||
2bea128c EJ |
256 | for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { |
257 | SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; | |
258 | DriveInfo *dinfo = drive_get_next(IF_SD); | |
259 | BlockBackend *blk; | |
260 | DeviceState *card; | |
261 | ||
262 | blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | |
263 | card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | |
264 | TYPE_SD_CARD); | |
265 | qdev_prop_set_drive(card, "drive", blk, &error_fatal); | |
266 | object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | |
267 | } | |
268 | ||
2744ece8 | 269 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); |
74fb1f38 | 270 | } |
b033271f | 271 | |
2cf6cb50 CLG |
272 | static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) |
273 | { | |
274 | AspeedSoCState *soc = &bmc->soc; | |
a87e81b9 | 275 | DeviceState *dev; |
3d165f12 | 276 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
2cf6cb50 CLG |
277 | |
278 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | |
279 | * enough to provide basic RTC features. Alarms will be missing */ | |
280 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); | |
a87e81b9 | 281 | |
3d165f12 CLG |
282 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, |
283 | eeprom_buf); | |
284 | ||
a87e81b9 CLG |
285 | /* add a TMP423 temperature sensor */ |
286 | dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), | |
287 | "tmp423", 0x4c); | |
288 | object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); | |
289 | object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); | |
290 | object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); | |
291 | object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | |
2cf6cb50 CLG |
292 | } |
293 | ||
2cf6cb50 CLG |
294 | static void ast2500_evb_i2c_init(AspeedBoardState *bmc) |
295 | { | |
296 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 CLG |
297 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
298 | ||
299 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, | |
300 | eeprom_buf); | |
2cf6cb50 CLG |
301 | |
302 | /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ | |
044475f3 PMD |
303 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), |
304 | TYPE_TMP105, 0x4d); | |
6c4567c7 CLG |
305 | |
306 | /* The AST2500 EVB does not have an RTC. Let's pretend that one is | |
307 | * plugged on the I2C bus header */ | |
308 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
2cf6cb50 CLG |
309 | } |
310 | ||
6c4567c7 CLG |
311 | static void romulus_bmc_i2c_init(AspeedBoardState *bmc) |
312 | { | |
313 | AspeedSoCState *soc = &bmc->soc; | |
314 | ||
315 | /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is | |
316 | * good enough */ | |
317 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
318 | } | |
319 | ||
aae7a18d AK |
320 | static void swift_bmc_i2c_init(AspeedBoardState *bmc) |
321 | { | |
322 | AspeedSoCState *soc = &bmc->soc; | |
323 | ||
324 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); | |
325 | ||
326 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
327 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); | |
328 | /* The swift board expects a pca9551 but a pca9552 is compatible */ | |
329 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); | |
330 | ||
331 | /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ | |
332 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); | |
333 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); | |
334 | ||
335 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); | |
336 | /* The swift board expects a pca9539 but a pca9552 is compatible */ | |
337 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); | |
338 | ||
339 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); | |
340 | /* The swift board expects a pca9539 but a pca9552 is compatible */ | |
341 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", | |
342 | 0x74); | |
343 | ||
344 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
345 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); | |
346 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); | |
347 | } | |
348 | ||
62c2c2eb CLG |
349 | static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) |
350 | { | |
351 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 | 352 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
62c2c2eb | 353 | |
044475f3 PMD |
354 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, |
355 | 0x60); | |
8c9a61d7 | 356 | |
62c2c2eb CLG |
357 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); |
358 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); | |
359 | ||
360 | /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ | |
044475f3 PMD |
361 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, |
362 | 0x4a); | |
6c4567c7 CLG |
363 | |
364 | /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is | |
365 | * good enough */ | |
366 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
3d165f12 CLG |
367 | |
368 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, | |
369 | eeprom_buf); | |
044475f3 | 370 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, |
8c9a61d7 | 371 | 0x60); |
62c2c2eb CLG |
372 | } |
373 | ||
fca9ca1b | 374 | static void aspeed_machine_init(MachineState *machine) |
62c2c2eb | 375 | { |
fca9ca1b CLG |
376 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
377 | ||
378 | aspeed_board_init(machine, amc->board); | |
62c2c2eb CLG |
379 | } |
380 | ||
fca9ca1b | 381 | static void aspeed_machine_class_init(ObjectClass *oc, void *data) |
62c2c2eb CLG |
382 | { |
383 | MachineClass *mc = MACHINE_CLASS(oc); | |
fca9ca1b CLG |
384 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
385 | const AspeedBoardConfig *board = data; | |
62c2c2eb | 386 | |
fca9ca1b CLG |
387 | mc->desc = board->desc; |
388 | mc->init = aspeed_machine_init; | |
ece09bee | 389 | mc->max_cpus = ASPEED_CPUS_NUM; |
62c2c2eb CLG |
390 | mc->no_floppy = 1; |
391 | mc->no_cdrom = 1; | |
392 | mc->no_parallel = 1; | |
a9df9622 JS |
393 | if (board->ram) { |
394 | mc->default_ram_size = board->ram; | |
395 | } | |
fca9ca1b | 396 | amc->board = board; |
62c2c2eb CLG |
397 | } |
398 | ||
fca9ca1b CLG |
399 | static const TypeInfo aspeed_machine_type = { |
400 | .name = TYPE_ASPEED_MACHINE, | |
62c2c2eb | 401 | .parent = TYPE_MACHINE, |
fca9ca1b CLG |
402 | .instance_size = sizeof(AspeedMachine), |
403 | .class_size = sizeof(AspeedMachineClass), | |
404 | .abstract = true, | |
405 | }; | |
406 | ||
407 | static const AspeedBoardConfig aspeed_boards[] = { | |
408 | { | |
409 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), | |
410 | .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", | |
411 | .soc_name = "ast2400-a1", | |
412 | .hw_strap1 = PALMETTO_BMC_HW_STRAP1, | |
413 | .fmc_model = "n25q256a", | |
414 | .spi_model = "mx25l25635e", | |
415 | .num_cs = 1, | |
416 | .i2c_init = palmetto_bmc_i2c_init, | |
a9df9622 | 417 | .ram = 256 * MiB, |
fca9ca1b CLG |
418 | }, { |
419 | .name = MACHINE_TYPE_NAME("ast2500-evb"), | |
420 | .desc = "Aspeed AST2500 EVB (ARM1176)", | |
421 | .soc_name = "ast2500-a1", | |
422 | .hw_strap1 = AST2500_EVB_HW_STRAP1, | |
423 | .fmc_model = "w25q256", | |
424 | .spi_model = "mx25l25635e", | |
425 | .num_cs = 1, | |
426 | .i2c_init = ast2500_evb_i2c_init, | |
a9df9622 | 427 | .ram = 512 * MiB, |
fca9ca1b CLG |
428 | }, { |
429 | .name = MACHINE_TYPE_NAME("romulus-bmc"), | |
430 | .desc = "OpenPOWER Romulus BMC (ARM1176)", | |
431 | .soc_name = "ast2500-a1", | |
432 | .hw_strap1 = ROMULUS_BMC_HW_STRAP1, | |
433 | .fmc_model = "n25q256a", | |
434 | .spi_model = "mx66l1g45g", | |
435 | .num_cs = 2, | |
436 | .i2c_init = romulus_bmc_i2c_init, | |
a9df9622 | 437 | .ram = 512 * MiB, |
aae7a18d AK |
438 | }, { |
439 | .name = MACHINE_TYPE_NAME("swift-bmc"), | |
440 | .desc = "OpenPOWER Swift BMC (ARM1176)", | |
441 | .soc_name = "ast2500-a1", | |
442 | .hw_strap1 = SWIFT_BMC_HW_STRAP1, | |
443 | .fmc_model = "mx66l1g45g", | |
444 | .spi_model = "mx66l1g45g", | |
445 | .num_cs = 2, | |
446 | .i2c_init = swift_bmc_i2c_init, | |
447 | .ram = 512 * MiB, | |
fca9ca1b CLG |
448 | }, { |
449 | .name = MACHINE_TYPE_NAME("witherspoon-bmc"), | |
450 | .desc = "OpenPOWER Witherspoon BMC (ARM1176)", | |
451 | .soc_name = "ast2500-a1", | |
452 | .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, | |
453 | .fmc_model = "mx25l25635e", | |
454 | .spi_model = "mx66l1g45g", | |
455 | .num_cs = 2, | |
456 | .i2c_init = witherspoon_bmc_i2c_init, | |
a9df9622 | 457 | .ram = 512 * MiB, |
fca9ca1b | 458 | }, |
62c2c2eb CLG |
459 | }; |
460 | ||
fca9ca1b | 461 | static void aspeed_machine_types(void) |
74fb1f38 | 462 | { |
fca9ca1b CLG |
463 | int i; |
464 | ||
465 | type_register_static(&aspeed_machine_type); | |
466 | for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { | |
467 | TypeInfo ti = { | |
468 | .name = aspeed_boards[i].name, | |
469 | .parent = TYPE_ASPEED_MACHINE, | |
470 | .class_init = aspeed_machine_class_init, | |
471 | .class_data = (void *)&aspeed_boards[i], | |
472 | }; | |
473 | type_register(&ti); | |
474 | } | |
74fb1f38 CLG |
475 | } |
476 | ||
fca9ca1b | 477 | type_init(aspeed_machine_types) |