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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
f25c0ae1 CLG |
12 | #include "hw/misc/unimp.h" |
13 | #include "hw/arm/aspeed_soc.h" | |
f25c0ae1 CLG |
14 | #include "qemu/module.h" |
15 | #include "qemu/error-report.h" | |
16 | #include "hw/i2c/aspeed_i2c.h" | |
17 | #include "net/net.h" | |
18 | #include "sysemu/sysemu.h" | |
19 | ||
20 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
d9e9cd59 | 21 | #define ASPEED_SOC_DPMCU_SIZE 0x00040000 |
f25c0ae1 CLG |
22 | |
23 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
347df6f8 | 24 | [ASPEED_DEV_SRAM] = 0x10000000, |
d9e9cd59 | 25 | [ASPEED_DEV_DPMCU] = 0x18000000, |
f25c0ae1 | 26 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
27 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
28 | [ASPEED_DEV_PWM] = 0x1E610000, | |
29 | [ASPEED_DEV_FMC] = 0x1E620000, | |
30 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
08048cbd | 31 | [ASPEED_DEV_SPI2] = 0x1E631000, |
347df6f8 EH |
32 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, |
33 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
34 | [ASPEED_DEV_MII1] = 0x1E650000, | |
35 | [ASPEED_DEV_MII2] = 0x1E650008, | |
36 | [ASPEED_DEV_MII3] = 0x1E650010, | |
37 | [ASPEED_DEV_MII4] = 0x1E650018, | |
38 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
39 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
40 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
41 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
42 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 43 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
44 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
45 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
46 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
47 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
d9e9cd59 | 48 | [ASPEED_DEV_DP] = 0x1E6EB000, |
e1acf581 | 49 | [ASPEED_DEV_SBC] = 0x1E6F2000, |
fe31a2ec | 50 | [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, |
347df6f8 EH |
51 | [ASPEED_DEV_VIDEO] = 0x1E700000, |
52 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
53 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
54 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
55 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
56 | [ASPEED_DEV_RTC] = 0x1E781000, | |
57 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
58 | [ASPEED_DEV_WDT] = 0x1E785000, | |
59 | [ASPEED_DEV_LPC] = 0x1E789000, | |
60 | [ASPEED_DEV_IBT] = 0x1E789140, | |
61 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
62 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
63 | [ASPEED_DEV_UART2] = 0x1E78D000, |
64 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
65 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 | 66 | [ASPEED_DEV_UART5] = 0x1E784000, |
ab5e8605 PD |
67 | [ASPEED_DEV_UART6] = 0x1E790000, |
68 | [ASPEED_DEV_UART7] = 0x1E790100, | |
69 | [ASPEED_DEV_UART8] = 0x1E790200, | |
70 | [ASPEED_DEV_UART9] = 0x1E790300, | |
71 | [ASPEED_DEV_UART10] = 0x1E790400, | |
72 | [ASPEED_DEV_UART11] = 0x1E790500, | |
73 | [ASPEED_DEV_UART12] = 0x1E790600, | |
74 | [ASPEED_DEV_UART13] = 0x1E790700, | |
347df6f8 | 75 | [ASPEED_DEV_VUART] = 0x1E787000, |
3222165d | 76 | [ASPEED_DEV_I3C] = 0x1E7A0000, |
347df6f8 | 77 | [ASPEED_DEV_SDRAM] = 0x80000000, |
f25c0ae1 CLG |
78 | }; |
79 | ||
80 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
81 | ||
b151de69 | 82 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 83 | |
a29e3e12 | 84 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 85 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
86 | [ASPEED_DEV_UART1] = 47, |
87 | [ASPEED_DEV_UART2] = 48, | |
88 | [ASPEED_DEV_UART3] = 49, | |
89 | [ASPEED_DEV_UART4] = 50, | |
90 | [ASPEED_DEV_UART5] = 8, | |
ab5e8605 PD |
91 | [ASPEED_DEV_UART6] = 57, |
92 | [ASPEED_DEV_UART7] = 58, | |
93 | [ASPEED_DEV_UART8] = 59, | |
94 | [ASPEED_DEV_UART9] = 60, | |
95 | [ASPEED_DEV_UART10] = 61, | |
96 | [ASPEED_DEV_UART11] = 62, | |
97 | [ASPEED_DEV_UART12] = 63, | |
98 | [ASPEED_DEV_UART13] = 64, | |
347df6f8 EH |
99 | [ASPEED_DEV_VUART] = 8, |
100 | [ASPEED_DEV_FMC] = 39, | |
101 | [ASPEED_DEV_SDMC] = 0, | |
102 | [ASPEED_DEV_SCU] = 12, | |
103 | [ASPEED_DEV_ADC] = 78, | |
104 | [ASPEED_DEV_XDMA] = 6, | |
105 | [ASPEED_DEV_SDHCI] = 43, | |
106 | [ASPEED_DEV_EHCI1] = 5, | |
107 | [ASPEED_DEV_EHCI2] = 9, | |
108 | [ASPEED_DEV_EMMC] = 15, | |
109 | [ASPEED_DEV_GPIO] = 40, | |
110 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
111 | [ASPEED_DEV_RTC] = 13, | |
112 | [ASPEED_DEV_TIMER1] = 16, | |
113 | [ASPEED_DEV_TIMER2] = 17, | |
114 | [ASPEED_DEV_TIMER3] = 18, | |
115 | [ASPEED_DEV_TIMER4] = 19, | |
116 | [ASPEED_DEV_TIMER5] = 20, | |
117 | [ASPEED_DEV_TIMER6] = 21, | |
118 | [ASPEED_DEV_TIMER7] = 22, | |
119 | [ASPEED_DEV_TIMER8] = 23, | |
120 | [ASPEED_DEV_WDT] = 24, | |
121 | [ASPEED_DEV_PWM] = 44, | |
122 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 123 | [ASPEED_DEV_IBT] = 143, |
347df6f8 EH |
124 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
125 | [ASPEED_DEV_ETH1] = 2, | |
126 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 127 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
128 | [ASPEED_DEV_ETH3] = 32, |
129 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 130 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
d9e9cd59 | 131 | [ASPEED_DEV_DP] = 62, |
3222165d | 132 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ |
f25c0ae1 CLG |
133 | }; |
134 | ||
699db715 | 135 | static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) |
f25c0ae1 CLG |
136 | { |
137 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
138 | ||
699db715 | 139 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); |
f25c0ae1 CLG |
140 | } |
141 | ||
142 | static void aspeed_soc_ast2600_init(Object *obj) | |
143 | { | |
144 | AspeedSoCState *s = ASPEED_SOC(obj); | |
145 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
146 | int i; | |
147 | char socname[8]; | |
148 | char typename[64]; | |
149 | ||
150 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
151 | g_assert_not_reached(); | |
152 | } | |
153 | ||
154 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 155 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
156 | } |
157 | ||
158 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 159 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
160 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
161 | sc->silicon_rev); | |
162 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 163 | "hw-strap1"); |
f25c0ae1 | 164 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 165 | "hw-strap2"); |
f25c0ae1 | 166 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 167 | "hw-prot-key"); |
f25c0ae1 | 168 | |
db873cc5 MA |
169 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
170 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 171 | |
db873cc5 | 172 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
173 | |
174 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 175 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 | 176 | |
199fd623 AJ |
177 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
178 | object_initialize_child(obj, "adc", &s->adc, typename); | |
179 | ||
f25c0ae1 | 180 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 181 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 CLG |
182 | |
183 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
db873cc5 | 184 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
f25c0ae1 CLG |
185 | |
186 | for (i = 0; i < sc->spis_num; i++) { | |
187 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 188 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
189 | } |
190 | ||
917940ce | 191 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
192 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
193 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
194 | } |
195 | ||
f25c0ae1 | 196 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 197 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 198 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 199 | "ram-size"); |
f25c0ae1 CLG |
200 | |
201 | for (i = 0; i < sc->wdts_num; i++) { | |
202 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 203 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
204 | } |
205 | ||
d300db02 | 206 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
207 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
208 | TYPE_FTGMAC100); | |
289251b0 | 209 | |
db873cc5 | 210 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
211 | } |
212 | ||
8efbee28 CLG |
213 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
214 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
f25c0ae1 CLG |
215 | |
216 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 217 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
218 | |
219 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 220 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 221 | |
db873cc5 MA |
222 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
223 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 224 | |
5325cc34 | 225 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 226 | |
f25c0ae1 CLG |
227 | /* Init sd card slot class here so that they're under the correct parent */ |
228 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
229 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
230 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 231 | } |
a29e3e12 | 232 | |
db873cc5 MA |
233 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
234 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 235 | |
5325cc34 | 236 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 237 | |
7089e0cc MA |
238 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
239 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
240 | |
241 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
242 | |
243 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
244 | object_initialize_child(obj, "hace", &s->hace, typename); | |
3222165d TL |
245 | |
246 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); | |
e1acf581 JS |
247 | |
248 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); | |
f25c0ae1 CLG |
249 | } |
250 | ||
251 | /* | |
252 | * ASPEED ast2600 has 0xf as cluster ID | |
253 | * | |
932a8d1f | 254 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
255 | */ |
256 | static uint64_t aspeed_calc_affinity(int cpu) | |
257 | { | |
258 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
259 | } | |
260 | ||
261 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
262 | { | |
263 | int i; | |
264 | AspeedSoCState *s = ASPEED_SOC(dev); | |
265 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 266 | Error *err = NULL; |
f25c0ae1 CLG |
267 | qemu_irq irq; |
268 | ||
269 | /* IO space */ | |
347df6f8 | 270 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
f25c0ae1 CLG |
271 | ASPEED_SOC_IOMEM_SIZE); |
272 | ||
514bcf6f | 273 | /* Video engine stub */ |
347df6f8 | 274 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
275 | 0x1000); |
276 | ||
fe31a2ec JS |
277 | /* eMMC Boot Controller stub */ |
278 | create_unimplemented_device("aspeed.emmc-boot-controller", | |
279 | sc->memmap[ASPEED_DEV_EMMC_BC], | |
280 | 0x1000); | |
281 | ||
f25c0ae1 | 282 | /* CPU */ |
b7f1a0cb | 283 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 284 | if (sc->num_cpus > 1) { |
5325cc34 MA |
285 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
286 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 287 | } |
5325cc34 MA |
288 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
289 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 290 | |
5325cc34 | 291 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 | 292 | &error_abort); |
e37976d7 PD |
293 | object_property_set_link(OBJECT(&s->cpu[i]), "memory", |
294 | OBJECT(get_system_memory()), &error_abort); | |
058d0955 | 295 | |
668f62ec | 296 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
297 | return; |
298 | } | |
299 | } | |
300 | ||
301 | /* A7MPCORE */ | |
5325cc34 | 302 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 303 | &error_abort); |
5325cc34 | 304 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
957ad79f | 305 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 306 | &error_abort); |
f25c0ae1 | 307 | |
db873cc5 | 308 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
f25c0ae1 CLG |
309 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
310 | ||
b7f1a0cb | 311 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 CLG |
312 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
313 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
314 | ||
315 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
316 | sysbus_connect_irq(sbd, i, irq); | |
317 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 318 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 319 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 320 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 321 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 322 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
323 | } |
324 | ||
325 | /* SRAM */ | |
326 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | |
327 | sc->sram_size, &err); | |
328 | if (err) { | |
329 | error_propagate(errp, err); | |
330 | return; | |
331 | } | |
332 | memory_region_add_subregion(get_system_memory(), | |
347df6f8 | 333 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 | 334 | |
d9e9cd59 TL |
335 | /* DPMCU */ |
336 | create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], | |
337 | ASPEED_SOC_DPMCU_SIZE); | |
338 | ||
f25c0ae1 | 339 | /* SCU */ |
668f62ec | 340 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
341 | return; |
342 | } | |
347df6f8 | 343 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
344 | |
345 | /* RTC */ | |
668f62ec | 346 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
347 | return; |
348 | } | |
347df6f8 | 349 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 350 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 351 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
352 | |
353 | /* Timer */ | |
5325cc34 MA |
354 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
355 | &error_abort); | |
668f62ec | 356 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
357 | return; |
358 | } | |
359 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
347df6f8 | 360 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 361 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 362 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
363 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
364 | } | |
365 | ||
199fd623 AJ |
366 | /* ADC */ |
367 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
368 | return; | |
369 | } | |
370 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); | |
371 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | |
372 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
373 | ||
470253b6 PD |
374 | /* UART */ |
375 | aspeed_soc_uart_init(s); | |
f25c0ae1 CLG |
376 | |
377 | /* I2C */ | |
5325cc34 | 378 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 379 | &error_abort); |
668f62ec | 380 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
381 | return; |
382 | } | |
347df6f8 | 383 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 CLG |
384 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
385 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
347df6f8 | 386 | sc->irqmap[ASPEED_DEV_I2C] + i); |
60261038 CLG |
387 | /* The AST2600 I2C controller has one IRQ per bus. */ |
388 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
f25c0ae1 CLG |
389 | } |
390 | ||
391 | /* FMC, The number of CS is set at the board level */ | |
5325cc34 | 392 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 393 | &error_abort); |
668f62ec | 394 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
395 | return; |
396 | } | |
347df6f8 | 397 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
f25c0ae1 | 398 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
30b6852c | 399 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
f25c0ae1 | 400 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 401 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 CLG |
402 | |
403 | /* SPI */ | |
404 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
405 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
406 | OBJECT(s->dram_mr), &error_abort); | |
668f62ec | 407 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
408 | return; |
409 | } | |
410 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
347df6f8 | 411 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
f25c0ae1 | 412 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 413 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
f25c0ae1 CLG |
414 | } |
415 | ||
917940ce GR |
416 | /* EHCI */ |
417 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 418 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
419 | return; |
420 | } | |
421 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 422 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 423 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 424 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
425 | } |
426 | ||
f25c0ae1 | 427 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 428 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
429 | return; |
430 | } | |
347df6f8 | 431 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
f25c0ae1 CLG |
432 | |
433 | /* Watch dog */ | |
434 | for (i = 0; i < sc->wdts_num; i++) { | |
435 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
436 | ||
5325cc34 MA |
437 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
438 | &error_abort); | |
668f62ec | 439 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
440 | return; |
441 | } | |
442 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 443 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
f25c0ae1 CLG |
444 | } |
445 | ||
346160cb CLG |
446 | /* RAM */ |
447 | if (!aspeed_soc_dram_init(s, errp)) { | |
448 | return; | |
449 | } | |
450 | ||
f25c0ae1 | 451 | /* Net */ |
d3bad7e7 | 452 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 453 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 454 | &error_abort); |
668f62ec | 455 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 456 | return; |
f25c0ae1 CLG |
457 | } |
458 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 459 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 460 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 461 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 462 | |
5325cc34 MA |
463 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
464 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 465 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
466 | return; |
467 | } | |
468 | ||
469 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | |
347df6f8 | 470 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
471 | } |
472 | ||
473 | /* XDMA */ | |
668f62ec | 474 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
475 | return; |
476 | } | |
477 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 478 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 479 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 480 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
481 | |
482 | /* GPIO */ | |
668f62ec | 483 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
484 | return; |
485 | } | |
347df6f8 | 486 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 487 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 488 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 489 | |
668f62ec | 490 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
491 | return; |
492 | } | |
493 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
347df6f8 | 494 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 495 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 496 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
497 | |
498 | /* SDHCI */ | |
668f62ec | 499 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
500 | return; |
501 | } | |
502 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 503 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 504 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 505 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
506 | |
507 | /* eMMC */ | |
668f62ec | 508 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
509 | return; |
510 | } | |
347df6f8 | 511 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); |
a29e3e12 | 512 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 513 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
514 | |
515 | /* LPC */ | |
516 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
517 | return; | |
518 | } | |
519 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
520 | |
521 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
522 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
523 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
524 | |
525 | /* | |
526 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
527 | * | |
528 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
529 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
530 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
531 | * offset 0. | |
532 | */ | |
533 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
534 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
535 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
536 | ||
537 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
538 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
539 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
540 | ||
541 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
542 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
543 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
544 | ||
545 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
546 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
547 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
a3888d75 JS |
548 | |
549 | /* HACE */ | |
550 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
551 | &error_abort); | |
552 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
553 | return; | |
554 | } | |
555 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
556 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
557 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
3222165d TL |
558 | |
559 | /* I3C */ | |
560 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { | |
561 | return; | |
562 | } | |
563 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); | |
564 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { | |
565 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
566 | sc->irqmap[ASPEED_DEV_I3C] + i); | |
567 | /* The AST2600 I3C controller has one IRQ per bus. */ | |
568 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | |
569 | } | |
e1acf581 JS |
570 | |
571 | /* Secure Boot Controller */ | |
572 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
573 | return; | |
574 | } | |
575 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); | |
f25c0ae1 CLG |
576 | } |
577 | ||
578 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
579 | { | |
580 | DeviceClass *dc = DEVICE_CLASS(oc); | |
581 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
582 | ||
583 | dc->realize = aspeed_soc_ast2600_realize; | |
584 | ||
c5811bb3 | 585 | sc->name = "ast2600-a3"; |
f25c0ae1 | 586 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
c5811bb3 | 587 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
e01b4d5b | 588 | sc->sram_size = 0x16400; |
f25c0ae1 | 589 | sc->spis_num = 2; |
917940ce | 590 | sc->ehcis_num = 2; |
f25c0ae1 | 591 | sc->wdts_num = 4; |
d300db02 | 592 | sc->macs_num = 4; |
c5e1bdb9 | 593 | sc->uarts_num = 13; |
f25c0ae1 CLG |
594 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
595 | sc->memmap = aspeed_soc_ast2600_memmap; | |
596 | sc->num_cpus = 2; | |
699db715 | 597 | sc->get_irq = aspeed_soc_ast2600_get_irq; |
f25c0ae1 CLG |
598 | } |
599 | ||
600 | static const TypeInfo aspeed_soc_ast2600_type_info = { | |
c5811bb3 | 601 | .name = "ast2600-a3", |
f25c0ae1 CLG |
602 | .parent = TYPE_ASPEED_SOC, |
603 | .instance_size = sizeof(AspeedSoCState), | |
604 | .instance_init = aspeed_soc_ast2600_init, | |
605 | .class_init = aspeed_soc_ast2600_class_init, | |
606 | .class_size = sizeof(AspeedSoCClass), | |
607 | }; | |
608 | ||
609 | static void aspeed_soc_register_types(void) | |
610 | { | |
611 | type_register_static(&aspeed_soc_ast2600_type_info); | |
612 | }; | |
613 | ||
614 | type_init(aspeed_soc_register_types) |