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intel_iommu: allow dev-iotlb context entry conditionally
[mirror_qemu.git] / hw / i386 / intel_iommu.c
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
4684a204 23#include "qemu/error-report.h"
6333e93c 24#include "qapi/error.h"
1da12ec4
LT		 25#include "hw/sysbus.h"
26#include "exec/address-spaces.h"
27#include "intel_iommu_internal.h"
7df953bd 28#include "hw/pci/pci.h"
3cb3b154 29#include "hw/pci/pci_bus.h"
621d983a 30#include "hw/i386/pc.h"
dea651a9 31#include "hw/i386/apic-msidef.h"
04af0e18
PX		 32#include "hw/boards.h"
33#include "hw/i386/x86-iommu.h"
cb135f59 34#include "hw/pci-host/q35.h"
4684a204 35#include "sysemu/kvm.h"
32946019 36#include "hw/i386/apic_internal.h"
fb506e70 37#include "kvm_i386.h"
bc535e59 38#include "trace.h"
1da12ec4
LT		 39
40/*#define DEBUG_INTEL_IOMMU*/
41#ifdef DEBUG_INTEL_IOMMU
42enum {
43 DEBUG_GENERAL, DEBUG_CSR, DEBUG_INV, DEBUG_MMU, DEBUG_FLOG,
a5861439 44 DEBUG_CACHE, DEBUG_IR,
1da12ec4
LT		 45};
46#define VTD_DBGBIT(x) (1 << DEBUG_##x)
47static int vtd_dbgflags = VTD_DBGBIT(GENERAL) | VTD_DBGBIT(CSR);
48
49#define VTD_DPRINTF(what, fmt, ...) do { \
50 if (vtd_dbgflags & VTD_DBGBIT(what)) { \
51 fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \
52 ## __VA_ARGS__); } \
53 } while (0)
54#else
55#define VTD_DPRINTF(what, fmt, ...) do {} while (0)
56#endif
57
58static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
59 uint64_t wmask, uint64_t w1cmask)
60{
61 stq_le_p(&s->csr[addr], val);
62 stq_le_p(&s->wmask[addr], wmask);
63 stq_le_p(&s->w1cmask[addr], w1cmask);
64}
65
66static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
67{
68 stq_le_p(&s->womask[addr], mask);
69}
70
71static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
72 uint32_t wmask, uint32_t w1cmask)
73{
74 stl_le_p(&s->csr[addr], val);
75 stl_le_p(&s->wmask[addr], wmask);
76 stl_le_p(&s->w1cmask[addr], w1cmask);
77}
78
79static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
80{
81 stl_le_p(&s->womask[addr], mask);
82}
83
84/* "External" get/set operations */
85static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
86{
87 uint64_t oldval = ldq_le_p(&s->csr[addr]);
88 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
89 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
90 stq_le_p(&s->csr[addr],
91 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
92}
93
94static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
95{
96 uint32_t oldval = ldl_le_p(&s->csr[addr]);
97 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
98 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
99 stl_le_p(&s->csr[addr],
100 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
101}
102
103static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
104{
105 uint64_t val = ldq_le_p(&s->csr[addr]);
106 uint64_t womask = ldq_le_p(&s->womask[addr]);
107 return val & ~womask;
108}
109
110static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
111{
112 uint32_t val = ldl_le_p(&s->csr[addr]);
113 uint32_t womask = ldl_le_p(&s->womask[addr]);
114 return val & ~womask;
115}
116
117/* "Internal" get/set operations */
118static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
119{
120 return ldq_le_p(&s->csr[addr]);
121}
122
123static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
124{
125 return ldl_le_p(&s->csr[addr]);
126}
127
128static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
129{
130 stq_le_p(&s->csr[addr], val);
131}
132
133static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
134 uint32_t clear, uint32_t mask)
135{
136 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
137 stl_le_p(&s->csr[addr], new_val);
138 return new_val;
139}
140
141static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
142 uint64_t clear, uint64_t mask)
143{
144 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
145 stq_le_p(&s->csr[addr], new_val);
146 return new_val;
147}
148
b5a280c0
LT		 149/* GHashTable functions */
150static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
151{
152 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
153}
154
155static guint vtd_uint64_hash(gconstpointer v)
156{
157 return (guint)*(const uint64_t *)v;
158}
159
160static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
161 gpointer user_data)
162{
163 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
164 uint16_t domain_id = *(uint16_t *)user_data;
165 return entry->domain_id == domain_id;
166}
167
d66b969b
JW		 168/* The shift of an addr for a certain level of paging structure */
169static inline uint32_t vtd_slpt_level_shift(uint32_t level)
170{
7e58326a 171 assert(level != 0);
d66b969b
JW		 172 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
173}
174
175static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
176{
177 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
178}
179
b5a280c0
LT		 180static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
181 gpointer user_data)
182{
183 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
184 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 185 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
186 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 187 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 188 (((entry->gfn & info->mask) == gfn) ||
189 (entry->gfn == gfn_tlb));
b5a280c0
LT		 190}
191
d92fa2dc
LT		 192/* Reset all the gen of VTDAddressSpace to zero and set the gen of
193 * IntelIOMMUState to 1.
194 */
195static void vtd_reset_context_cache(IntelIOMMUState *s)
196{
d92fa2dc 197 VTDAddressSpace *vtd_as;
7df953bd
KO		 198 VTDBus *vtd_bus;
199 GHashTableIter bus_it;
d92fa2dc
LT		 200 uint32_t devfn_it;
201
7df953bd
KO		 202 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
203
d92fa2dc 204 VTD_DPRINTF(CACHE, "global context_cache_gen=1");
7df953bd 205 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
04af0e18 206 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 207 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 208 if (!vtd_as) {
209 continue;
210 }
211 vtd_as->context_cache_entry.context_cache_gen = 0;
212 }
213 }
214 s->context_cache_gen = 1;
215}
216
b5a280c0
LT		 217static void vtd_reset_iotlb(IntelIOMMUState *s)
218{
219 assert(s->iotlb);
220 g_hash_table_remove_all(s->iotlb);
221}
222
bacabb0a 223static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
d66b969b
JW		 224 uint32_t level)
225{
226 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
227 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
228}
229
230static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
231{
232 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
233}
234
b5a280c0
LT		 235static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
236 hwaddr addr)
237{
d66b969b 238 VTDIOTLBEntry *entry;
b5a280c0 239 uint64_t key;
d66b969b
JW		 240 int level;
241
242 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
243 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
244 source_id, level);
245 entry = g_hash_table_lookup(s->iotlb, &key);
246 if (entry) {
247 goto out;
248 }
249 }
b5a280c0 250
d66b969b
JW		 251out:
252 return entry;
b5a280c0
LT		 253}
254
255static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
256 uint16_t domain_id, hwaddr addr, uint64_t slpte,
d66b969b
JW		 257 bool read_flags, bool write_flags,
258 uint32_t level)
b5a280c0
LT		 259{
260 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
261 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 262 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0 263
6c441e1d 264 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
b5a280c0 265 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
6c441e1d 266 trace_vtd_iotlb_reset("iotlb exceeds size limit");
b5a280c0
LT		 267 vtd_reset_iotlb(s);
268 }
269
270 entry->gfn = gfn;
271 entry->domain_id = domain_id;
272 entry->slpte = slpte;
273 entry->read_flags = read_flags;
274 entry->write_flags = write_flags;
d66b969b
JW		 275 entry->mask = vtd_slpt_level_page_mask(level);
276 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 277 g_hash_table_replace(s->iotlb, key, entry);
278}
279
1da12ec4
LT		 280/* Given the reg addr of both the message data and address, generate an
281 * interrupt via MSI.
282 */
283static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
284 hwaddr mesg_data_reg)
285{
32946019 286 MSIMessage msi;
1da12ec4
LT		 287
288 assert(mesg_data_reg < DMAR_REG_SIZE);
289 assert(mesg_addr_reg < DMAR_REG_SIZE);
290
32946019
RK		 291 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
292 msi.data = vtd_get_long_raw(s, mesg_data_reg);
1da12ec4 293
32946019
RK		 294 VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32,
295 msi.address, msi.data);
296 apic_get_class()->send_msi(&msi);
1da12ec4
LT		 297}
298
299/* Generate a fault event to software via MSI if conditions are met.
300 * Notice that the value of FSTS_REG being passed to it should be the one
301 * before any update.
302 */
303static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
304{
305 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
306 pre_fsts & VTD_FSTS_IQE) {
307 VTD_DPRINTF(FLOG, "there are previous interrupt conditions "
308 "to be serviced by software, fault event is not generated "
309 "(FSTS_REG 0x%"PRIx32 ")", pre_fsts);
310 return;
311 }
312 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
313 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
314 VTD_DPRINTF(FLOG, "Interrupt Mask set, fault event is not generated");
315 } else {
316 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
317 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
318 }
319}
320
321/* Check if the Fault (F) field of the Fault Recording Register referenced by
322 * @index is Set.
323 */
324static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
325{
326 /* Each reg is 128-bit */
327 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
328 addr += 8; /* Access the high 64-bit half */
329
330 assert(index < DMAR_FRCD_REG_NR);
331
332 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
333}
334
335/* Update the PPF field of Fault Status Register.
336 * Should be called whenever change the F field of any fault recording
337 * registers.
338 */
339static void vtd_update_fsts_ppf(IntelIOMMUState *s)
340{
341 uint32_t i;
342 uint32_t ppf_mask = 0;
343
344 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
345 if (vtd_is_frcd_set(s, i)) {
346 ppf_mask = VTD_FSTS_PPF;
347 break;
348 }
349 }
350 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
351 VTD_DPRINTF(FLOG, "set PPF of FSTS_REG to %d", ppf_mask ? 1 : 0);
352}
353
354static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
355{
356 /* Each reg is 128-bit */
357 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
358 addr += 8; /* Access the high 64-bit half */
359
360 assert(index < DMAR_FRCD_REG_NR);
361
362 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
363 vtd_update_fsts_ppf(s);
364}
365
366/* Must not update F field now, should be done later */
367static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
368 uint16_t source_id, hwaddr addr,
369 VTDFaultReason fault, bool is_write)
370{
371 uint64_t hi = 0, lo;
372 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
373
374 assert(index < DMAR_FRCD_REG_NR);
375
376 lo = VTD_FRCD_FI(addr);
377 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
378 if (!is_write) {
379 hi |= VTD_FRCD_T;
380 }
381 vtd_set_quad_raw(s, frcd_reg_addr, lo);
382 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
383 VTD_DPRINTF(FLOG, "record to FRCD_REG #%"PRIu16 ": hi 0x%"PRIx64
384 ", lo 0x%"PRIx64, index, hi, lo);
385}
386
387/* Try to collapse multiple pending faults from the same requester */
388static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
389{
390 uint32_t i;
391 uint64_t frcd_reg;
392 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
393
394 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
395 frcd_reg = vtd_get_quad_raw(s, addr);
396 VTD_DPRINTF(FLOG, "frcd_reg #%d 0x%"PRIx64, i, frcd_reg);
397 if ((frcd_reg & VTD_FRCD_F) &&
398 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
399 return true;
400 }
401 addr += 16; /* 128-bit for each */
402 }
403 return false;
404}
405
406/* Log and report an DMAR (address translation) fault to software */
407static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
408 hwaddr addr, VTDFaultReason fault,
409 bool is_write)
410{
411 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
412
413 assert(fault < VTD_FR_MAX);
414
415 if (fault == VTD_FR_RESERVED_ERR) {
416 /* This is not a normal fault reason case. Drop it. */
417 return;
418 }
419 VTD_DPRINTF(FLOG, "sid 0x%"PRIx16 ", fault %d, addr 0x%"PRIx64
420 ", is_write %d", source_id, fault, addr, is_write);
421 if (fsts_reg & VTD_FSTS_PFO) {
422 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
423 "Primary Fault Overflow");
424 return;
425 }
426 if (vtd_try_collapse_fault(s, source_id)) {
427 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
428 "compression of faults");
429 return;
430 }
431 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
432 VTD_DPRINTF(FLOG, "Primary Fault Overflow and "
433 "new fault is not recorded, set PFO field");
434 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
435 return;
436 }
437
438 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
439
440 if (fsts_reg & VTD_FSTS_PPF) {
441 VTD_DPRINTF(FLOG, "there are pending faults already, "
442 "fault event is not generated");
443 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
444 s->next_frcd_reg++;
445 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
446 s->next_frcd_reg = 0;
447 }
448 } else {
449 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
450 VTD_FSTS_FRI(s->next_frcd_reg));
451 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
452 s->next_frcd_reg++;
453 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
454 s->next_frcd_reg = 0;
455 }
456 /* This case actually cause the PPF to be Set.
457 * So generate fault event (interrupt).
458 */
459 vtd_generate_fault_event(s, fsts_reg);
460 }
461}
462
ed7b8fbc
LT		 463/* Handle Invalidation Queue Errors of queued invalidation interface error
464 * conditions.
465 */
466static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
467{
468 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
469
470 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
471 vtd_generate_fault_event(s, fsts_reg);
472}
473
474/* Set the IWC field and try to generate an invalidation completion interrupt */
475static void vtd_generate_completion_event(IntelIOMMUState *s)
476{
ed7b8fbc 477 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
bc535e59 478 trace_vtd_inv_desc_wait_irq("One pending, skip current");
ed7b8fbc
LT		 479 return;
480 }
481 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
482 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
483 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
bc535e59
PX		 484 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
485 "new event not generated");
ed7b8fbc
LT		 486 return;
487 } else {
488 /* Generate the interrupt event */
bc535e59 489 trace_vtd_inv_desc_wait_irq("Generating complete event");
ed7b8fbc
LT		 490 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
491 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
492 }
493}
494
1da12ec4
LT		 495static inline bool vtd_root_entry_present(VTDRootEntry *root)
496{
497 return root->val & VTD_ROOT_ENTRY_P;
498}
499
500static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
501 VTDRootEntry *re)
502{
503 dma_addr_t addr;
504
505 addr = s->root + index * sizeof(*re);
506 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
6c441e1d 507 trace_vtd_re_invalid(re->rsvd, re->val);
1da12ec4
LT		 508 re->val = 0;
509 return -VTD_FR_ROOT_TABLE_INV;
510 }
511 re->val = le64_to_cpu(re->val);
512 return 0;
513}
514
8f7d7161 515static inline bool vtd_ce_present(VTDContextEntry *context)
1da12ec4
LT		 516{
517 return context->lo & VTD_CONTEXT_ENTRY_P;
518}
519
520static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
521 VTDContextEntry *ce)
522{
523 dma_addr_t addr;
524
6c441e1d 525 /* we have checked that root entry is present */
1da12ec4
LT		 526 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
527 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
6c441e1d 528 trace_vtd_re_invalid(root->rsvd, root->val);
1da12ec4
LT		 529 return -VTD_FR_CONTEXT_TABLE_INV;
530 }
531 ce->lo = le64_to_cpu(ce->lo);
532 ce->hi = le64_to_cpu(ce->hi);
533 return 0;
534}
535
8f7d7161 536static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
1da12ec4
LT		 537{
538 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
539}
540
1da12ec4
LT		 541static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
542{
543 return slpte & VTD_SL_PT_BASE_ADDR_MASK;
544}
545
546/* Whether the pte indicates the address of the page frame */
547static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
548{
549 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
550}
551
552/* Get the content of a spte located in @base_addr[@index] */
553static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
554{
555 uint64_t slpte;
556
557 assert(index < VTD_SL_PT_ENTRY_NR);
558
559 if (dma_memory_read(&address_space_memory,
560 base_addr + index * sizeof(slpte), &slpte,
561 sizeof(slpte))) {
562 slpte = (uint64_t)-1;
563 return slpte;
564 }
565 slpte = le64_to_cpu(slpte);
566 return slpte;
567}
568
6e905564
PX		 569/* Given an iova and the level of paging structure, return the offset
570 * of current level.
1da12ec4 571 */
6e905564 572static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
1da12ec4 573{
6e905564 574 return (iova >> vtd_slpt_level_shift(level)) &
1da12ec4
LT		 575 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
576}
577
578/* Check Capability Register to see if the @level of page-table is supported */
579static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
580{
581 return VTD_CAP_SAGAW_MASK & s->cap &
582 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
583}
584
585/* Get the page-table level that hardware should use for the second-level
586 * page-table walk from the Address Width field of context-entry.
587 */
8f7d7161 588static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
1da12ec4
LT		 589{
590 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
591}
592
8f7d7161 593static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
1da12ec4
LT		 594{
595 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
596}
597
127ff5c3
PX		 598static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
599{
600 return ce->lo & VTD_CONTEXT_ENTRY_TT;
601}
602
f80c9874
PX		 603/* Return true if check passed, otherwise false */
604static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
605 VTDContextEntry *ce)
606{
607 switch (vtd_ce_get_type(ce)) {
608 case VTD_CONTEXT_TT_MULTI_LEVEL:
609 /* Always supported */
610 break;
611 case VTD_CONTEXT_TT_DEV_IOTLB:
612 if (!x86_iommu->dt_supported) {
613 return false;
614 }
615 break;
616 default:
617 /* Unknwon type */
618 return false;
619 }
620 return true;
621}
622
f06a696d
PX		 623static inline uint64_t vtd_iova_limit(VTDContextEntry *ce)
624{
8f7d7161 625 uint32_t ce_agaw = vtd_ce_get_agaw(ce);
f06a696d
PX		 626 return 1ULL << MIN(ce_agaw, VTD_MGAW);
627}
628
629/* Return true if IOVA passes range check, otherwise false. */
630static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce)
631{
632 /*
633 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
634 * in CAP_REG and AW in context-entry.
635 */
636 return !(iova & ~(vtd_iova_limit(ce) - 1));
637}
638
1da12ec4
LT		 639static const uint64_t vtd_paging_entry_rsvd_field[] = {
640 [0] = ~0ULL,
641 /* For not large page */
642 [1] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
643 [2] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
644 [3] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
645 [4] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
646 /* For large page */
647 [5] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
648 [6] = 0x1ff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
649 [7] = 0x3ffff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
650 [8] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
651};
652
653static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
654{
655 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
656 /* Maybe large page */
657 return slpte & vtd_paging_entry_rsvd_field[level + 4];
658 } else {
659 return slpte & vtd_paging_entry_rsvd_field[level];
660 }
661}
662
6e905564 663/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1da12ec4
LT		 664 * of the translation, can be used for deciding the size of large page.
665 */
6e905564
PX		 666static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
667 uint64_t *slptep, uint32_t *slpte_level,
668 bool *reads, bool *writes)
1da12ec4 669{
8f7d7161
PX		 670 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
671 uint32_t level = vtd_ce_get_level(ce);
1da12ec4
LT		 672 uint32_t offset;
673 uint64_t slpte;
1da12ec4
LT		 674 uint64_t access_right_check;
675
f06a696d 676 if (!vtd_iova_range_check(iova, ce)) {
6e905564 677 VTD_DPRINTF(GENERAL, "error: iova 0x%"PRIx64 " exceeds limits", iova);
1da12ec4
LT		 678 return -VTD_FR_ADDR_BEYOND_MGAW;
679 }
680
681 /* FIXME: what is the Atomics request here? */
682 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
683
684 while (true) {
6e905564 685 offset = vtd_iova_level_offset(iova, level);
1da12ec4
LT		 686 slpte = vtd_get_slpte(addr, offset);
687
688 if (slpte == (uint64_t)-1) {
689 VTD_DPRINTF(GENERAL, "error: fail to access second-level paging "
6e905564
PX		 690 "entry at level %"PRIu32 " for iova 0x%"PRIx64,
691 level, iova);
8f7d7161 692 if (level == vtd_ce_get_level(ce)) {
1da12ec4
LT		 693 /* Invalid programming of context-entry */
694 return -VTD_FR_CONTEXT_ENTRY_INV;
695 } else {
696 return -VTD_FR_PAGING_ENTRY_INV;
697 }
698 }
699 *reads = (*reads) && (slpte & VTD_SL_R);
700 *writes = (*writes) && (slpte & VTD_SL_W);
701 if (!(slpte & access_right_check)) {
702 VTD_DPRINTF(GENERAL, "error: lack of %s permission for "
6e905564
PX		 703 "iova 0x%"PRIx64 " slpte 0x%"PRIx64,
704 (is_write ? "write" : "read"), iova, slpte);
1da12ec4
LT		 705 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
706 }
707 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
708 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in second "
709 "level paging entry level %"PRIu32 " slpte 0x%"PRIx64,
710 level, slpte);
711 return -VTD_FR_PAGING_ENTRY_RSVD;
712 }
713
714 if (vtd_is_last_slpte(slpte, level)) {
715 *slptep = slpte;
716 *slpte_level = level;
717 return 0;
718 }
719 addr = vtd_get_slpte_addr(slpte);
720 level--;
721 }
722}
723
f06a696d
PX		 724typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
725
726/**
727 * vtd_page_walk_level - walk over specific level for IOVA range
728 *
729 * @addr: base GPA addr to start the walk
730 * @start: IOVA range start address
731 * @end: IOVA range end address (start <= addr < end)
732 * @hook_fn: hook func to be called when detected page
733 * @private: private data to be passed into hook func
734 * @read: whether parent level has read permission
735 * @write: whether parent level has write permission
736 * @notify_unmap: whether we should notify invalid entries
737 */
738static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
739 uint64_t end, vtd_page_walk_hook hook_fn,
740 void *private, uint32_t level,
741 bool read, bool write, bool notify_unmap)
742{
743 bool read_cur, write_cur, entry_valid;
744 uint32_t offset;
745 uint64_t slpte;
746 uint64_t subpage_size, subpage_mask;
747 IOMMUTLBEntry entry;
748 uint64_t iova = start;
749 uint64_t iova_next;
750 int ret = 0;
751
752 trace_vtd_page_walk_level(addr, level, start, end);
753
754 subpage_size = 1ULL << vtd_slpt_level_shift(level);
755 subpage_mask = vtd_slpt_level_page_mask(level);
756
757 while (iova < end) {
758 iova_next = (iova & subpage_mask) + subpage_size;
759
760 offset = vtd_iova_level_offset(iova, level);
761 slpte = vtd_get_slpte(addr, offset);
762
763 if (slpte == (uint64_t)-1) {
764 trace_vtd_page_walk_skip_read(iova, iova_next);
765 goto next;
766 }
767
768 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
769 trace_vtd_page_walk_skip_reserve(iova, iova_next);
770 goto next;
771 }
772
773 /* Permissions are stacked with parents' */
774 read_cur = read && (slpte & VTD_SL_R);
775 write_cur = write && (slpte & VTD_SL_W);
776
777 /*
778 * As long as we have either read/write permission, this is a
779 * valid entry. The rule works for both page entries and page
780 * table entries.
781 */
782 entry_valid = read_cur | write_cur;
783
784 if (vtd_is_last_slpte(slpte, level)) {
785 entry.target_as = &address_space_memory;
786 entry.iova = iova & subpage_mask;
787 /* NOTE: this is only meaningful if entry_valid == true */
788 entry.translated_addr = vtd_get_slpte_addr(slpte);
789 entry.addr_mask = ~subpage_mask;
790 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
791 if (!entry_valid && !notify_unmap) {
792 trace_vtd_page_walk_skip_perm(iova, iova_next);
793 goto next;
794 }
795 trace_vtd_page_walk_one(level, entry.iova, entry.translated_addr,
796 entry.addr_mask, entry.perm);
797 if (hook_fn) {
798 ret = hook_fn(&entry, private);
799 if (ret < 0) {
800 return ret;
801 }
802 }
803 } else {
804 if (!entry_valid) {
805 trace_vtd_page_walk_skip_perm(iova, iova_next);
806 goto next;
807 }
808 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte), iova,
809 MIN(iova_next, end), hook_fn, private,
810 level - 1, read_cur, write_cur,
811 notify_unmap);
812 if (ret < 0) {
813 return ret;
814 }
815 }
816
817next:
818 iova = iova_next;
819 }
820
821 return 0;
822}
823
824/**
825 * vtd_page_walk - walk specific IOVA range, and call the hook
826 *
827 * @ce: context entry to walk upon
828 * @start: IOVA address to start the walk
829 * @end: IOVA range end address (start <= addr < end)
830 * @hook_fn: the hook that to be called for each detected area
831 * @private: private data for the hook function
832 */
833static int vtd_page_walk(VTDContextEntry *ce, uint64_t start, uint64_t end,
dd4d607e
PX		 834 vtd_page_walk_hook hook_fn, void *private,
835 bool notify_unmap)
f06a696d 836{
8f7d7161
PX		 837 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
838 uint32_t level = vtd_ce_get_level(ce);
f06a696d
PX		 839
840 if (!vtd_iova_range_check(start, ce)) {
841 return -VTD_FR_ADDR_BEYOND_MGAW;
842 }
843
844 if (!vtd_iova_range_check(end, ce)) {
845 /* Fix end so that it reaches the maximum */
846 end = vtd_iova_limit(ce);
847 }
848
849 return vtd_page_walk_level(addr, start, end, hook_fn, private,
dd4d607e 850 level, true, true, notify_unmap);
f06a696d
PX		 851}
852
1da12ec4
LT		 853/* Map a device to its corresponding domain (context-entry) */
854static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
855 uint8_t devfn, VTDContextEntry *ce)
856{
857 VTDRootEntry re;
858 int ret_fr;
f80c9874 859 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1da12ec4
LT		 860
861 ret_fr = vtd_get_root_entry(s, bus_num, &re);
862 if (ret_fr) {
863 return ret_fr;
864 }
865
866 if (!vtd_root_entry_present(&re)) {
6c441e1d
PX		 867 /* Not error - it's okay we don't have root entry. */
868 trace_vtd_re_not_present(bus_num);
1da12ec4 869 return -VTD_FR_ROOT_ENTRY_P;
f80c9874
PX		 870 }
871
872 if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) {
6c441e1d 873 trace_vtd_re_invalid(re.rsvd, re.val);
1da12ec4
LT		 874 return -VTD_FR_ROOT_ENTRY_RSVD;
875 }
876
877 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
878 if (ret_fr) {
879 return ret_fr;
880 }
881
8f7d7161 882 if (!vtd_ce_present(ce)) {
6c441e1d
PX		 883 /* Not error - it's okay we don't have context entry. */
884 trace_vtd_ce_not_present(bus_num, devfn);
1da12ec4 885 return -VTD_FR_CONTEXT_ENTRY_P;
f80c9874
PX		 886 }
887
888 if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
889 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) {
6c441e1d 890 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4
LT		 891 return -VTD_FR_CONTEXT_ENTRY_RSVD;
892 }
f80c9874 893
1da12ec4 894 /* Check if the programming of context-entry is valid */
8f7d7161 895 if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
6c441e1d 896 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4 897 return -VTD_FR_CONTEXT_ENTRY_INV;
1da12ec4 898 }
f80c9874
PX		 899
900 /* Do translation type check */
901 if (!vtd_ce_type_check(x86_iommu, ce)) {
902 trace_vtd_ce_invalid(ce->hi, ce->lo);
903 return -VTD_FR_CONTEXT_ENTRY_INV;
904 }
905
1da12ec4
LT		 906 return 0;
907}
908
909static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
910{
911 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
912}
913
914static const bool vtd_qualified_faults[] = {
915 [VTD_FR_RESERVED] = false,
916 [VTD_FR_ROOT_ENTRY_P] = false,
917 [VTD_FR_CONTEXT_ENTRY_P] = true,
918 [VTD_FR_CONTEXT_ENTRY_INV] = true,
919 [VTD_FR_ADDR_BEYOND_MGAW] = true,
920 [VTD_FR_WRITE] = true,
921 [VTD_FR_READ] = true,
922 [VTD_FR_PAGING_ENTRY_INV] = true,
923 [VTD_FR_ROOT_TABLE_INV] = false,
924 [VTD_FR_CONTEXT_TABLE_INV] = false,
925 [VTD_FR_ROOT_ENTRY_RSVD] = false,
926 [VTD_FR_PAGING_ENTRY_RSVD] = true,
927 [VTD_FR_CONTEXT_ENTRY_TT] = true,
928 [VTD_FR_RESERVED_ERR] = false,
929 [VTD_FR_MAX] = false,
930};
931
932/* To see if a fault condition is "qualified", which is reported to software
933 * only if the FPD field in the context-entry used to process the faulting
934 * request is 0.
935 */
936static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
937{
938 return vtd_qualified_faults[fault];
939}
940
941static inline bool vtd_is_interrupt_addr(hwaddr addr)
942{
943 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
944}
945
946/* Map dev to context-entry then do a paging-structures walk to do a iommu
947 * translation.
79e2b9ae
PB		 948 *
949 * Called from RCU critical section.
950 *
1da12ec4
LT		 951 * @bus_num: The bus number
952 * @devfn: The devfn, which is the combined of device and function number
953 * @is_write: The access is a write operation
954 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
955 */
7df953bd 956static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 957 uint8_t devfn, hwaddr addr, bool is_write,
958 IOMMUTLBEntry *entry)
959{
d92fa2dc 960 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 961 VTDContextEntry ce;
7df953bd 962 uint8_t bus_num = pci_bus_num(bus);
d92fa2dc 963 VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
d66b969b 964 uint64_t slpte, page_mask;
1da12ec4
LT		 965 uint32_t level;
966 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
967 int ret_fr;
968 bool is_fpd_set = false;
969 bool reads = true;
970 bool writes = true;
b5a280c0 971 VTDIOTLBEntry *iotlb_entry;
1da12ec4 972
046ab7e9
PX		 973 /*
974 * We have standalone memory region for interrupt addresses, we
975 * should never receive translation requests in this region.
976 */
977 assert(!vtd_is_interrupt_addr(addr));
978
b5a280c0
LT		 979 /* Try to fetch slpte form IOTLB */
980 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
981 if (iotlb_entry) {
6c441e1d
PX		 982 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
983 iotlb_entry->domain_id);
b5a280c0
LT		 984 slpte = iotlb_entry->slpte;
985 reads = iotlb_entry->read_flags;
986 writes = iotlb_entry->write_flags;
d66b969b 987 page_mask = iotlb_entry->mask;
b5a280c0
LT		 988 goto out;
989 }
d92fa2dc
LT		 990 /* Try to fetch context-entry from cache first */
991 if (cc_entry->context_cache_gen == s->context_cache_gen) {
6c441e1d
PX		 992 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
993 cc_entry->context_entry.lo,
994 cc_entry->context_cache_gen);
d92fa2dc
LT		 995 ce = cc_entry->context_entry;
996 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
997 } else {
998 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
999 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1000 if (ret_fr) {
1001 ret_fr = -ret_fr;
1002 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1003 trace_vtd_fault_disabled();
d92fa2dc
LT		 1004 } else {
1005 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1006 }
1007 return;
1da12ec4 1008 }
d92fa2dc 1009 /* Update context-cache */
6c441e1d
PX		 1010 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1011 cc_entry->context_cache_gen,
1012 s->context_cache_gen);
d92fa2dc
LT		 1013 cc_entry->context_entry = ce;
1014 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 1015 }
1016
6e905564
PX		 1017 ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
1018 &reads, &writes);
1da12ec4
LT		 1019 if (ret_fr) {
1020 ret_fr = -ret_fr;
1021 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1022 trace_vtd_fault_disabled();
1da12ec4
LT		 1023 } else {
1024 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1025 }
1026 return;
1027 }
1028
d66b969b 1029 page_mask = vtd_slpt_level_page_mask(level);
b5a280c0 1030 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
d66b969b 1031 reads, writes, level);
b5a280c0 1032out:
d66b969b
JW		 1033 entry->iova = addr & page_mask;
1034 entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
1035 entry->addr_mask = ~page_mask;
5a38cb59 1036 entry->perm = IOMMU_ACCESS_FLAG(reads, writes);
1da12ec4
LT		 1037}
1038
1039static void vtd_root_table_setup(IntelIOMMUState *s)
1040{
1041 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1042 s->root_extended = s->root & VTD_RTADDR_RTT;
1043 s->root &= VTD_RTADDR_ADDR_MASK;
1044
1045 VTD_DPRINTF(CSR, "root_table addr 0x%"PRIx64 " %s", s->root,
1046 (s->root_extended ? "(extended)" : ""));
1047}
1048
02a2cbc8
PX		 1049static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1050 uint32_t index, uint32_t mask)
1051{
1052 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1053}
1054
a5861439
PX		 1055static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1056{
1057 uint64_t value = 0;
1058 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1059 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
1060 s->intr_root = value & VTD_IRTA_ADDR_MASK;
28589311 1061 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 1062
02a2cbc8
PX		 1063 /* Notify global invalidation */
1064 vtd_iec_notify_all(s, true, 0, 0);
a5861439
PX		 1065
1066 VTD_DPRINTF(CSR, "int remap table addr 0x%"PRIx64 " size %"PRIu32,
1067 s->intr_root, s->intr_size);
1068}
1069
dd4d607e
PX		 1070static void vtd_iommu_replay_all(IntelIOMMUState *s)
1071{
1072 IntelIOMMUNotifierNode *node;
1073
1074 QLIST_FOREACH(node, &s->notifiers_list, next) {
1075 memory_region_iommu_replay_all(&node->vtd_as->iommu);
1076 }
1077}
1078
d92fa2dc
LT		 1079static void vtd_context_global_invalidate(IntelIOMMUState *s)
1080{
bc535e59 1081 trace_vtd_inv_desc_cc_global();
d92fa2dc
LT		 1082 s->context_cache_gen++;
1083 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1084 vtd_reset_context_cache(s);
1085 }
dd4d607e
PX		 1086 /*
1087 * From VT-d spec 6.5.2.1, a global context entry invalidation
1088 * should be followed by a IOTLB global invalidation, so we should
1089 * be safe even without this. Hoewever, let's replay the region as
1090 * well to be safer, and go back here when we need finer tunes for
1091 * VT-d emulation codes.
1092 */
1093 vtd_iommu_replay_all(s);
d92fa2dc
LT		 1094}
1095
7df953bd
KO		 1096
1097/* Find the VTD address space currently associated with a given bus number,
1098 */
1099static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
1100{
1101 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
1102 if (!vtd_bus) {
1103 /* Iterate over the registered buses to find the one
1104 * which currently hold this bus number, and update the bus_num lookup table:
1105 */
1106 GHashTableIter iter;
1107
1108 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1109 while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) {
1110 if (pci_bus_num(vtd_bus->bus) == bus_num) {
1111 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
1112 return vtd_bus;
1113 }
1114 }
1115 }
1116 return vtd_bus;
1117}
1118
d92fa2dc
LT		 1119/* Do a context-cache device-selective invalidation.
1120 * @func_mask: FM field after shifting
1121 */
1122static void vtd_context_device_invalidate(IntelIOMMUState *s,
1123 uint16_t source_id,
1124 uint16_t func_mask)
1125{
1126 uint16_t mask;
7df953bd 1127 VTDBus *vtd_bus;
d92fa2dc 1128 VTDAddressSpace *vtd_as;
bc535e59 1129 uint8_t bus_n, devfn;
d92fa2dc
LT		 1130 uint16_t devfn_it;
1131
bc535e59
PX		 1132 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1133
d92fa2dc
LT		 1134 switch (func_mask & 3) {
1135 case 0:
1136 mask = 0; /* No bits in the SID field masked */
1137 break;
1138 case 1:
1139 mask = 4; /* Mask bit 2 in the SID field */
1140 break;
1141 case 2:
1142 mask = 6; /* Mask bit 2:1 in the SID field */
1143 break;
1144 case 3:
1145 mask = 7; /* Mask bit 2:0 in the SID field */
1146 break;
1147 }
6cb99acc 1148 mask = ~mask;
bc535e59
PX		 1149
1150 bus_n = VTD_SID_TO_BUS(source_id);
1151 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
7df953bd 1152 if (vtd_bus) {
d92fa2dc 1153 devfn = VTD_SID_TO_DEVFN(source_id);
04af0e18 1154 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 1155 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc 1156 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
bc535e59
PX		 1157 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1158 VTD_PCI_FUNC(devfn_it));
d92fa2dc 1159 vtd_as->context_cache_entry.context_cache_gen = 0;
dd4d607e
PX		 1160 /*
1161 * So a device is moving out of (or moving into) a
1162 * domain, a replay() suites here to notify all the
1163 * IOMMU_NOTIFIER_MAP registers about this change.
1164 * This won't bring bad even if we have no such
1165 * notifier registered - the IOMMU notification
1166 * framework will skip MAP notifications if that
1167 * happened.
1168 */
1169 memory_region_iommu_replay_all(&vtd_as->iommu);
d92fa2dc
LT		 1170 }
1171 }
1172 }
1173}
1174
1da12ec4
LT		 1175/* Context-cache invalidation
1176 * Returns the Context Actual Invalidation Granularity.
1177 * @val: the content of the CCMD_REG
1178 */
1179static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1180{
1181 uint64_t caig;
1182 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1183
1184 switch (type) {
d92fa2dc
LT		 1185 case VTD_CCMD_DOMAIN_INVL:
1186 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1187 (uint16_t)VTD_CCMD_DID(val));
1188 /* Fall through */
1da12ec4 1189 case VTD_CCMD_GLOBAL_INVL:
d92fa2dc 1190 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1191 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1192 vtd_context_global_invalidate(s);
1da12ec4
LT		 1193 break;
1194
1195 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1196 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1197 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1198 break;
1199
1200 default:
d92fa2dc 1201 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1202 caig = 0;
1203 }
1204 return caig;
1205}
1206
b5a280c0
LT		 1207static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1208{
6c441e1d 1209 trace_vtd_iotlb_reset("global invalidation recved");
b5a280c0 1210 vtd_reset_iotlb(s);
dd4d607e 1211 vtd_iommu_replay_all(s);
b5a280c0
LT		 1212}
1213
1214static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1215{
dd4d607e
PX		 1216 IntelIOMMUNotifierNode *node;
1217 VTDContextEntry ce;
1218 VTDAddressSpace *vtd_as;
1219
b5a280c0
LT		 1220 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1221 &domain_id);
dd4d607e
PX		 1222
1223 QLIST_FOREACH(node, &s->notifiers_list, next) {
1224 vtd_as = node->vtd_as;
1225 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1226 vtd_as->devfn, &ce) &&
1227 domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1228 memory_region_iommu_replay_all(&vtd_as->iommu);
1229 }
1230 }
1231}
1232
1233static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry *entry,
1234 void *private)
1235{
1236 memory_region_notify_iommu((MemoryRegion *)private, *entry);
1237 return 0;
1238}
1239
1240static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1241 uint16_t domain_id, hwaddr addr,
1242 uint8_t am)
1243{
1244 IntelIOMMUNotifierNode *node;
1245 VTDContextEntry ce;
1246 int ret;
1247
1248 QLIST_FOREACH(node, &(s->notifiers_list), next) {
1249 VTDAddressSpace *vtd_as = node->vtd_as;
1250 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1251 vtd_as->devfn, &ce);
1252 if (!ret && domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1253 vtd_page_walk(&ce, addr, addr + (1 << am) * VTD_PAGE_SIZE,
1254 vtd_page_invalidate_notify_hook,
1255 (void *)&vtd_as->iommu, true);
1256 }
1257 }
b5a280c0
LT		 1258}
1259
1260static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1261 hwaddr addr, uint8_t am)
1262{
1263 VTDIOTLBPageInvInfo info;
1264
1265 assert(am <= VTD_MAMV);
1266 info.domain_id = domain_id;
d66b969b 1267 info.addr = addr;
b5a280c0
LT		 1268 info.mask = ~((1 << am) - 1);
1269 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
dd4d607e 1270 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
b5a280c0
LT		 1271}
1272
1da12ec4
LT		 1273/* Flush IOTLB
1274 * Returns the IOTLB Actual Invalidation Granularity.
1275 * @val: the content of the IOTLB_REG
1276 */
1277static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1278{
1279 uint64_t iaig;
1280 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1281 uint16_t domain_id;
1282 hwaddr addr;
1283 uint8_t am;
1da12ec4
LT		 1284
1285 switch (type) {
1286 case VTD_TLB_GLOBAL_FLUSH:
b5a280c0 1287 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1288 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1289 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1290 break;
1291
1292 case VTD_TLB_DSI_FLUSH:
b5a280c0
LT		 1293 domain_id = VTD_TLB_DID(val);
1294 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1295 domain_id);
1da12ec4 1296 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1297 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1298 break;
1299
1300 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1301 domain_id = VTD_TLB_DID(val);
1302 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1303 am = VTD_IVA_AM(addr);
1304 addr = VTD_IVA_ADDR(addr);
1305 VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1306 " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1307 if (am > VTD_MAMV) {
1308 VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1309 "%"PRIu8, (uint8_t)VTD_MAMV);
1310 iaig = 0;
1311 break;
1312 }
1da12ec4 1313 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1314 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1315 break;
1316
1317 default:
b5a280c0 1318 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1319 iaig = 0;
1320 }
1321 return iaig;
1322}
1323
ed7b8fbc
LT		 1324static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)
1325{
1326 return s->iq_tail == 0;
1327}
1328
1329static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1330{
1331 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1332 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1333}
1334
1335static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1336{
1337 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1338
1339 VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off"));
1340 if (en) {
1341 if (vtd_queued_inv_enable_check(s)) {
1342 s->iq = iqa_val & VTD_IQA_IQA_MASK;
1343 /* 2^(x+8) entries */
1344 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1345 s->qi_enabled = true;
1346 VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
1347 VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
1348 s->iq, s->iq_size);
1349 /* Ok - report back to driver */
1350 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1351 } else {
1352 VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: "
1353 "tail %"PRIu16, s->iq_tail);
1354 }
1355 } else {
1356 if (vtd_queued_inv_disable_check(s)) {
1357 /* disable Queued Invalidation */
1358 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1359 s->iq_head = 0;
1360 s->qi_enabled = false;
1361 /* Ok - report back to driver */
1362 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1363 } else {
1364 VTD_DPRINTF(GENERAL, "error: can't disable Queued Invalidation: "
1365 "head %"PRIu16 ", tail %"PRIu16
1366 ", last_descriptor %"PRIu8,
1367 s->iq_head, s->iq_tail, s->iq_last_desc_type);
1368 }
1369 }
1370}
1371
1da12ec4
LT		 1372/* Set Root Table Pointer */
1373static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1374{
1375 VTD_DPRINTF(CSR, "set Root Table Pointer");
1376
1377 vtd_root_table_setup(s);
1378 /* Ok - report back to driver */
1379 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1380}
1381
a5861439
PX		 1382/* Set Interrupt Remap Table Pointer */
1383static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1384{
1385 VTD_DPRINTF(CSR, "set Interrupt Remap Table Pointer");
1386
1387 vtd_interrupt_remap_table_setup(s);
1388 /* Ok - report back to driver */
1389 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1390}
1391
558e0024
PX		 1392static void vtd_switch_address_space(VTDAddressSpace *as)
1393{
1394 assert(as);
1395
1396 trace_vtd_switch_address_space(pci_bus_num(as->bus),
1397 VTD_PCI_SLOT(as->devfn),
1398 VTD_PCI_FUNC(as->devfn),
1399 as->iommu_state->dmar_enabled);
1400
1401 /* Turn off first then on the other */
1402 if (as->iommu_state->dmar_enabled) {
1403 memory_region_set_enabled(&as->sys_alias, false);
1404 memory_region_set_enabled(&as->iommu, true);
1405 } else {
1406 memory_region_set_enabled(&as->iommu, false);
1407 memory_region_set_enabled(&as->sys_alias, true);
1408 }
1409}
1410
1411static void vtd_switch_address_space_all(IntelIOMMUState *s)
1412{
1413 GHashTableIter iter;
1414 VTDBus *vtd_bus;
1415 int i;
1416
1417 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1418 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
1419 for (i = 0; i < X86_IOMMU_PCI_DEVFN_MAX; i++) {
1420 if (!vtd_bus->dev_as[i]) {
1421 continue;
1422 }
1423 vtd_switch_address_space(vtd_bus->dev_as[i]);
1424 }
1425 }
1426}
1427
1da12ec4
LT		 1428/* Handle Translation Enable/Disable */
1429static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1430{
558e0024
PX		 1431 if (s->dmar_enabled == en) {
1432 return;
1433 }
1434
1da12ec4
LT		 1435 VTD_DPRINTF(CSR, "Translation Enable %s", (en ? "on" : "off"));
1436
1437 if (en) {
1438 s->dmar_enabled = true;
1439 /* Ok - report back to driver */
1440 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1441 } else {
1442 s->dmar_enabled = false;
1443
1444 /* Clear the index of Fault Recording Register */
1445 s->next_frcd_reg = 0;
1446 /* Ok - report back to driver */
1447 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1448 }
558e0024
PX		 1449
1450 vtd_switch_address_space_all(s);
1da12ec4
LT		 1451}
1452
80de52ba
PX		 1453/* Handle Interrupt Remap Enable/Disable */
1454static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1455{
1456 VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
1457
1458 if (en) {
1459 s->intr_enabled = true;
1460 /* Ok - report back to driver */
1461 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1462 } else {
1463 s->intr_enabled = false;
1464 /* Ok - report back to driver */
1465 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1466 }
1467}
1468
1da12ec4
LT		 1469/* Handle write to Global Command Register */
1470static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1471{
1472 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1473 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1474 uint32_t changed = status ^ val;
1475
1476 VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);
1477 if (changed & VTD_GCMD_TE) {
1478 /* Translation enable/disable */
1479 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1480 }
1481 if (val & VTD_GCMD_SRTP) {
1482 /* Set/update the root-table pointer */
1483 vtd_handle_gcmd_srtp(s);
1484 }
ed7b8fbc
LT		 1485 if (changed & VTD_GCMD_QIE) {
1486 /* Queued Invalidation Enable */
1487 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1488 }
a5861439
PX		 1489 if (val & VTD_GCMD_SIRTP) {
1490 /* Set/update the interrupt remapping root-table pointer */
1491 vtd_handle_gcmd_sirtp(s);
1492 }
80de52ba
PX		 1493 if (changed & VTD_GCMD_IRE) {
1494 /* Interrupt remap enable/disable */
1495 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1496 }
1da12ec4
LT		 1497}
1498
1499/* Handle write to Context Command Register */
1500static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1501{
1502 uint64_t ret;
1503 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1504
1505 /* Context-cache invalidation request */
1506 if (val & VTD_CCMD_ICC) {
ed7b8fbc
LT		 1507 if (s->qi_enabled) {
1508 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1509 "should not use register-based invalidation");
1510 return;
1511 }
1da12ec4
LT		 1512 ret = vtd_context_cache_invalidate(s, val);
1513 /* Invalidation completed. Change something to show */
1514 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1515 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1516 ret);
1517 VTD_DPRINTF(INV, "CCMD_REG write-back val: 0x%"PRIx64, ret);
1518 }
1519}
1520
1521/* Handle write to IOTLB Invalidation Register */
1522static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1523{
1524 uint64_t ret;
1525 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1526
1527 /* IOTLB invalidation request */
1528 if (val & VTD_TLB_IVT) {
ed7b8fbc
LT		 1529 if (s->qi_enabled) {
1530 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1531 "should not use register-based invalidation");
1532 return;
1533 }
1da12ec4
LT		 1534 ret = vtd_iotlb_flush(s, val);
1535 /* Invalidation completed. Change something to show */
1536 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1537 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1538 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1539 VTD_DPRINTF(INV, "IOTLB_REG write-back val: 0x%"PRIx64, ret);
1540 }
1541}
1542
ed7b8fbc
LT		 1543/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1544static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1545 VTDInvDesc *inv_desc)
1546{
1547 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1548 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1549 sizeof(*inv_desc))) {
1550 VTD_DPRINTF(GENERAL, "error: fail to fetch Invalidation Descriptor "
1551 "base_addr 0x%"PRIx64 " offset %"PRIu32, base_addr, offset);
1552 inv_desc->lo = 0;
1553 inv_desc->hi = 0;
1554
1555 return false;
1556 }
1557 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1558 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1559 return true;
1560}
1561
1562static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1563{
1564 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1565 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
bc535e59 1566 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1567 return false;
1568 }
1569 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1570 /* Status Write */
1571 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1572 VTD_INV_DESC_WAIT_DATA_SHIFT);
1573
1574 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1575
1576 /* FIXME: need to be masked with HAW? */
1577 dma_addr_t status_addr = inv_desc->hi;
bc535e59 1578 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
ed7b8fbc
LT		 1579 status_data = cpu_to_le32(status_data);
1580 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1581 sizeof(status_data))) {
bc535e59 1582 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1583 return false;
1584 }
1585 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1586 /* Interrupt flag */
ed7b8fbc
LT		 1587 vtd_generate_completion_event(s);
1588 } else {
bc535e59 1589 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1590 return false;
1591 }
1592 return true;
1593}
1594
d92fa2dc
LT		 1595static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1596 VTDInvDesc *inv_desc)
1597{
bc535e59
PX		 1598 uint16_t sid, fmask;
1599
d92fa2dc 1600 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
bc535e59 1601 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1602 return false;
1603 }
1604 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1605 case VTD_INV_DESC_CC_DOMAIN:
bc535e59
PX		 1606 trace_vtd_inv_desc_cc_domain(
1607 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
d92fa2dc
LT		 1608 /* Fall through */
1609 case VTD_INV_DESC_CC_GLOBAL:
d92fa2dc
LT		 1610 vtd_context_global_invalidate(s);
1611 break;
1612
1613 case VTD_INV_DESC_CC_DEVICE:
bc535e59
PX		 1614 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
1615 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
1616 vtd_context_device_invalidate(s, sid, fmask);
d92fa2dc
LT		 1617 break;
1618
1619 default:
bc535e59 1620 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1621 return false;
1622 }
1623 return true;
1624}
1625
b5a280c0
LT		 1626static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1627{
1628 uint16_t domain_id;
1629 uint8_t am;
1630 hwaddr addr;
1631
1632 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1633 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
bc535e59 1634 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1635 return false;
1636 }
1637
1638 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1639 case VTD_INV_DESC_IOTLB_GLOBAL:
bc535e59 1640 trace_vtd_inv_desc_iotlb_global();
b5a280c0
LT		 1641 vtd_iotlb_global_invalidate(s);
1642 break;
1643
1644 case VTD_INV_DESC_IOTLB_DOMAIN:
1645 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
bc535e59 1646 trace_vtd_inv_desc_iotlb_domain(domain_id);
b5a280c0
LT		 1647 vtd_iotlb_domain_invalidate(s, domain_id);
1648 break;
1649
1650 case VTD_INV_DESC_IOTLB_PAGE:
1651 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1652 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1653 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
bc535e59 1654 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
b5a280c0 1655 if (am > VTD_MAMV) {
bc535e59 1656 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1657 return false;
1658 }
1659 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1660 break;
1661
1662 default:
bc535e59 1663 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1664 return false;
1665 }
1666 return true;
1667}
1668
02a2cbc8
PX		 1669static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1670 VTDInvDesc *inv_desc)
1671{
1672 VTD_DPRINTF(INV, "inv ir glob %d index %d mask %d",
1673 inv_desc->iec.granularity,
1674 inv_desc->iec.index,
1675 inv_desc->iec.index_mask);
1676
1677 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1678 inv_desc->iec.index,
1679 inv_desc->iec.index_mask);
554f5e16
JW		 1680 return true;
1681}
1682
1683static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
1684 VTDInvDesc *inv_desc)
1685{
1686 VTDAddressSpace *vtd_dev_as;
1687 IOMMUTLBEntry entry;
1688 struct VTDBus *vtd_bus;
1689 hwaddr addr;
1690 uint64_t sz;
1691 uint16_t sid;
1692 uint8_t devfn;
1693 bool size;
1694 uint8_t bus_num;
1695
1696 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
1697 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
1698 devfn = sid & 0xff;
1699 bus_num = sid >> 8;
1700 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
1701
1702 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
1703 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
1704 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Device "
1705 "IOTLB Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1706 inv_desc->hi, inv_desc->lo);
1707 return false;
1708 }
1709
1710 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
1711 if (!vtd_bus) {
1712 goto done;
1713 }
1714
1715 vtd_dev_as = vtd_bus->dev_as[devfn];
1716 if (!vtd_dev_as) {
1717 goto done;
1718 }
1719
04eb6247
JW		 1720 /* According to ATS spec table 2.4:
1721 * S = 0, bits 15:12 = xxxx range size: 4K
1722 * S = 1, bits 15:12 = xxx0 range size: 8K
1723 * S = 1, bits 15:12 = xx01 range size: 16K
1724 * S = 1, bits 15:12 = x011 range size: 32K
1725 * S = 1, bits 15:12 = 0111 range size: 64K
1726 * ...
1727 */
554f5e16 1728 if (size) {
04eb6247 1729 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
554f5e16
JW		 1730 addr &= ~(sz - 1);
1731 } else {
1732 sz = VTD_PAGE_SIZE;
1733 }
02a2cbc8 1734
554f5e16
JW		 1735 entry.target_as = &vtd_dev_as->as;
1736 entry.addr_mask = sz - 1;
1737 entry.iova = addr;
1738 entry.perm = IOMMU_NONE;
1739 entry.translated_addr = 0;
10315b9b 1740 memory_region_notify_iommu(&vtd_dev_as->iommu, entry);
554f5e16
JW		 1741
1742done:
02a2cbc8
PX		 1743 return true;
1744}
1745
ed7b8fbc
LT		 1746static bool vtd_process_inv_desc(IntelIOMMUState *s)
1747{
1748 VTDInvDesc inv_desc;
1749 uint8_t desc_type;
1750
1751 VTD_DPRINTF(INV, "iq head %"PRIu16, s->iq_head);
1752 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1753 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1754 return false;
1755 }
1756 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1757 /* FIXME: should update at first or at last? */
1758 s->iq_last_desc_type = desc_type;
1759
1760 switch (desc_type) {
1761 case VTD_INV_DESC_CC:
bc535e59 1762 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1763 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1764 return false;
1765 }
ed7b8fbc
LT		 1766 break;
1767
1768 case VTD_INV_DESC_IOTLB:
bc535e59 1769 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1770 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1771 return false;
1772 }
ed7b8fbc
LT		 1773 break;
1774
1775 case VTD_INV_DESC_WAIT:
bc535e59 1776 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1777 if (!vtd_process_wait_desc(s, &inv_desc)) {
1778 return false;
1779 }
1780 break;
1781
b7910472 1782 case VTD_INV_DESC_IEC:
bc535e59 1783 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
02a2cbc8
PX		 1784 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1785 return false;
1786 }
b7910472
PX		 1787 break;
1788
554f5e16
JW		 1789 case VTD_INV_DESC_DEVICE:
1790 VTD_DPRINTF(INV, "Device IOTLB Invalidation Descriptor hi 0x%"PRIx64
1791 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1792 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
1793 return false;
1794 }
1795 break;
1796
ed7b8fbc 1797 default:
bc535e59 1798 trace_vtd_inv_desc_invalid(inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1799 return false;
1800 }
1801 s->iq_head++;
1802 if (s->iq_head == s->iq_size) {
1803 s->iq_head = 0;
1804 }
1805 return true;
1806}
1807
1808/* Try to fetch and process more Invalidation Descriptors */
1809static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1810{
1811 VTD_DPRINTF(INV, "fetch Invalidation Descriptors");
1812 if (s->iq_tail >= s->iq_size) {
1813 /* Detects an invalid Tail pointer */
1814 VTD_DPRINTF(GENERAL, "error: iq_tail is %"PRIu16
1815 " while iq_size is %"PRIu16, s->iq_tail, s->iq_size);
1816 vtd_handle_inv_queue_error(s);
1817 return;
1818 }
1819 while (s->iq_head != s->iq_tail) {
1820 if (!vtd_process_inv_desc(s)) {
1821 /* Invalidation Queue Errors */
1822 vtd_handle_inv_queue_error(s);
1823 break;
1824 }
1825 /* Must update the IQH_REG in time */
1826 vtd_set_quad_raw(s, DMAR_IQH_REG,
1827 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1828 VTD_IQH_QH_MASK);
1829 }
1830}
1831
1832/* Handle write to Invalidation Queue Tail Register */
1833static void vtd_handle_iqt_write(IntelIOMMUState *s)
1834{
1835 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1836
1837 s->iq_tail = VTD_IQT_QT(val);
1838 VTD_DPRINTF(INV, "set iq tail %"PRIu16, s->iq_tail);
1839 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1840 /* Process Invalidation Queue here */
1841 vtd_fetch_inv_desc(s);
1842 }
1843}
1844
1da12ec4
LT		 1845static void vtd_handle_fsts_write(IntelIOMMUState *s)
1846{
1847 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1848 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1849 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1850
1851 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1852 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1853 VTD_DPRINTF(FLOG, "all pending interrupt conditions serviced, clear "
1854 "IP field of FECTL_REG");
1855 }
ed7b8fbc
LT		 1856 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1857 * Descriptors if there are any when Queued Invalidation is enabled?
1858 */
1da12ec4
LT		 1859}
1860
1861static void vtd_handle_fectl_write(IntelIOMMUState *s)
1862{
1863 uint32_t fectl_reg;
1864 /* FIXME: when software clears the IM field, check the IP field. But do we
1865 * need to compare the old value and the new value to conclude that
1866 * software clears the IM field? Or just check if the IM field is zero?
1867 */
1868 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1869 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1870 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1871 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1872 VTD_DPRINTF(FLOG, "IM field is cleared, generate "
1873 "fault event interrupt");
1874 }
1875}
1876
ed7b8fbc
LT		 1877static void vtd_handle_ics_write(IntelIOMMUState *s)
1878{
1879 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1880 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1881
1882 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
1883 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1884 VTD_DPRINTF(INV, "pending completion interrupt condition serviced, "
1885 "clear IP field of IECTL_REG");
1886 }
1887}
1888
1889static void vtd_handle_iectl_write(IntelIOMMUState *s)
1890{
1891 uint32_t iectl_reg;
1892 /* FIXME: when software clears the IM field, check the IP field. But do we
1893 * need to compare the old value and the new value to conclude that
1894 * software clears the IM field? Or just check if the IM field is zero?
1895 */
1896 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1897 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
1898 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
1899 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1900 VTD_DPRINTF(INV, "IM field is cleared, generate "
1901 "invalidation event interrupt");
1902 }
1903}
1904
1da12ec4
LT		 1905static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
1906{
1907 IntelIOMMUState *s = opaque;
1908 uint64_t val;
1909
1910 if (addr + size > DMAR_REG_SIZE) {
1911 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1912 ", got 0x%"PRIx64 " %d",
1913 (uint64_t)DMAR_REG_SIZE, addr, size);
1914 return (uint64_t)-1;
1915 }
1916
1917 switch (addr) {
1918 /* Root Table Address Register, 64-bit */
1919 case DMAR_RTADDR_REG:
1920 if (size == 4) {
1921 val = s->root & ((1ULL << 32) - 1);
1922 } else {
1923 val = s->root;
1924 }
1925 break;
1926
1927 case DMAR_RTADDR_REG_HI:
1928 assert(size == 4);
1929 val = s->root >> 32;
1930 break;
1931
ed7b8fbc
LT		 1932 /* Invalidation Queue Address Register, 64-bit */
1933 case DMAR_IQA_REG:
1934 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
1935 if (size == 4) {
1936 val = val & ((1ULL << 32) - 1);
1937 }
1938 break;
1939
1940 case DMAR_IQA_REG_HI:
1941 assert(size == 4);
1942 val = s->iq >> 32;
1943 break;
1944
1da12ec4
LT		 1945 default:
1946 if (size == 4) {
1947 val = vtd_get_long(s, addr);
1948 } else {
1949 val = vtd_get_quad(s, addr);
1950 }
1951 }
1952 VTD_DPRINTF(CSR, "addr 0x%"PRIx64 " size %d val 0x%"PRIx64,
1953 addr, size, val);
1954 return val;
1955}
1956
1957static void vtd_mem_write(void *opaque, hwaddr addr,
1958 uint64_t val, unsigned size)
1959{
1960 IntelIOMMUState *s = opaque;
1961
1962 if (addr + size > DMAR_REG_SIZE) {
1963 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1964 ", got 0x%"PRIx64 " %d",
1965 (uint64_t)DMAR_REG_SIZE, addr, size);
1966 return;
1967 }
1968
1969 switch (addr) {
1970 /* Global Command Register, 32-bit */
1971 case DMAR_GCMD_REG:
1972 VTD_DPRINTF(CSR, "DMAR_GCMD_REG write addr 0x%"PRIx64
1973 ", size %d, val 0x%"PRIx64, addr, size, val);
1974 vtd_set_long(s, addr, val);
1975 vtd_handle_gcmd_write(s);
1976 break;
1977
1978 /* Context Command Register, 64-bit */
1979 case DMAR_CCMD_REG:
1980 VTD_DPRINTF(CSR, "DMAR_CCMD_REG write addr 0x%"PRIx64
1981 ", size %d, val 0x%"PRIx64, addr, size, val);
1982 if (size == 4) {
1983 vtd_set_long(s, addr, val);
1984 } else {
1985 vtd_set_quad(s, addr, val);
1986 vtd_handle_ccmd_write(s);
1987 }
1988 break;
1989
1990 case DMAR_CCMD_REG_HI:
1991 VTD_DPRINTF(CSR, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64
1992 ", size %d, val 0x%"PRIx64, addr, size, val);
1993 assert(size == 4);
1994 vtd_set_long(s, addr, val);
1995 vtd_handle_ccmd_write(s);
1996 break;
1997
1998 /* IOTLB Invalidation Register, 64-bit */
1999 case DMAR_IOTLB_REG:
2000 VTD_DPRINTF(INV, "DMAR_IOTLB_REG write addr 0x%"PRIx64
2001 ", size %d, val 0x%"PRIx64, addr, size, val);
2002 if (size == 4) {
2003 vtd_set_long(s, addr, val);
2004 } else {
2005 vtd_set_quad(s, addr, val);
2006 vtd_handle_iotlb_write(s);
2007 }
2008 break;
2009
2010 case DMAR_IOTLB_REG_HI:
2011 VTD_DPRINTF(INV, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64
2012 ", size %d, val 0x%"PRIx64, addr, size, val);
2013 assert(size == 4);
2014 vtd_set_long(s, addr, val);
2015 vtd_handle_iotlb_write(s);
2016 break;
2017
b5a280c0
LT		 2018 /* Invalidate Address Register, 64-bit */
2019 case DMAR_IVA_REG:
2020 VTD_DPRINTF(INV, "DMAR_IVA_REG write addr 0x%"PRIx64
2021 ", size %d, val 0x%"PRIx64, addr, size, val);
2022 if (size == 4) {
2023 vtd_set_long(s, addr, val);
2024 } else {
2025 vtd_set_quad(s, addr, val);
2026 }
2027 break;
2028
2029 case DMAR_IVA_REG_HI:
2030 VTD_DPRINTF(INV, "DMAR_IVA_REG_HI write addr 0x%"PRIx64
2031 ", size %d, val 0x%"PRIx64, addr, size, val);
2032 assert(size == 4);
2033 vtd_set_long(s, addr, val);
2034 break;
2035
1da12ec4
LT		 2036 /* Fault Status Register, 32-bit */
2037 case DMAR_FSTS_REG:
2038 VTD_DPRINTF(FLOG, "DMAR_FSTS_REG write addr 0x%"PRIx64
2039 ", size %d, val 0x%"PRIx64, addr, size, val);
2040 assert(size == 4);
2041 vtd_set_long(s, addr, val);
2042 vtd_handle_fsts_write(s);
2043 break;
2044
2045 /* Fault Event Control Register, 32-bit */
2046 case DMAR_FECTL_REG:
2047 VTD_DPRINTF(FLOG, "DMAR_FECTL_REG write addr 0x%"PRIx64
2048 ", size %d, val 0x%"PRIx64, addr, size, val);
2049 assert(size == 4);
2050 vtd_set_long(s, addr, val);
2051 vtd_handle_fectl_write(s);
2052 break;
2053
2054 /* Fault Event Data Register, 32-bit */
2055 case DMAR_FEDATA_REG:
2056 VTD_DPRINTF(FLOG, "DMAR_FEDATA_REG write addr 0x%"PRIx64
2057 ", size %d, val 0x%"PRIx64, addr, size, val);
2058 assert(size == 4);
2059 vtd_set_long(s, addr, val);
2060 break;
2061
2062 /* Fault Event Address Register, 32-bit */
2063 case DMAR_FEADDR_REG:
2064 VTD_DPRINTF(FLOG, "DMAR_FEADDR_REG write addr 0x%"PRIx64
2065 ", size %d, val 0x%"PRIx64, addr, size, val);
2066 assert(size == 4);
2067 vtd_set_long(s, addr, val);
2068 break;
2069
2070 /* Fault Event Upper Address Register, 32-bit */
2071 case DMAR_FEUADDR_REG:
2072 VTD_DPRINTF(FLOG, "DMAR_FEUADDR_REG write addr 0x%"PRIx64
2073 ", size %d, val 0x%"PRIx64, addr, size, val);
2074 assert(size == 4);
2075 vtd_set_long(s, addr, val);
2076 break;
2077
2078 /* Protected Memory Enable Register, 32-bit */
2079 case DMAR_PMEN_REG:
2080 VTD_DPRINTF(CSR, "DMAR_PMEN_REG write addr 0x%"PRIx64
2081 ", size %d, val 0x%"PRIx64, addr, size, val);
2082 assert(size == 4);
2083 vtd_set_long(s, addr, val);
2084 break;
2085
2086 /* Root Table Address Register, 64-bit */
2087 case DMAR_RTADDR_REG:
2088 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG write addr 0x%"PRIx64
2089 ", size %d, val 0x%"PRIx64, addr, size, val);
2090 if (size == 4) {
2091 vtd_set_long(s, addr, val);
2092 } else {
2093 vtd_set_quad(s, addr, val);
2094 }
2095 break;
2096
2097 case DMAR_RTADDR_REG_HI:
2098 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64
2099 ", size %d, val 0x%"PRIx64, addr, size, val);
2100 assert(size == 4);
2101 vtd_set_long(s, addr, val);
2102 break;
2103
ed7b8fbc
LT		 2104 /* Invalidation Queue Tail Register, 64-bit */
2105 case DMAR_IQT_REG:
2106 VTD_DPRINTF(INV, "DMAR_IQT_REG write addr 0x%"PRIx64
2107 ", size %d, val 0x%"PRIx64, addr, size, val);
2108 if (size == 4) {
2109 vtd_set_long(s, addr, val);
2110 } else {
2111 vtd_set_quad(s, addr, val);
2112 }
2113 vtd_handle_iqt_write(s);
2114 break;
2115
2116 case DMAR_IQT_REG_HI:
2117 VTD_DPRINTF(INV, "DMAR_IQT_REG_HI write addr 0x%"PRIx64
2118 ", size %d, val 0x%"PRIx64, addr, size, val);
2119 assert(size == 4);
2120 vtd_set_long(s, addr, val);
2121 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2122 break;
2123
2124 /* Invalidation Queue Address Register, 64-bit */
2125 case DMAR_IQA_REG:
2126 VTD_DPRINTF(INV, "DMAR_IQA_REG write addr 0x%"PRIx64
2127 ", size %d, val 0x%"PRIx64, addr, size, val);
2128 if (size == 4) {
2129 vtd_set_long(s, addr, val);
2130 } else {
2131 vtd_set_quad(s, addr, val);
2132 }
2133 break;
2134
2135 case DMAR_IQA_REG_HI:
2136 VTD_DPRINTF(INV, "DMAR_IQA_REG_HI write addr 0x%"PRIx64
2137 ", size %d, val 0x%"PRIx64, addr, size, val);
2138 assert(size == 4);
2139 vtd_set_long(s, addr, val);
2140 break;
2141
2142 /* Invalidation Completion Status Register, 32-bit */
2143 case DMAR_ICS_REG:
2144 VTD_DPRINTF(INV, "DMAR_ICS_REG write addr 0x%"PRIx64
2145 ", size %d, val 0x%"PRIx64, addr, size, val);
2146 assert(size == 4);
2147 vtd_set_long(s, addr, val);
2148 vtd_handle_ics_write(s);
2149 break;
2150
2151 /* Invalidation Event Control Register, 32-bit */
2152 case DMAR_IECTL_REG:
2153 VTD_DPRINTF(INV, "DMAR_IECTL_REG write addr 0x%"PRIx64
2154 ", size %d, val 0x%"PRIx64, addr, size, val);
2155 assert(size == 4);
2156 vtd_set_long(s, addr, val);
2157 vtd_handle_iectl_write(s);
2158 break;
2159
2160 /* Invalidation Event Data Register, 32-bit */
2161 case DMAR_IEDATA_REG:
2162 VTD_DPRINTF(INV, "DMAR_IEDATA_REG write addr 0x%"PRIx64
2163 ", size %d, val 0x%"PRIx64, addr, size, val);
2164 assert(size == 4);
2165 vtd_set_long(s, addr, val);
2166 break;
2167
2168 /* Invalidation Event Address Register, 32-bit */
2169 case DMAR_IEADDR_REG:
2170 VTD_DPRINTF(INV, "DMAR_IEADDR_REG write addr 0x%"PRIx64
2171 ", size %d, val 0x%"PRIx64, addr, size, val);
2172 assert(size == 4);
2173 vtd_set_long(s, addr, val);
2174 break;
2175
2176 /* Invalidation Event Upper Address Register, 32-bit */
2177 case DMAR_IEUADDR_REG:
2178 VTD_DPRINTF(INV, "DMAR_IEUADDR_REG write addr 0x%"PRIx64
2179 ", size %d, val 0x%"PRIx64, addr, size, val);
2180 assert(size == 4);
2181 vtd_set_long(s, addr, val);
2182 break;
2183
1da12ec4
LT		 2184 /* Fault Recording Registers, 128-bit */
2185 case DMAR_FRCD_REG_0_0:
2186 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64
2187 ", size %d, val 0x%"PRIx64, addr, size, val);
2188 if (size == 4) {
2189 vtd_set_long(s, addr, val);
2190 } else {
2191 vtd_set_quad(s, addr, val);
2192 }
2193 break;
2194
2195 case DMAR_FRCD_REG_0_1:
2196 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64
2197 ", size %d, val 0x%"PRIx64, addr, size, val);
2198 assert(size == 4);
2199 vtd_set_long(s, addr, val);
2200 break;
2201
2202 case DMAR_FRCD_REG_0_2:
2203 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64
2204 ", size %d, val 0x%"PRIx64, addr, size, val);
2205 if (size == 4) {
2206 vtd_set_long(s, addr, val);
2207 } else {
2208 vtd_set_quad(s, addr, val);
2209 /* May clear bit 127 (Fault), update PPF */
2210 vtd_update_fsts_ppf(s);
2211 }
2212 break;
2213
2214 case DMAR_FRCD_REG_0_3:
2215 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64
2216 ", size %d, val 0x%"PRIx64, addr, size, val);
2217 assert(size == 4);
2218 vtd_set_long(s, addr, val);
2219 /* May clear bit 127 (Fault), update PPF */
2220 vtd_update_fsts_ppf(s);
2221 break;
2222
a5861439
PX		 2223 case DMAR_IRTA_REG:
2224 VTD_DPRINTF(IR, "DMAR_IRTA_REG write addr 0x%"PRIx64
2225 ", size %d, val 0x%"PRIx64, addr, size, val);
2226 if (size == 4) {
2227 vtd_set_long(s, addr, val);
2228 } else {
2229 vtd_set_quad(s, addr, val);
2230 }
2231 break;
2232
2233 case DMAR_IRTA_REG_HI:
2234 VTD_DPRINTF(IR, "DMAR_IRTA_REG_HI write addr 0x%"PRIx64
2235 ", size %d, val 0x%"PRIx64, addr, size, val);
2236 assert(size == 4);
2237 vtd_set_long(s, addr, val);
2238 break;
2239
1da12ec4
LT		 2240 default:
2241 VTD_DPRINTF(GENERAL, "error: unhandled reg write addr 0x%"PRIx64
2242 ", size %d, val 0x%"PRIx64, addr, size, val);
2243 if (size == 4) {
2244 vtd_set_long(s, addr, val);
2245 } else {
2246 vtd_set_quad(s, addr, val);
2247 }
2248 }
2249}
2250
2251static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr,
bf55b7af 2252 IOMMUAccessFlags flag)
1da12ec4
LT		 2253{
2254 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2255 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4
LT		 2256 IOMMUTLBEntry ret = {
2257 .target_as = &address_space_memory,
2258 .iova = addr,
2259 .translated_addr = 0,
2260 .addr_mask = ~(hwaddr)0,
2261 .perm = IOMMU_NONE,
2262 };
2263
2264 if (!s->dmar_enabled) {
2265 /* DMAR disabled, passthrough, use 4k-page*/
2266 ret.iova = addr & VTD_PAGE_MASK_4K;
2267 ret.translated_addr = addr & VTD_PAGE_MASK_4K;
2268 ret.addr_mask = ~VTD_PAGE_MASK_4K;
2269 ret.perm = IOMMU_RW;
2270 return ret;
2271 }
2272
7df953bd 2273 vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr,
bf55b7af 2274 flag & IOMMU_WO, &ret);
1da12ec4
LT		 2275 VTD_DPRINTF(MMU,
2276 "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8
6e905564 2277 " iova 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bus),
d92fa2dc
LT		 2278 VTD_PCI_SLOT(vtd_as->devfn), VTD_PCI_FUNC(vtd_as->devfn),
2279 vtd_as->devfn, addr, ret.translated_addr);
1da12ec4
LT		 2280 return ret;
2281}
2282
5bf3d319
PX		 2283static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu,
2284 IOMMUNotifierFlag old,
2285 IOMMUNotifierFlag new)
3cb3b154
AW		 2286{
2287 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
dd4d607e
PX		 2288 IntelIOMMUState *s = vtd_as->iommu_state;
2289 IntelIOMMUNotifierNode *node = NULL;
2290 IntelIOMMUNotifierNode *next_node = NULL;
3cb3b154 2291
dd4d607e
PX		 2292 if (!s->caching_mode && new & IOMMU_NOTIFIER_MAP) {
2293 error_report("We need to set cache_mode=1 for intel-iommu to enable "
2294 "device assignment with IOMMU protection.");
a3276f78
PX		 2295 exit(1);
2296 }
dd4d607e
PX		 2297
2298 if (old == IOMMU_NOTIFIER_NONE) {
2299 node = g_malloc0(sizeof(*node));
2300 node->vtd_as = vtd_as;
2301 QLIST_INSERT_HEAD(&s->notifiers_list, node, next);
2302 return;
2303 }
2304
2305 /* update notifier node with new flags */
2306 QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) {
2307 if (node->vtd_as == vtd_as) {
2308 if (new == IOMMU_NOTIFIER_NONE) {
2309 QLIST_REMOVE(node, next);
2310 g_free(node);
2311 }
2312 return;
2313 }
2314 }
3cb3b154
AW		 2315}
2316
1da12ec4
LT		 2317static const VMStateDescription vtd_vmstate = {
2318 .name = "iommu-intel",
8cdcf3c1
PX		 2319 .version_id = 1,
2320 .minimum_version_id = 1,
2321 .priority = MIG_PRI_IOMMU,
2322 .fields = (VMStateField[]) {
2323 VMSTATE_UINT64(root, IntelIOMMUState),
2324 VMSTATE_UINT64(intr_root, IntelIOMMUState),
2325 VMSTATE_UINT64(iq, IntelIOMMUState),
2326 VMSTATE_UINT32(intr_size, IntelIOMMUState),
2327 VMSTATE_UINT16(iq_head, IntelIOMMUState),
2328 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
2329 VMSTATE_UINT16(iq_size, IntelIOMMUState),
2330 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
2331 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
2332 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
2333 VMSTATE_BOOL(root_extended, IntelIOMMUState),
2334 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
2335 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
2336 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
2337 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
2338 VMSTATE_END_OF_LIST()
2339 }
1da12ec4
LT		 2340};
2341
2342static const MemoryRegionOps vtd_mem_ops = {
2343 .read = vtd_mem_read,
2344 .write = vtd_mem_write,
2345 .endianness = DEVICE_LITTLE_ENDIAN,
2346 .impl = {
2347 .min_access_size = 4,
2348 .max_access_size = 8,
2349 },
2350 .valid = {
2351 .min_access_size = 4,
2352 .max_access_size = 8,
2353 },
2354};
2355
2356static Property vtd_properties[] = {
2357 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
e6b6af05
RK		 2358 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
2359 ON_OFF_AUTO_AUTO),
fb506e70 2360 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
3b40f0e5 2361 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
1da12ec4
LT		 2362 DEFINE_PROP_END_OF_LIST(),
2363};
2364
651e4cef
PX		 2365/* Read IRTE entry with specific index */
2366static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
bc38ee10 2367 VTD_IR_TableEntry *entry, uint16_t sid)
651e4cef 2368{
ede9c94a
PX		 2369 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
2370 {0xffff, 0xfffb, 0xfff9, 0xfff8};
651e4cef 2371 dma_addr_t addr = 0x00;
ede9c94a
PX		 2372 uint16_t mask, source_id;
2373 uint8_t bus, bus_max, bus_min;
651e4cef
PX		 2374
2375 addr = iommu->intr_root + index * sizeof(*entry);
2376 if (dma_memory_read(&address_space_memory, addr, entry,
2377 sizeof(*entry))) {
2378 VTD_DPRINTF(GENERAL, "error: fail to access IR root at 0x%"PRIx64
2379 " + %"PRIu16, iommu->intr_root, index);
2380 return -VTD_FR_IR_ROOT_INVAL;
2381 }
2382
bc38ee10 2383 if (!entry->irte.present) {
651e4cef
PX		 2384 VTD_DPRINTF(GENERAL, "error: present flag not set in IRTE"
2385 " entry index %u value 0x%"PRIx64 " 0x%"PRIx64,
2386 index, le64_to_cpu(entry->data[1]),
2387 le64_to_cpu(entry->data[0]));
2388 return -VTD_FR_IR_ENTRY_P;
2389 }
2390
bc38ee10
MT		 2391 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
2392 entry->irte.__reserved_2) {
651e4cef
PX		 2393 VTD_DPRINTF(GENERAL, "error: IRTE entry index %"PRIu16
2394 " reserved fields non-zero: 0x%"PRIx64 " 0x%"PRIx64,
2395 index, le64_to_cpu(entry->data[1]),
2396 le64_to_cpu(entry->data[0]));
2397 return -VTD_FR_IR_IRTE_RSVD;
2398 }
2399
ede9c94a
PX		 2400 if (sid != X86_IOMMU_SID_INVALID) {
2401 /* Validate IRTE SID */
bc38ee10
MT		 2402 source_id = le32_to_cpu(entry->irte.source_id);
2403 switch (entry->irte.sid_vtype) {
ede9c94a
PX		 2404 case VTD_SVT_NONE:
2405 VTD_DPRINTF(IR, "No SID validation for IRTE index %d", index);
2406 break;
2407
2408 case VTD_SVT_ALL:
bc38ee10 2409 mask = vtd_svt_mask[entry->irte.sid_q];
ede9c94a
PX		 2410 if ((source_id & mask) != (sid & mask)) {
2411 VTD_DPRINTF(GENERAL, "SID validation for IRTE index "
2412 "%d failed (reqid 0x%04x sid 0x%04x)", index,
2413 sid, source_id);
2414 return -VTD_FR_IR_SID_ERR;
2415 }
2416 break;
2417
2418 case VTD_SVT_BUS:
2419 bus_max = source_id >> 8;
2420 bus_min = source_id & 0xff;
2421 bus = sid >> 8;
2422 if (bus > bus_max || bus < bus_min) {
2423 VTD_DPRINTF(GENERAL, "SID validation for IRTE index %d "
2424 "failed (bus %d outside %d-%d)", index, bus,
2425 bus_min, bus_max);
2426 return -VTD_FR_IR_SID_ERR;
2427 }
2428 break;
2429
2430 default:
2431 VTD_DPRINTF(GENERAL, "Invalid SVT bits (0x%x) in IRTE index "
bc38ee10 2432 "%d", entry->irte.sid_vtype, index);
ede9c94a
PX		 2433 /* Take this as verification failure. */
2434 return -VTD_FR_IR_SID_ERR;
2435 break;
2436 }
2437 }
651e4cef
PX		 2438
2439 return 0;
2440}
2441
2442/* Fetch IRQ information of specific IR index */
ede9c94a
PX		 2443static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
2444 VTDIrq *irq, uint16_t sid)
651e4cef 2445{
bc38ee10 2446 VTD_IR_TableEntry irte = {};
651e4cef
PX		 2447 int ret = 0;
2448
ede9c94a 2449 ret = vtd_irte_get(iommu, index, &irte, sid);
651e4cef
PX		 2450 if (ret) {
2451 return ret;
2452 }
2453
bc38ee10
MT		 2454 irq->trigger_mode = irte.irte.trigger_mode;
2455 irq->vector = irte.irte.vector;
2456 irq->delivery_mode = irte.irte.delivery_mode;
2457 irq->dest = le32_to_cpu(irte.irte.dest_id);
28589311 2458 if (!iommu->intr_eime) {
651e4cef
PX		 2459#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2460#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2461 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2462 VTD_IR_APIC_DEST_SHIFT;
2463 }
bc38ee10
MT		 2464 irq->dest_mode = irte.irte.dest_mode;
2465 irq->redir_hint = irte.irte.redir_hint;
651e4cef
PX		 2466
2467 VTD_DPRINTF(IR, "remapping interrupt index %d: trig:%u,vec:%u,"
2468 "deliver:%u,dest:%u,dest_mode:%u", index,
2469 irq->trigger_mode, irq->vector, irq->delivery_mode,
2470 irq->dest, irq->dest_mode);
2471
2472 return 0;
2473}
2474
2475/* Generate one MSI message from VTDIrq info */
2476static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2477{
2478 VTD_MSIMessage msg = {};
2479
2480 /* Generate address bits */
2481 msg.dest_mode = irq->dest_mode;
2482 msg.redir_hint = irq->redir_hint;
2483 msg.dest = irq->dest;
32946019 2484 msg.__addr_hi = irq->dest & 0xffffff00;
651e4cef
PX		 2485 msg.__addr_head = cpu_to_le32(0xfee);
2486 /* Keep this from original MSI address bits */
2487 msg.__not_used = irq->msi_addr_last_bits;
2488
2489 /* Generate data bits */
2490 msg.vector = irq->vector;
2491 msg.delivery_mode = irq->delivery_mode;
2492 msg.level = 1;
2493 msg.trigger_mode = irq->trigger_mode;
2494
2495 msg_out->address = msg.msi_addr;
2496 msg_out->data = msg.msi_data;
2497}
2498
2499/* Interrupt remapping for MSI/MSI-X entry */
2500static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2501 MSIMessage *origin,
ede9c94a
PX		 2502 MSIMessage *translated,
2503 uint16_t sid)
651e4cef
PX		 2504{
2505 int ret = 0;
2506 VTD_IR_MSIAddress addr;
2507 uint16_t index;
09cd058a 2508 VTDIrq irq = {};
651e4cef
PX		 2509
2510 assert(origin && translated);
2511
2512 if (!iommu || !iommu->intr_enabled) {
2513 goto do_not_translate;
2514 }
2515
2516 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
2517 VTD_DPRINTF(GENERAL, "error: MSI addr high 32 bits nonzero"
2518 " during interrupt remapping: 0x%"PRIx32,
2519 (uint32_t)((origin->address & VTD_MSI_ADDR_HI_MASK) >> \
2520 VTD_MSI_ADDR_HI_SHIFT));
2521 return -VTD_FR_IR_REQ_RSVD;
2522 }
2523
2524 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
1a43713b 2525 if (addr.addr.__head != 0xfee) {
651e4cef
PX		 2526 VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: "
2527 "0x%"PRIx32, addr.data);
2528 return -VTD_FR_IR_REQ_RSVD;
2529 }
2530
2531 /* This is compatible mode. */
bc38ee10 2532 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
651e4cef
PX		 2533 goto do_not_translate;
2534 }
2535
bc38ee10 2536 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
651e4cef
PX		 2537
2538#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2539#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2540
bc38ee10 2541 if (addr.addr.sub_valid) {
651e4cef
PX		 2542 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2543 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2544 }
2545
ede9c94a 2546 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
651e4cef
PX		 2547 if (ret) {
2548 return ret;
2549 }
2550
bc38ee10 2551 if (addr.addr.sub_valid) {
651e4cef
PX		 2552 VTD_DPRINTF(IR, "received MSI interrupt");
2553 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
2554 VTD_DPRINTF(GENERAL, "error: MSI data bits non-zero for "
2555 "interrupt remappable entry: 0x%"PRIx32,
2556 origin->data);
2557 return -VTD_FR_IR_REQ_RSVD;
2558 }
2559 } else {
2560 uint8_t vector = origin->data & 0xff;
dea651a9
FW		 2561 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
2562
651e4cef
PX		 2563 VTD_DPRINTF(IR, "received IOAPIC interrupt");
2564 /* IOAPIC entry vector should be aligned with IRTE vector
2565 * (see vt-d spec 5.1.5.1). */
2566 if (vector != irq.vector) {
2567 VTD_DPRINTF(GENERAL, "IOAPIC vector inconsistent: "
2568 "entry: %d, IRTE: %d, index: %d",
2569 vector, irq.vector, index);
2570 }
dea651a9
FW		 2571
2572 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2573 * (see vt-d spec 5.1.5.1). */
2574 if (trigger_mode != irq.trigger_mode) {
2575 VTD_DPRINTF(GENERAL, "IOAPIC trigger mode inconsistent: "
2576 "entry: %u, IRTE: %u, index: %d",
2577 trigger_mode, irq.trigger_mode, index);
2578 }
2579
651e4cef
PX		 2580 }
2581
2582 /*
2583 * We'd better keep the last two bits, assuming that guest OS
2584 * might modify it. Keep it does not hurt after all.
2585 */
bc38ee10 2586 irq.msi_addr_last_bits = addr.addr.__not_care;
651e4cef
PX		 2587
2588 /* Translate VTDIrq to MSI message */
2589 vtd_generate_msi_message(&irq, translated);
2590
2591 VTD_DPRINTF(IR, "mapping MSI 0x%"PRIx64":0x%"PRIx32 " -> "
2592 "0x%"PRIx64":0x%"PRIx32, origin->address, origin->data,
2593 translated->address, translated->data);
2594 return 0;
2595
2596do_not_translate:
2597 memcpy(translated, origin, sizeof(*origin));
2598 return 0;
2599}
2600
8b5ed7df
PX		 2601static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2602 MSIMessage *dst, uint16_t sid)
2603{
ede9c94a
PX		 2604 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
2605 src, dst, sid);
8b5ed7df
PX		 2606}
2607
651e4cef
PX		 2608static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2609 uint64_t *data, unsigned size,
2610 MemTxAttrs attrs)
2611{
2612 return MEMTX_OK;
2613}
2614
2615static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2616 uint64_t value, unsigned size,
2617 MemTxAttrs attrs)
2618{
2619 int ret = 0;
09cd058a 2620 MSIMessage from = {}, to = {};
ede9c94a 2621 uint16_t sid = X86_IOMMU_SID_INVALID;
651e4cef
PX		 2622
2623 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2624 from.data = (uint32_t) value;
2625
ede9c94a
PX		 2626 if (!attrs.unspecified) {
2627 /* We have explicit Source ID */
2628 sid = attrs.requester_id;
2629 }
2630
2631 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
651e4cef
PX		 2632 if (ret) {
2633 /* TODO: report error */
2634 VTD_DPRINTF(GENERAL, "int remap fail for addr 0x%"PRIx64
2635 " data 0x%"PRIx32, from.address, from.data);
2636 /* Drop this interrupt */
2637 return MEMTX_ERROR;
2638 }
2639
2640 VTD_DPRINTF(IR, "delivering MSI 0x%"PRIx64":0x%"PRIx32
2641 " for device sid 0x%04x",
2642 to.address, to.data, sid);
2643
32946019 2644 apic_get_class()->send_msi(&to);
651e4cef
PX		 2645
2646 return MEMTX_OK;
2647}
2648
2649static const MemoryRegionOps vtd_mem_ir_ops = {
2650 .read_with_attrs = vtd_mem_ir_read,
2651 .write_with_attrs = vtd_mem_ir_write,
2652 .endianness = DEVICE_LITTLE_ENDIAN,
2653 .impl = {
2654 .min_access_size = 4,
2655 .max_access_size = 4,
2656 },
2657 .valid = {
2658 .min_access_size = 4,
2659 .max_access_size = 4,
2660 },
2661};
7df953bd
KO		 2662
2663VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2664{
2665 uintptr_t key = (uintptr_t)bus;
2666 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2667 VTDAddressSpace *vtd_dev_as;
e0a3c8cc 2668 char name[128];
7df953bd
KO		 2669
2670 if (!vtd_bus) {
2d3fc581
JW		 2671 uintptr_t *new_key = g_malloc(sizeof(*new_key));
2672 *new_key = (uintptr_t)bus;
7df953bd 2673 /* No corresponding free() */
04af0e18
PX		 2674 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
2675 X86_IOMMU_PCI_DEVFN_MAX);
7df953bd 2676 vtd_bus->bus = bus;
2d3fc581 2677 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
7df953bd
KO		 2678 }
2679
2680 vtd_dev_as = vtd_bus->dev_as[devfn];
2681
2682 if (!vtd_dev_as) {
e0a3c8cc 2683 snprintf(name, sizeof(name), "intel_iommu_devfn_%d", devfn);
7df953bd
KO		 2684 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2685
2686 vtd_dev_as->bus = bus;
2687 vtd_dev_as->devfn = (uint8_t)devfn;
2688 vtd_dev_as->iommu_state = s;
2689 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
558e0024
PX		 2690
2691 /*
2692 * Memory region relationships looks like (Address range shows
2693 * only lower 32 bits to make it short in length...):
2694 *
2695 * |-----------------+-------------------+----------|
2696 * | Name | Address range | Priority |
2697 * |-----------------+-------------------+----------+
2698 * | vtd_root | 00000000-ffffffff | 0 |
2699 * | intel_iommu | 00000000-ffffffff | 1 |
2700 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2701 * | intel_iommu_ir | fee00000-feefffff | 64 |
2702 * |-----------------+-------------------+----------|
2703 *
2704 * We enable/disable DMAR by switching enablement for
2705 * vtd_sys_alias and intel_iommu regions. IR region is always
2706 * enabled.
2707 */
7df953bd 2708 memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s),
558e0024
PX		 2709 &s->iommu_ops, "intel_iommu_dmar",
2710 UINT64_MAX);
2711 memory_region_init_alias(&vtd_dev_as->sys_alias, OBJECT(s),
2712 "vtd_sys_alias", get_system_memory(),
2713 0, memory_region_size(get_system_memory()));
651e4cef
PX		 2714 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2715 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2716 VTD_INTERRUPT_ADDR_SIZE);
558e0024
PX		 2717 memory_region_init(&vtd_dev_as->root, OBJECT(s),
2718 "vtd_root", UINT64_MAX);
2719 memory_region_add_subregion_overlap(&vtd_dev_as->root,
2720 VTD_INTERRUPT_ADDR_FIRST,
2721 &vtd_dev_as->iommu_ir, 64);
2722 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, name);
2723 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
2724 &vtd_dev_as->sys_alias, 1);
2725 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
2726 &vtd_dev_as->iommu, 1);
2727 vtd_switch_address_space(vtd_dev_as);
7df953bd
KO		 2728 }
2729 return vtd_dev_as;
2730}
2731
dd4d607e
PX		 2732/* Unmap the whole range in the notifier's scope. */
2733static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
2734{
2735 IOMMUTLBEntry entry;
2736 hwaddr size;
2737 hwaddr start = n->start;
2738 hwaddr end = n->end;
2739
2740 /*
2741 * Note: all the codes in this function has a assumption that IOVA
2742 * bits are no more than VTD_MGAW bits (which is restricted by
2743 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2744 */
2745
2746 if (end > VTD_ADDRESS_SIZE) {
2747 /*
2748 * Don't need to unmap regions that is bigger than the whole
2749 * VT-d supported address space size
2750 */
2751 end = VTD_ADDRESS_SIZE;
2752 }
2753
2754 assert(start <= end);
2755 size = end - start;
2756
2757 if (ctpop64(size) != 1) {
2758 /*
2759 * This size cannot format a correct mask. Let's enlarge it to
2760 * suite the minimum available mask.
2761 */
2762 int n = 64 - clz64(size);
2763 if (n > VTD_MGAW) {
2764 /* should not happen, but in case it happens, limit it */
2765 n = VTD_MGAW;
2766 }
2767 size = 1ULL << n;
2768 }
2769
2770 entry.target_as = &address_space_memory;
2771 /* Adjust iova for the size */
2772 entry.iova = n->start & ~(size - 1);
2773 /* This field is meaningless for unmap */
2774 entry.translated_addr = 0;
2775 entry.perm = IOMMU_NONE;
2776 entry.addr_mask = size - 1;
2777
2778 trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
2779 VTD_PCI_SLOT(as->devfn),
2780 VTD_PCI_FUNC(as->devfn),
2781 entry.iova, size);
2782
2783 memory_region_notify_one(n, &entry);
2784}
2785
2786static void vtd_address_space_unmap_all(IntelIOMMUState *s)
2787{
2788 IntelIOMMUNotifierNode *node;
2789 VTDAddressSpace *vtd_as;
2790 IOMMUNotifier *n;
2791
2792 QLIST_FOREACH(node, &s->notifiers_list, next) {
2793 vtd_as = node->vtd_as;
2794 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
2795 vtd_address_space_unmap(vtd_as, n);
2796 }
2797 }
2798}
2799
f06a696d
PX		 2800static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
2801{
2802 memory_region_notify_one((IOMMUNotifier *)private, entry);
2803 return 0;
2804}
2805
2806static void vtd_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n)
2807{
2808 VTDAddressSpace *vtd_as = container_of(mr, VTDAddressSpace, iommu);
2809 IntelIOMMUState *s = vtd_as->iommu_state;
2810 uint8_t bus_n = pci_bus_num(vtd_as->bus);
2811 VTDContextEntry ce;
2812
dd4d607e
PX		 2813 /*
2814 * The replay can be triggered by either a invalidation or a newly
2815 * created entry. No matter what, we release existing mappings
2816 * (it means flushing caches for UNMAP-only registers).
2817 */
2818 vtd_address_space_unmap(vtd_as, n);
2819
f06a696d 2820 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
f06a696d
PX		 2821 trace_vtd_replay_ce_valid(bus_n, PCI_SLOT(vtd_as->devfn),
2822 PCI_FUNC(vtd_as->devfn),
2823 VTD_CONTEXT_ENTRY_DID(ce.hi),
2824 ce.hi, ce.lo);
dd4d607e 2825 vtd_page_walk(&ce, 0, ~0ULL, vtd_replay_hook, (void *)n, false);
f06a696d
PX		 2826 } else {
2827 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
2828 PCI_FUNC(vtd_as->devfn));
2829 }
2830
2831 return;
2832}
2833
1da12ec4
LT		 2834/* Do the initialization. It will also be called when reset, so pay
2835 * attention when adding new initialization stuff.
2836 */
2837static void vtd_init(IntelIOMMUState *s)
2838{
d54bd7f8
PX		 2839 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2840
1da12ec4
LT		 2841 memset(s->csr, 0, DMAR_REG_SIZE);
2842 memset(s->wmask, 0, DMAR_REG_SIZE);
2843 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2844 memset(s->womask, 0, DMAR_REG_SIZE);
2845
2846 s->iommu_ops.translate = vtd_iommu_translate;
5bf3d319 2847 s->iommu_ops.notify_flag_changed = vtd_iommu_notify_flag_changed;
f06a696d 2848 s->iommu_ops.replay = vtd_iommu_replay;
1da12ec4
LT		 2849 s->root = 0;
2850 s->root_extended = false;
2851 s->dmar_enabled = false;
2852 s->iq_head = 0;
2853 s->iq_tail = 0;
2854 s->iq = 0;
2855 s->iq_size = 0;
2856 s->qi_enabled = false;
2857 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2858 s->next_frcd_reg = 0;
2859 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MGAW |
d66b969b 2860 VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
ed7b8fbc 2861 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2862
d54bd7f8 2863 if (x86_iommu->intr_supported) {
e6b6af05
RK		 2864 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
2865 if (s->intr_eim == ON_OFF_AUTO_ON) {
2866 s->ecap |= VTD_ECAP_EIM;
2867 }
2868 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
d54bd7f8
PX		 2869 }
2870
554f5e16
JW		 2871 if (x86_iommu->dt_supported) {
2872 s->ecap |= VTD_ECAP_DT;
2873 }
2874
3b40f0e5
ABD		 2875 if (s->caching_mode) {
2876 s->cap |= VTD_CAP_CM;
2877 }
2878
d92fa2dc 2879 vtd_reset_context_cache(s);
b5a280c0 2880 vtd_reset_iotlb(s);
d92fa2dc 2881
1da12ec4
LT		 2882 /* Define registers with default values and bit semantics */
2883 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2884 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2885 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2886 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2887 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2888 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2889 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2890 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2891 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2892
2893 /* Advanced Fault Logging not supported */
2894 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2895 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2896 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2897 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2898
2899 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2900 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2901 */
2902 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2903
2904 /* Treated as RO for implementations that PLMR and PHMR fields reported
2905 * as Clear in the CAP_REG.
2906 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2907 */
2908 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2909
ed7b8fbc
LT		 2910 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2911 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2912 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2913 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2914 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2915 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2916 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2917 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2918 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2919
1da12ec4
LT		 2920 /* IOTLB registers */
2921 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2922 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2923 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2924
2925 /* Fault Recording Registers, 128-bit */
2926 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2927 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 2928
2929 /*
28589311 2930 * Interrupt remapping registers.
a5861439 2931 */
28589311 2932 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 2933}
2934
2935/* Should not reset address_spaces when reset because devices will still use
2936 * the address space they got at first (won't ask the bus again).
2937 */
2938static void vtd_reset(DeviceState *dev)
2939{
2940 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2941
2942 VTD_DPRINTF(GENERAL, "");
2943 vtd_init(s);
dd4d607e
PX		 2944
2945 /*
2946 * When device reset, throw away all mappings and external caches
2947 */
2948 vtd_address_space_unmap_all(s);
1da12ec4
LT		 2949}
2950
621d983a
MA		 2951static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
2952{
2953 IntelIOMMUState *s = opaque;
2954 VTDAddressSpace *vtd_as;
2955
8e7a0a16 2956 assert(0 <= devfn && devfn < X86_IOMMU_PCI_DEVFN_MAX);
621d983a
MA		 2957
2958 vtd_as = vtd_find_add_as(s, bus, devfn);
2959 return &vtd_as->as;
2960}
2961
e6b6af05 2962static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
6333e93c 2963{
e6b6af05
RK		 2964 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2965
6333e93c
RK		 2966 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
2967 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
2968 !kvm_irqchip_is_split()) {
2969 error_setg(errp, "Intel Interrupt Remapping cannot work with "
2970 "kernel-irqchip=on, please use 'split|off'.");
2971 return false;
2972 }
e6b6af05
RK		 2973 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu->intr_supported) {
2974 error_setg(errp, "eim=on cannot be selected without intremap=on");
2975 return false;
2976 }
2977
2978 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
fb506e70
RK		 2979 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
2980 && x86_iommu->intr_supported ?
e6b6af05
RK		 2981 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
2982 }
fb506e70
RK		 2983 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
2984 if (!kvm_irqchip_in_kernel()) {
2985 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
2986 return false;
2987 }
2988 if (!kvm_enable_x2apic()) {
2989 error_setg(errp, "eim=on requires support on the KVM side"
2990 "(X2APIC_API, first shipped in v4.7)");
2991 return false;
2992 }
2993 }
e6b6af05 2994
6333e93c
RK		 2995 return true;
2996}
2997
1da12ec4
LT		 2998static void vtd_realize(DeviceState *dev, Error **errp)
2999{
ef0e8fc7
EH		 3000 MachineState *ms = MACHINE(qdev_get_machine());
3001 MachineClass *mc = MACHINE_GET_CLASS(ms);
3002 PCMachineState *pcms =
3003 PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE));
3004 PCIBus *bus;
1da12ec4 3005 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
4684a204 3006 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
1da12ec4 3007
ef0e8fc7
EH		 3008 if (!pcms) {
3009 error_setg(errp, "Machine-type '%s' not supported by intel-iommu",
3010 mc->name);
3011 return;
3012 }
3013
3014 bus = pcms->bus;
1da12ec4 3015 VTD_DPRINTF(GENERAL, "");
fb9f5926 3016 x86_iommu->type = TYPE_INTEL;
6333e93c 3017
e6b6af05 3018 if (!vtd_decide_config(s, errp)) {
6333e93c
RK		 3019 return;
3020 }
3021
dd4d607e 3022 QLIST_INIT(&s->notifiers_list);
7df953bd 3023 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 3024 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
3025 "intel_iommu", DMAR_REG_SIZE);
3026 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 3027 /* No corresponding destroy */
3028 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3029 g_free, g_free);
7df953bd
KO		 3030 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3031 g_free, g_free);
1da12ec4 3032 vtd_init(s);
621d983a
MA		 3033 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
3034 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 3035 /* Pseudo address space under root PCI bus. */
3036 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 3037}
3038
3039static void vtd_class_init(ObjectClass *klass, void *data)
3040{
3041 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 3042 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 3043
3044 dc->reset = vtd_reset;
1da12ec4
LT		 3045 dc->vmsd = &vtd_vmstate;
3046 dc->props = vtd_properties;
621d983a 3047 dc->hotpluggable = false;
1c7955c4 3048 x86_class->realize = vtd_realize;
8b5ed7df 3049 x86_class->int_remap = vtd_int_remap;
8ab5700c 3050 /* Supported by the pc-q35-* machine types */
e4f4fb1e 3051 dc->user_creatable = true;
1da12ec4
LT		 3052}
3053
3054static const TypeInfo vtd_info = {
3055 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 3056 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 3057 .instance_size = sizeof(IntelIOMMUState),
3058 .class_init = vtd_class_init,
3059};
3060
3061static void vtd_register_types(void)
3062{
3063 VTD_DPRINTF(GENERAL, "");
3064 type_register_static(&vtd_info);
3065}
3066
3067type_init(vtd_register_types)
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