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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
549e984e | 27 | #include "hw/i386/x86.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 | 32 | #include "hw/i386/topology.h" |
87abaa5d | 33 | #include "hw/i386/fw_cfg.h" |
54a40293 | 34 | #include "sysemu/cpus.h" |
0d09e41a | 35 | #include "hw/block/fdc.h" |
83c9f4ca PB |
36 | #include "hw/ide.h" |
37 | #include "hw/pci/pci.h" | |
2118196b | 38 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
39 | #include "hw/nvram/fw_cfg.h" |
40 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 41 | #include "hw/firmware/smbios.h" |
83c9f4ca | 42 | #include "hw/loader.h" |
ca20cf32 | 43 | #include "elf.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
47b43a1f | 45 | #include "multiboot.h" |
bcdb9064 | 46 | #include "hw/rtc/mc146818rtc.h" |
55f613ac | 47 | #include "hw/dma/i8257.h" |
0d09e41a | 48 | #include "hw/timer/i8254.h" |
47973a2d | 49 | #include "hw/input/i8042.h" |
64552b6b | 50 | #include "hw/irq.h" |
0d09e41a | 51 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
52 | #include "hw/pci/msi.h" |
53 | #include "hw/sysbus.h" | |
9c17d615 | 54 | #include "sysemu/sysemu.h" |
14a48c1d | 55 | #include "sysemu/tcg.h" |
e35704ba | 56 | #include "sysemu/numa.h" |
9c17d615 | 57 | #include "sysemu/kvm.h" |
b1c12027 | 58 | #include "sysemu/qtest.h" |
71e8a915 | 59 | #include "sysemu/reset.h" |
54d31236 | 60 | #include "sysemu/runstate.h" |
1d31f66b | 61 | #include "kvm_i386.h" |
0d09e41a | 62 | #include "hw/xen/xen.h" |
ab969087 | 63 | #include "hw/xen/start_info.h" |
a19cbfb3 | 64 | #include "ui/qemu-spice.h" |
022c62cb PB |
65 | #include "exec/memory.h" |
66 | #include "exec/address-spaces.h" | |
9c17d615 | 67 | #include "sysemu/arch_init.h" |
1de7afc9 | 68 | #include "qemu/bitmap.h" |
0c764a9d | 69 | #include "qemu/config-file.h" |
d49b6836 | 70 | #include "qemu/error-report.h" |
922a01a0 | 71 | #include "qemu/option.h" |
133ef074 | 72 | #include "qemu/cutils.h" |
0445259b | 73 | #include "hw/acpi/acpi.h" |
5ff020b7 | 74 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 75 | #include "hw/boards.h" |
72c194f7 | 76 | #include "acpi-build.h" |
95bee274 | 77 | #include "hw/mem/pc-dimm.h" |
e688df6b | 78 | #include "qapi/error.h" |
9af23989 | 79 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 80 | #include "qapi/visitor.h" |
2e5b09fd | 81 | #include "hw/core/cpu.h" |
a310e653 | 82 | #include "hw/usb.h" |
60c5e104 | 83 | #include "hw/i386/intel_iommu.h" |
489983d6 | 84 | #include "hw/net/ne2000-isa.h" |
06e0259a | 85 | #include "standard-headers/asm-x86/bootparam.h" |
a0a49813 DH |
86 | #include "hw/virtio/virtio-pmem-pci.h" |
87 | #include "hw/mem/memory-device.h" | |
6f479566 LX |
88 | #include "sysemu/replay.h" |
89 | #include "qapi/qmp/qerror.h" | |
97fd1ea8 | 90 | #include "config-devices.h" |
d6d059ca | 91 | #include "e820_memory_layout.h" |
149c50ca | 92 | #include "fw_cfg.h" |
80cabfad | 93 | |
471fd342 BS |
94 | /* debug PC/ISA interrupts */ |
95 | //#define DEBUG_IRQ | |
96 | ||
97 | #ifdef DEBUG_IRQ | |
98 | #define DPRINTF(fmt, ...) \ | |
99 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
100 | #else | |
101 | #define DPRINTF(fmt, ...) | |
102 | #endif | |
103 | ||
dd703b99 | 104 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 105 | |
9aec2e52 CH |
106 | GlobalProperty pc_compat_4_1[] = {}; |
107 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
108 | ||
9bf2650b CH |
109 | GlobalProperty pc_compat_4_0[] = {}; |
110 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
111 | ||
abd93cc7 | 112 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 113 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
114 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
115 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
116 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
117 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 118 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
119 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
120 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
121 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
122 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
123 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
124 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
125 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
126 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
127 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
128 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
129 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
130 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
131 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 132 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 133 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
134 | }; |
135 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
136 | ||
ddb3235d | 137 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
138 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
139 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
140 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
141 | }; |
142 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
143 | ||
0d47310b | 144 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
145 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
146 | { TYPE_X86_CPU, "topoext", "off" }, | |
147 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
148 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
149 | }; |
150 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
151 | ||
43df70a9 | 152 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
153 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
154 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
155 | }; |
156 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
157 | ||
503224f4 | 158 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
159 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
160 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
161 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
162 | }; |
163 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
164 | ||
3e803152 | 165 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 166 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
167 | }; |
168 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
169 | ||
edc24ccd | 170 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
171 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
172 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
173 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
174 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
175 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
176 | }; |
177 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
178 | ||
5a995064 | 179 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
180 | { TYPE_X86_CPU, "l3-cache", "off" }, |
181 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
182 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
183 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
184 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
185 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
186 | }; |
187 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
188 | ||
ff8f261f | 189 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
190 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
191 | { "vmxnet3", "romfile", "" }, | |
192 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
193 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
194 | }; |
195 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
196 | ||
fe759610 MAL |
197 | GlobalProperty pc_compat_2_5[] = {}; |
198 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
199 | ||
2f99b9c2 MAL |
200 | GlobalProperty pc_compat_2_4[] = { |
201 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
202 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
203 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
204 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
205 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
206 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
207 | { TYPE_X86_CPU, "check", "off" }, | |
208 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
209 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
210 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
211 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
212 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
213 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
214 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
215 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
216 | }; |
217 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
218 | ||
8995dd90 MAL |
219 | GlobalProperty pc_compat_2_3[] = { |
220 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
221 | { TYPE_X86_CPU, "arat", "off" }, |
222 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
223 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
224 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
225 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
226 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
227 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
228 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
229 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
230 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
231 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
232 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
233 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
234 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
235 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
236 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
237 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
238 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
239 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
240 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
241 | }; |
242 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
243 | ||
1c30044e MAL |
244 | GlobalProperty pc_compat_2_2[] = { |
245 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
246 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
247 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
248 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
249 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
250 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
251 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
252 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
253 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
254 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
255 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
256 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
257 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
258 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
259 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
260 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
261 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
262 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
263 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
264 | }; |
265 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
266 | ||
c4fc5695 MAL |
267 | GlobalProperty pc_compat_2_1[] = { |
268 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
269 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
270 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
271 | }; |
272 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
273 | ||
a310e653 MAL |
274 | GlobalProperty pc_compat_2_0[] = { |
275 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
276 | { "virtio-scsi-pci", "any_layout", "off" }, |
277 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
278 | { "apic", "version", "0x11" }, | |
279 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
280 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
281 | { "pci-serial", "prog_if", "0" }, | |
282 | { "pci-serial-2x", "prog_if", "0" }, | |
283 | { "pci-serial-4x", "prog_if", "0" }, | |
284 | { "virtio-net-pci", "guest_announce", "off" }, | |
285 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
286 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
287 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
a310e653 MAL |
288 | }; |
289 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
290 | ||
291 | GlobalProperty pc_compat_1_7[] = { | |
292 | PC_CPU_MODEL_IDS("1.7.0") | |
6c36bddf EH |
293 | { TYPE_USB_DEVICE, "msos-desc", "no" }, |
294 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
295 | { "hpet", HPET_INTCAP, "4" }, | |
a310e653 MAL |
296 | }; |
297 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
298 | ||
299 | GlobalProperty pc_compat_1_6[] = { | |
300 | PC_CPU_MODEL_IDS("1.6.0") | |
6c36bddf EH |
301 | { "e1000", "mitigation", "off" }, |
302 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
303 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
304 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
305 | { "q35-pcihost", "short_root_bus", "1" }, | |
a310e653 MAL |
306 | }; |
307 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
308 | ||
309 | GlobalProperty pc_compat_1_5[] = { | |
310 | PC_CPU_MODEL_IDS("1.5.0") | |
6c36bddf EH |
311 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, |
312 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
313 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
314 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
315 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
316 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
317 | { "virtio-net-pci", "any_layout", "off" }, | |
318 | { TYPE_X86_CPU, "pmu", "on" }, | |
319 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
320 | { "q35-pcihost", "short_root_bus", "0" }, | |
a310e653 MAL |
321 | }; |
322 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
323 | ||
324 | GlobalProperty pc_compat_1_4[] = { | |
325 | PC_CPU_MODEL_IDS("1.4.0") | |
6c36bddf EH |
326 | { "scsi-hd", "discard_granularity", "0" }, |
327 | { "scsi-cd", "discard_granularity", "0" }, | |
328 | { "scsi-disk", "discard_granularity", "0" }, | |
329 | { "ide-hd", "discard_granularity", "0" }, | |
330 | { "ide-cd", "discard_granularity", "0" }, | |
331 | { "ide-drive", "discard_granularity", "0" }, | |
332 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
333 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
334 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
335 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
336 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
337 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
338 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
339 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
340 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
341 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
342 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
343 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
a310e653 MAL |
344 | }; |
345 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
346 | ||
b881fbe9 | 347 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 348 | { |
b881fbe9 | 349 | GSIState *s = opaque; |
1452411b | 350 | |
b881fbe9 JK |
351 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
352 | if (n < ISA_NUM_IRQS) { | |
353 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 354 | } |
b881fbe9 | 355 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 356 | } |
1452411b | 357 | |
417258f1 PMD |
358 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
359 | { | |
360 | GSIState *s; | |
361 | ||
362 | s = g_new0(GSIState, 1); | |
363 | if (kvm_ioapic_in_kernel()) { | |
364 | kvm_pc_setup_irq_routing(pci_enabled); | |
365 | *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS); | |
366 | } else { | |
367 | *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); | |
368 | } | |
369 | ||
370 | return s; | |
371 | } | |
372 | ||
258711c6 JG |
373 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
374 | unsigned size) | |
80cabfad FB |
375 | { |
376 | } | |
377 | ||
c02e1eac JG |
378 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
379 | { | |
a6fc23e5 | 380 | return 0xffffffffffffffffULL; |
c02e1eac JG |
381 | } |
382 | ||
f929aad6 | 383 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 384 | static qemu_irq ferr_irq; |
8e78eb28 IY |
385 | |
386 | void pc_register_ferr_irq(qemu_irq irq) | |
387 | { | |
388 | ferr_irq = irq; | |
389 | } | |
390 | ||
f929aad6 FB |
391 | /* XXX: add IGNNE support */ |
392 | void cpu_set_ferr(CPUX86State *s) | |
393 | { | |
d537cf6c | 394 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
395 | } |
396 | ||
258711c6 JG |
397 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
398 | unsigned size) | |
f929aad6 | 399 | { |
d537cf6c | 400 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
401 | } |
402 | ||
c02e1eac JG |
403 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
404 | { | |
a6fc23e5 | 405 | return 0xffffffffffffffffULL; |
c02e1eac JG |
406 | } |
407 | ||
28ab0e2e | 408 | /* TSC handling */ |
28ab0e2e FB |
409 | uint64_t cpu_get_tsc(CPUX86State *env) |
410 | { | |
4a1418e0 | 411 | return cpu_get_ticks(); |
28ab0e2e FB |
412 | } |
413 | ||
3de388f6 | 414 | /* IRQ handling */ |
4a8fa5dc | 415 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 416 | { |
6aa9e42f | 417 | X86CPU *cpu = env_archcpu(env); |
3de388f6 FB |
418 | int intno; |
419 | ||
bb93e099 WL |
420 | if (!kvm_irqchip_in_kernel()) { |
421 | intno = apic_get_interrupt(cpu->apic_state); | |
422 | if (intno >= 0) { | |
423 | return intno; | |
424 | } | |
425 | /* read the irq from the PIC */ | |
426 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
427 | return -1; | |
428 | } | |
cf6d64bf | 429 | } |
0e21e12b | 430 | |
3de388f6 FB |
431 | intno = pic_read_irq(isa_pic); |
432 | return intno; | |
433 | } | |
434 | ||
d537cf6c | 435 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 436 | { |
182735ef AF |
437 | CPUState *cs = first_cpu; |
438 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 439 | |
471fd342 | 440 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 441 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 442 | CPU_FOREACH(cs) { |
182735ef | 443 | cpu = X86_CPU(cs); |
02e51483 CF |
444 | if (apic_accept_pic_intr(cpu->apic_state)) { |
445 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 446 | } |
d5529471 AJ |
447 | } |
448 | } else { | |
d8ed887b | 449 | if (level) { |
c3affe56 | 450 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
451 | } else { |
452 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
453 | } | |
a5b38b51 | 454 | } |
3de388f6 FB |
455 | } |
456 | ||
b0a21b53 FB |
457 | /* PC cmos mappings */ |
458 | ||
80cabfad FB |
459 | #define REG_EQUIPMENT_BYTE 0x14 |
460 | ||
bda05509 | 461 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
462 | { |
463 | int val; | |
464 | ||
465 | switch (fd0) { | |
2da44dd0 | 466 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
467 | /* 1.44 Mb 3"5 drive */ |
468 | val = 4; | |
469 | break; | |
2da44dd0 | 470 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
471 | /* 2.88 Mb 3"5 drive */ |
472 | val = 5; | |
473 | break; | |
2da44dd0 | 474 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
475 | /* 1.2 Mb 5"5 drive */ |
476 | val = 2; | |
477 | break; | |
2da44dd0 | 478 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
479 | default: |
480 | val = 0; | |
481 | break; | |
482 | } | |
483 | return val; | |
484 | } | |
485 | ||
9139046c MA |
486 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
487 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 488 | { |
ba6c2377 FB |
489 | rtc_set_memory(s, type_ofs, 47); |
490 | rtc_set_memory(s, info_ofs, cylinders); | |
491 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
492 | rtc_set_memory(s, info_ofs + 2, heads); | |
493 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
494 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
495 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
496 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
497 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
498 | rtc_set_memory(s, info_ofs + 8, sectors); | |
499 | } | |
500 | ||
6ac0e82d AZ |
501 | /* convert boot_device letter to something recognizable by the bios */ |
502 | static int boot_device2nibble(char boot_device) | |
503 | { | |
504 | switch(boot_device) { | |
505 | case 'a': | |
506 | case 'b': | |
507 | return 0x01; /* floppy boot */ | |
508 | case 'c': | |
509 | return 0x02; /* hard drive boot */ | |
510 | case 'd': | |
511 | return 0x03; /* CD-ROM boot */ | |
512 | case 'n': | |
513 | return 0x04; /* Network boot */ | |
514 | } | |
515 | return 0; | |
516 | } | |
517 | ||
ddcd5531 | 518 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
519 | { |
520 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
521 | int nbds, bds[3] = { 0, }; |
522 | int i; | |
523 | ||
524 | nbds = strlen(boot_device); | |
525 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
526 | error_setg(errp, "Too many boot devices for PC"); |
527 | return; | |
0ecdffbb AJ |
528 | } |
529 | for (i = 0; i < nbds; i++) { | |
530 | bds[i] = boot_device2nibble(boot_device[i]); | |
531 | if (bds[i] == 0) { | |
ddcd5531 GA |
532 | error_setg(errp, "Invalid boot device for PC: '%c'", |
533 | boot_device[i]); | |
534 | return; | |
0ecdffbb AJ |
535 | } |
536 | } | |
537 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 538 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
539 | } |
540 | ||
ddcd5531 | 541 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 542 | { |
ddcd5531 | 543 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
544 | } |
545 | ||
7444ca4e LE |
546 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
547 | { | |
548 | int val, nb, i; | |
2da44dd0 JS |
549 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
550 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
551 | |
552 | /* floppy type */ | |
553 | if (floppy) { | |
554 | for (i = 0; i < 2; i++) { | |
555 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
556 | } | |
557 | } | |
558 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
559 | cmos_get_fd_drive_type(fd_type[1]); | |
560 | rtc_set_memory(rtc_state, 0x10, val); | |
561 | ||
562 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
563 | nb = 0; | |
2da44dd0 | 564 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
565 | nb++; |
566 | } | |
2da44dd0 | 567 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
568 | nb++; |
569 | } | |
570 | switch (nb) { | |
571 | case 0: | |
572 | break; | |
573 | case 1: | |
574 | val |= 0x01; /* 1 drive, ready for boot */ | |
575 | break; | |
576 | case 2: | |
577 | val |= 0x41; /* 2 drives, ready for boot */ | |
578 | break; | |
579 | } | |
580 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
581 | } | |
582 | ||
c0897e0c MA |
583 | typedef struct pc_cmos_init_late_arg { |
584 | ISADevice *rtc_state; | |
9139046c | 585 | BusState *idebus[2]; |
c0897e0c MA |
586 | } pc_cmos_init_late_arg; |
587 | ||
b86f4613 LE |
588 | typedef struct check_fdc_state { |
589 | ISADevice *floppy; | |
590 | bool multiple; | |
591 | } CheckFdcState; | |
592 | ||
593 | static int check_fdc(Object *obj, void *opaque) | |
594 | { | |
595 | CheckFdcState *state = opaque; | |
596 | Object *fdc; | |
597 | uint32_t iobase; | |
598 | Error *local_err = NULL; | |
599 | ||
600 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
601 | if (!fdc) { | |
602 | return 0; | |
603 | } | |
604 | ||
1ea1572a | 605 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
606 | if (local_err || iobase != 0x3f0) { |
607 | error_free(local_err); | |
608 | return 0; | |
609 | } | |
610 | ||
611 | if (state->floppy) { | |
612 | state->multiple = true; | |
613 | } else { | |
614 | state->floppy = ISA_DEVICE(obj); | |
615 | } | |
616 | return 0; | |
617 | } | |
618 | ||
619 | static const char * const fdc_container_path[] = { | |
620 | "/unattached", "/peripheral", "/peripheral-anon" | |
621 | }; | |
622 | ||
424e4a87 RK |
623 | /* |
624 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
625 | * and ACPI objects. | |
626 | */ | |
627 | ISADevice *pc_find_fdc0(void) | |
628 | { | |
629 | int i; | |
630 | Object *container; | |
631 | CheckFdcState state = { 0 }; | |
632 | ||
633 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
634 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
635 | object_child_foreach(container, check_fdc, &state); | |
636 | } | |
637 | ||
638 | if (state.multiple) { | |
3dc6f869 AF |
639 | warn_report("multiple floppy disk controllers with " |
640 | "iobase=0x3f0 have been found"); | |
433672b0 | 641 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 642 | "your intent"); |
424e4a87 RK |
643 | } |
644 | ||
645 | return state.floppy; | |
646 | } | |
647 | ||
c0897e0c MA |
648 | static void pc_cmos_init_late(void *opaque) |
649 | { | |
650 | pc_cmos_init_late_arg *arg = opaque; | |
651 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
652 | int16_t cylinders; |
653 | int8_t heads, sectors; | |
c0897e0c | 654 | int val; |
2adc99b2 | 655 | int i, trans; |
c0897e0c | 656 | |
9139046c | 657 | val = 0; |
272f0428 CP |
658 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
659 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
660 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
661 | val |= 0xf0; | |
662 | } | |
272f0428 CP |
663 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
664 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
665 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
666 | val |= 0x0f; | |
667 | } | |
668 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
669 | |
670 | val = 0; | |
671 | for (i = 0; i < 4; i++) { | |
9139046c MA |
672 | /* NOTE: ide_get_geometry() returns the physical |
673 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
674 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
675 | geometry can be different if a translation is done. */ | |
272f0428 CP |
676 | if (arg->idebus[i / 2] && |
677 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 678 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
679 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
680 | assert((trans & ~3) == 0); | |
681 | val |= trans << (i * 2); | |
c0897e0c MA |
682 | } |
683 | } | |
684 | rtc_set_memory(s, 0x39, val); | |
685 | ||
424e4a87 | 686 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 687 | |
c0897e0c MA |
688 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
689 | } | |
690 | ||
23d30407 | 691 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 692 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 693 | ISADevice *s) |
80cabfad | 694 | { |
7444ca4e | 695 | int val; |
c0897e0c | 696 | static pc_cmos_init_late_arg arg; |
f0bb276b | 697 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b0a21b53 | 698 | |
b0a21b53 | 699 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
700 | |
701 | /* memory size */ | |
e89001f7 | 702 | /* base memory (first MiB) */ |
f0bb276b | 703 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
333190eb FB |
704 | rtc_set_memory(s, 0x15, val); |
705 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 706 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
707 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
708 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
709 | } else { |
710 | val = 0; | |
711 | } | |
80cabfad FB |
712 | if (val > 65535) |
713 | val = 65535; | |
b0a21b53 FB |
714 | rtc_set_memory(s, 0x17, val); |
715 | rtc_set_memory(s, 0x18, val >> 8); | |
716 | rtc_set_memory(s, 0x30, val); | |
717 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 718 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
719 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
720 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 721 | } else { |
9da98861 | 722 | val = 0; |
e89001f7 | 723 | } |
80cabfad FB |
724 | if (val > 65535) |
725 | val = 65535; | |
b0a21b53 FB |
726 | rtc_set_memory(s, 0x34, val); |
727 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 728 | /* memory above 4GiB */ |
f0bb276b | 729 | val = x86ms->above_4g_mem_size / 65536; |
e89001f7 MA |
730 | rtc_set_memory(s, 0x5b, val); |
731 | rtc_set_memory(s, 0x5c, val >> 8); | |
732 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 733 | |
23d30407 | 734 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 735 | TYPE_ISA_DEVICE, |
f0bb276b | 736 | (Object **)&x86ms->rtc, |
2d996150 | 737 | object_property_allow_set_link, |
265b578c | 738 | OBJ_PROP_LINK_STRONG, &error_abort); |
23d30407 | 739 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 740 | "rtc_state", &error_abort); |
298e01b6 | 741 | |
007b0657 | 742 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 743 | |
b0a21b53 | 744 | val = 0; |
b0a21b53 FB |
745 | val |= 0x02; /* FPU is there */ |
746 | val |= 0x04; /* PS/2 mouse installed */ | |
747 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
748 | ||
b86f4613 | 749 | /* hard drives and FDC */ |
c0897e0c | 750 | arg.rtc_state = s; |
9139046c MA |
751 | arg.idebus[0] = idebus0; |
752 | arg.idebus[1] = idebus1; | |
c0897e0c | 753 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
754 | } |
755 | ||
a0881c64 AF |
756 | #define TYPE_PORT92 "port92" |
757 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
758 | ||
4b78a802 BS |
759 | /* port 92 stuff: could be split off */ |
760 | typedef struct Port92State { | |
a0881c64 AF |
761 | ISADevice parent_obj; |
762 | ||
23af670e | 763 | MemoryRegion io; |
4b78a802 | 764 | uint8_t outport; |
d812b3d6 | 765 | qemu_irq a20_out; |
4b78a802 BS |
766 | } Port92State; |
767 | ||
93ef4192 AG |
768 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
769 | unsigned size) | |
4b78a802 BS |
770 | { |
771 | Port92State *s = opaque; | |
4700a316 | 772 | int oldval = s->outport; |
4b78a802 | 773 | |
c5539cb4 | 774 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 775 | s->outport = val; |
d812b3d6 | 776 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 777 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 778 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
779 | } |
780 | } | |
781 | ||
93ef4192 AG |
782 | static uint64_t port92_read(void *opaque, hwaddr addr, |
783 | unsigned size) | |
4b78a802 BS |
784 | { |
785 | Port92State *s = opaque; | |
786 | uint32_t ret; | |
787 | ||
788 | ret = s->outport; | |
789 | DPRINTF("port92: read 0x%02x\n", ret); | |
790 | return ret; | |
791 | } | |
792 | ||
d80fe99d | 793 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 794 | { |
d80fe99d | 795 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
796 | } |
797 | ||
798 | static const VMStateDescription vmstate_port92_isa = { | |
799 | .name = "port92", | |
800 | .version_id = 1, | |
801 | .minimum_version_id = 1, | |
d49805ae | 802 | .fields = (VMStateField[]) { |
4b78a802 BS |
803 | VMSTATE_UINT8(outport, Port92State), |
804 | VMSTATE_END_OF_LIST() | |
805 | } | |
806 | }; | |
807 | ||
808 | static void port92_reset(DeviceState *d) | |
809 | { | |
a0881c64 | 810 | Port92State *s = PORT92(d); |
4b78a802 BS |
811 | |
812 | s->outport &= ~1; | |
813 | } | |
814 | ||
23af670e | 815 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
816 | .read = port92_read, |
817 | .write = port92_write, | |
818 | .impl = { | |
819 | .min_access_size = 1, | |
820 | .max_access_size = 1, | |
821 | }, | |
822 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
823 | }; |
824 | ||
db895a1e | 825 | static void port92_initfn(Object *obj) |
4b78a802 | 826 | { |
db895a1e | 827 | Port92State *s = PORT92(obj); |
4b78a802 | 828 | |
1437c94b | 829 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 830 | |
4b78a802 | 831 | s->outport = 0; |
d812b3d6 EV |
832 | |
833 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
834 | } |
835 | ||
836 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
837 | { | |
838 | ISADevice *isadev = ISA_DEVICE(dev); | |
839 | Port92State *s = PORT92(dev); | |
840 | ||
841 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
842 | } |
843 | ||
8f04ee08 AL |
844 | static void port92_class_initfn(ObjectClass *klass, void *data) |
845 | { | |
39bffca2 | 846 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 847 | |
db895a1e | 848 | dc->realize = port92_realizefn; |
39bffca2 AL |
849 | dc->reset = port92_reset; |
850 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
851 | /* |
852 | * Reason: unlike ordinary ISA devices, this one needs additional | |
853 | * wiring: its A20 output line needs to be wired up by | |
854 | * port92_init(). | |
855 | */ | |
e90f2a8c | 856 | dc->user_creatable = false; |
8f04ee08 AL |
857 | } |
858 | ||
8c43a6f0 | 859 | static const TypeInfo port92_info = { |
a0881c64 | 860 | .name = TYPE_PORT92, |
39bffca2 AL |
861 | .parent = TYPE_ISA_DEVICE, |
862 | .instance_size = sizeof(Port92State), | |
db895a1e | 863 | .instance_init = port92_initfn, |
39bffca2 | 864 | .class_init = port92_class_initfn, |
4b78a802 BS |
865 | }; |
866 | ||
83f7d43a | 867 | static void port92_register_types(void) |
4b78a802 | 868 | { |
39bffca2 | 869 | type_register_static(&port92_info); |
4b78a802 | 870 | } |
83f7d43a AF |
871 | |
872 | type_init(port92_register_types) | |
4b78a802 | 873 | |
956a3e6b | 874 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 875 | { |
cc36a7a2 | 876 | X86CPU *cpu = opaque; |
e1a23744 | 877 | |
956a3e6b | 878 | /* XXX: send to all CPUs ? */ |
4b78a802 | 879 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 880 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
881 | } |
882 | ||
b41a2cd1 FB |
883 | #define NE2000_NB_MAX 6 |
884 | ||
675d6f82 BS |
885 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
886 | 0x280, 0x380 }; | |
887 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 888 | |
48a18b3c | 889 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
890 | { |
891 | static int nb_ne2k = 0; | |
892 | ||
893 | if (nb_ne2k == NE2000_NB_MAX) | |
894 | return; | |
48a18b3c | 895 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 896 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
897 | nb_ne2k++; |
898 | } | |
899 | ||
92a16d7a | 900 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 901 | { |
4917cf44 AF |
902 | if (current_cpu) { |
903 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 904 | return cpu->apic_state; |
0e26b7b8 BS |
905 | } else { |
906 | return NULL; | |
907 | } | |
908 | } | |
909 | ||
845773ab | 910 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 911 | { |
c3affe56 | 912 | X86CPU *cpu = opaque; |
53b67b30 BS |
913 | |
914 | if (level) { | |
c3affe56 | 915 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
916 | } |
917 | } | |
918 | ||
6f479566 LX |
919 | /* |
920 | * This function is very similar to smp_parse() | |
921 | * in hw/core/machine.c but includes CPU die support. | |
922 | */ | |
923 | void pc_smp_parse(MachineState *ms, QemuOpts *opts) | |
924 | { | |
f0bb276b | 925 | X86MachineState *x86ms = X86_MACHINE(ms); |
1b458422 | 926 | |
6f479566 LX |
927 | if (opts) { |
928 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
929 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
1b458422 | 930 | unsigned dies = qemu_opt_get_number(opts, "dies", 1); |
6f479566 LX |
931 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); |
932 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
933 | ||
934 | /* compute missing values, prefer sockets over cores over threads */ | |
935 | if (cpus == 0 || sockets == 0) { | |
936 | cores = cores > 0 ? cores : 1; | |
937 | threads = threads > 0 ? threads : 1; | |
938 | if (cpus == 0) { | |
939 | sockets = sockets > 0 ? sockets : 1; | |
1b458422 | 940 | cpus = cores * threads * dies * sockets; |
6f479566 LX |
941 | } else { |
942 | ms->smp.max_cpus = | |
943 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1b458422 | 944 | sockets = ms->smp.max_cpus / (cores * threads * dies); |
6f479566 LX |
945 | } |
946 | } else if (cores == 0) { | |
947 | threads = threads > 0 ? threads : 1; | |
1b458422 | 948 | cores = cpus / (sockets * dies * threads); |
6f479566 LX |
949 | cores = cores > 0 ? cores : 1; |
950 | } else if (threads == 0) { | |
1b458422 | 951 | threads = cpus / (cores * dies * sockets); |
6f479566 | 952 | threads = threads > 0 ? threads : 1; |
1b458422 | 953 | } else if (sockets * dies * cores * threads < cpus) { |
6f479566 | 954 | error_report("cpu topology: " |
1b458422 | 955 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " |
6f479566 | 956 | "smp_cpus (%u)", |
1b458422 | 957 | sockets, dies, cores, threads, cpus); |
6f479566 LX |
958 | exit(1); |
959 | } | |
960 | ||
961 | ms->smp.max_cpus = | |
962 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
963 | ||
964 | if (ms->smp.max_cpus < cpus) { | |
965 | error_report("maxcpus must be equal to or greater than smp"); | |
966 | exit(1); | |
967 | } | |
968 | ||
1b458422 | 969 | if (sockets * dies * cores * threads > ms->smp.max_cpus) { |
6f479566 | 970 | error_report("cpu topology: " |
1b458422 | 971 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " |
6f479566 | 972 | "maxcpus (%u)", |
1b458422 | 973 | sockets, dies, cores, threads, |
6f479566 LX |
974 | ms->smp.max_cpus); |
975 | exit(1); | |
976 | } | |
977 | ||
1b458422 | 978 | if (sockets * dies * cores * threads != ms->smp.max_cpus) { |
6f479566 | 979 | warn_report("Invalid CPU topology deprecated: " |
1b458422 | 980 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " |
6f479566 | 981 | "!= maxcpus (%u)", |
1b458422 | 982 | sockets, dies, cores, threads, |
6f479566 LX |
983 | ms->smp.max_cpus); |
984 | } | |
985 | ||
986 | ms->smp.cpus = cpus; | |
987 | ms->smp.cores = cores; | |
988 | ms->smp.threads = threads; | |
f0bb276b | 989 | x86ms->smp_dies = dies; |
6f479566 LX |
990 | } |
991 | ||
992 | if (ms->smp.cpus > 1) { | |
993 | Error *blocker = NULL; | |
994 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
995 | replay_add_blocker(blocker); | |
996 | } | |
997 | } | |
998 | ||
a0628599 | 999 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) |
c649983b | 1000 | { |
703a548a SL |
1001 | X86MachineState *x86ms = X86_MACHINE(ms); |
1002 | int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); | |
0e3bd562 | 1003 | Error *local_err = NULL; |
c649983b | 1004 | |
8de433cb IM |
1005 | if (id < 0) { |
1006 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1007 | return; | |
1008 | } | |
1009 | ||
5ff020b7 EH |
1010 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1011 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1012 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1013 | id, apic_id); | |
1014 | return; | |
1015 | } | |
1016 | ||
703a548a SL |
1017 | |
1018 | x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); | |
0e3bd562 AF |
1019 | if (local_err) { |
1020 | error_propagate(errp, local_err); | |
1021 | return; | |
1022 | } | |
c649983b IM |
1023 | } |
1024 | ||
e3cadac0 IM |
1025 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1026 | { | |
1027 | if (cpus_count > 0xff) { | |
1028 | /* If the number of CPUs can't be represented in 8 bits, the | |
1029 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1030 | * to make old BIOSes fail more predictably. | |
1031 | */ | |
1032 | rtc_set_memory(rtc, 0x5f, 0); | |
1033 | } else { | |
1034 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1035 | } | |
1036 | } | |
1037 | ||
3459a625 | 1038 | static |
9ebeed0c | 1039 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1040 | { |
9ebeed0c EH |
1041 | PCMachineState *pcms = container_of(notifier, |
1042 | PCMachineState, machine_done); | |
f0bb276b | 1043 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9ebeed0c | 1044 | PCIBus *bus = pcms->bus; |
2118196b | 1045 | |
ba157b69 | 1046 | /* set the number of CPUs */ |
f0bb276b | 1047 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 1048 | |
2118196b MA |
1049 | if (bus) { |
1050 | int extra_hosts = 0; | |
1051 | ||
1052 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1053 | /* look for expander root buses */ | |
1054 | if (pci_bus_is_root(bus)) { | |
1055 | extra_hosts++; | |
1056 | } | |
1057 | } | |
f0bb276b | 1058 | if (extra_hosts && x86ms->fw_cfg) { |
2118196b MA |
1059 | uint64_t *val = g_malloc(sizeof(*val)); |
1060 | *val = cpu_to_le64(extra_hosts); | |
f0bb276b | 1061 | fw_cfg_add_file(x86ms->fw_cfg, |
2118196b MA |
1062 | "etc/extra-pci-roots", val, sizeof(*val)); |
1063 | } | |
1064 | } | |
1065 | ||
bb292f5a | 1066 | acpi_setup(); |
f0bb276b PB |
1067 | if (x86ms->fw_cfg) { |
1068 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
1069 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 1070 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 1071 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 1072 | } |
60c5e104 | 1073 | |
f0bb276b | 1074 | if (x86ms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
1075 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
1076 | ||
a924b3d8 | 1077 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || |
60c5e104 IM |
1078 | iommu->intr_eim != ON_OFF_AUTO_ON) { |
1079 | error_report("current -smp configuration requires " | |
1080 | "Extended Interrupt Mode enabled. " | |
1081 | "You can add an IOMMU using: " | |
1082 | "-device intel-iommu,intremap=on,eim=on"); | |
1083 | exit(EXIT_FAILURE); | |
1084 | } | |
1085 | } | |
3459a625 MT |
1086 | } |
1087 | ||
e4e8ba04 | 1088 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1089 | { |
1f3aba37 | 1090 | int i; |
aa570207 | 1091 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1092 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 1093 | |
f0bb276b | 1094 | x86ms->apic_xrupt_override = kvm_allows_irq0_override(); |
aa570207 | 1095 | pcms->numa_nodes = ms->numa_state->num_nodes; |
dd4c2f01 EH |
1096 | pcms->node_mem = g_malloc0(pcms->numa_nodes * |
1097 | sizeof *pcms->node_mem); | |
aa570207 | 1098 | for (i = 0; i < ms->numa_state->num_nodes; i++) { |
7e721e7b | 1099 | pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; |
8c85901e WG |
1100 | } |
1101 | ||
9ebeed0c EH |
1102 | pcms->machine_done.notify = pc_machine_done; |
1103 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1104 | } |
1105 | ||
83d08f26 MT |
1106 | /* setup pci memory address space mapping into system address space */ |
1107 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1108 | MemoryRegion *pci_address_space) | |
39848901 | 1109 | { |
83d08f26 MT |
1110 | /* Set to lower priority than RAM */ |
1111 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1112 | pci_address_space, -1); | |
39848901 IM |
1113 | } |
1114 | ||
7bc35e0f | 1115 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1116 | { |
1117 | int i; | |
1118 | FWCfgState *fw_cfg; | |
703a548a | 1119 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1120 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 1121 | |
df1f79fd | 1122 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1123 | |
305ae888 | 1124 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 1125 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
1126 | rom_set_fw(fw_cfg); |
1127 | ||
703a548a SL |
1128 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1129 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
b33a5bbf CL |
1130 | for (i = 0; i < nb_option_roms; i++) { |
1131 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1132 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 1133 | !strcmp(option_rom[i].name, "pvh.bin") || |
b33a5bbf CL |
1134 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1135 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1136 | } | |
f0bb276b | 1137 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1138 | } |
1139 | ||
5934e216 EH |
1140 | void pc_memory_init(PCMachineState *pcms, |
1141 | MemoryRegion *system_memory, | |
1142 | MemoryRegion *rom_memory, | |
1143 | MemoryRegion **ram_memory) | |
80cabfad | 1144 | { |
cbc5b5f3 JJ |
1145 | int linux_boot, i; |
1146 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1147 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1148 | FWCfgState *fw_cfg; |
62b160c0 | 1149 | MachineState *machine = MACHINE(pcms); |
264b4857 | 1150 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 1151 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1152 | X86MachineState *x86ms = X86_MACHINE(pcms); |
d592d303 | 1153 | |
f0bb276b PB |
1154 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
1155 | x86ms->above_4g_mem_size); | |
9521d42b PB |
1156 | |
1157 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1158 | |
00cb2a99 | 1159 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1160 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1161 | * with older qemus that used qemu_ram_alloc(). |
1162 | */ | |
7267c094 | 1163 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1164 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1165 | machine->ram_size); | |
ae0a5466 | 1166 | *ram_memory = ram; |
7267c094 | 1167 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1168 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
f0bb276b | 1169 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 1170 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
1171 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
1172 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 1173 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1174 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
f0bb276b PB |
1175 | x86ms->below_4g_mem_size, |
1176 | x86ms->above_4g_mem_size); | |
00cb2a99 AK |
1177 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1178 | ram_above_4g); | |
f0bb276b | 1179 | e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1180 | } |
82b36dc3 | 1181 | |
bb292f5a | 1182 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1183 | (machine->ram_slots || |
9521d42b | 1184 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1185 | |
1186 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1187 | mc->name); | |
1188 | exit(EXIT_FAILURE); | |
1189 | } | |
1190 | ||
b0c14ec4 DH |
1191 | /* always allocate the device memory information */ |
1192 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1193 | ||
f2ffbe2b | 1194 | /* initialize device memory address space */ |
bb292f5a | 1195 | if (pcmc->has_reserved_memory && |
9521d42b | 1196 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 1197 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 1198 | |
a0cc8856 IM |
1199 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1200 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1201 | machine->ram_slots); | |
1202 | exit(EXIT_FAILURE); | |
1203 | } | |
1204 | ||
f2c38522 PK |
1205 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1206 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1207 | error_report("maximum memory size must by aligned to multiple of " | |
1208 | "%d bytes", TARGET_PAGE_SIZE); | |
1209 | exit(EXIT_FAILURE); | |
1210 | } | |
1211 | ||
b0c14ec4 | 1212 | machine->device_memory->base = |
f0bb276b | 1213 | ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); |
619d11e4 | 1214 | |
16a9e8a5 | 1215 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 1216 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 1217 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
1218 | } |
1219 | ||
f2ffbe2b DH |
1220 | if ((machine->device_memory->base + device_mem_size) < |
1221 | device_mem_size) { | |
619d11e4 IM |
1222 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1223 | machine->maxram_size); | |
1224 | exit(EXIT_FAILURE); | |
1225 | } | |
1226 | ||
b0c14ec4 | 1227 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 1228 | "device-memory", device_mem_size); |
b0c14ec4 DH |
1229 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
1230 | &machine->device_memory->mr); | |
619d11e4 | 1231 | } |
cbc5b5f3 JJ |
1232 | |
1233 | /* Initialize PC system firmware */ | |
5e640a9e | 1234 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 1235 | |
7267c094 | 1236 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1237 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1238 | &error_fatal); |
208fa0e4 IM |
1239 | if (pcmc->pci_enabled) { |
1240 | memory_region_set_readonly(option_rom_mr, true); | |
1241 | } | |
4463aee6 | 1242 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1243 | PC_ROM_MIN_VGA, |
1244 | option_rom_mr, | |
1245 | 1); | |
f753ff16 | 1246 | |
bd802bd9 | 1247 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 1248 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 1249 | |
8832cb80 | 1250 | rom_set_fw(fw_cfg); |
1d108d97 | 1251 | |
b0c14ec4 | 1252 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 1253 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 1254 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 1255 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1256 | |
1257 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1258 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1259 | } |
d471bf3e | 1260 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1261 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1262 | } | |
1263 | ||
f753ff16 | 1264 | if (linux_boot) { |
703a548a SL |
1265 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1266 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
f753ff16 PB |
1267 | } |
1268 | ||
1269 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1270 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1271 | } |
f0bb276b | 1272 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
1273 | |
1274 | /* Init default IOAPIC address space */ | |
f0bb276b | 1275 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
1276 | |
1277 | /* Init ACPI memory hotplug IO base address */ | |
1278 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
1279 | } |
1280 | ||
9fa99d25 MA |
1281 | /* |
1282 | * The 64bit pci hole starts after "above 4G RAM" and | |
1283 | * potentially the space reserved for memory hotplug. | |
1284 | */ | |
1285 | uint64_t pc_pci_hole64_start(void) | |
1286 | { | |
1287 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1288 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1289 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1290 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9fa99d25 MA |
1291 | uint64_t hole64_start = 0; |
1292 | ||
b0c14ec4 DH |
1293 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
1294 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 1295 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 1296 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 MA |
1297 | } |
1298 | } else { | |
f0bb276b | 1299 | hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; |
9fa99d25 MA |
1300 | } |
1301 | ||
d471bf3e | 1302 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1303 | } |
1304 | ||
0b0cc076 | 1305 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1306 | { |
0b0cc076 | 1307 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1308 | } |
1309 | ||
48a18b3c | 1310 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1311 | { |
ad6d45fa AL |
1312 | DeviceState *dev = NULL; |
1313 | ||
bab47d9a | 1314 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1315 | if (pci_bus) { |
1316 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1317 | dev = pcidev ? &pcidev->qdev : NULL; | |
1318 | } else if (isa_bus) { | |
1319 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1320 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1321 | } |
bab47d9a | 1322 | rom_reset_order_override(); |
ad6d45fa | 1323 | return dev; |
765d7908 IY |
1324 | } |
1325 | ||
258711c6 JG |
1326 | static const MemoryRegionOps ioport80_io_ops = { |
1327 | .write = ioport80_write, | |
c02e1eac | 1328 | .read = ioport80_read, |
258711c6 JG |
1329 | .endianness = DEVICE_NATIVE_ENDIAN, |
1330 | .impl = { | |
1331 | .min_access_size = 1, | |
1332 | .max_access_size = 1, | |
1333 | }, | |
1334 | }; | |
1335 | ||
1336 | static const MemoryRegionOps ioportF0_io_ops = { | |
1337 | .write = ioportF0_write, | |
c02e1eac | 1338 | .read = ioportF0_read, |
258711c6 JG |
1339 | .endianness = DEVICE_NATIVE_ENDIAN, |
1340 | .impl = { | |
1341 | .min_access_size = 1, | |
1342 | .max_access_size = 1, | |
1343 | }, | |
1344 | }; | |
1345 | ||
ac64273c PMD |
1346 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1347 | { | |
1348 | int i; | |
1349 | DriveInfo *fd[MAX_FD]; | |
1350 | qemu_irq *a20_line; | |
1351 | ISADevice *i8042, *port92, *vmmouse; | |
1352 | ||
def337ff | 1353 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1354 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1355 | ||
1356 | for (i = 0; i < MAX_FD; i++) { | |
1357 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1358 | create_fdctrl |= !!fd[i]; | |
1359 | } | |
1360 | if (create_fdctrl) { | |
1361 | fdctrl_init_isa(isa_bus, fd); | |
1362 | } | |
1363 | ||
1364 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1365 | if (!no_vmport) { | |
1366 | vmport_init(isa_bus); | |
1367 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1368 | } else { | |
1369 | vmmouse = NULL; | |
1370 | } | |
1371 | if (vmmouse) { | |
1372 | DeviceState *dev = DEVICE(vmmouse); | |
1373 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1374 | qdev_init_nofail(dev); | |
1375 | } | |
1376 | port92 = isa_create_simple(isa_bus, "port92"); | |
1377 | ||
1378 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1379 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1380 | port92_init(port92, a20_line[1]); | |
1381 | g_free(a20_line); | |
1382 | } | |
1383 | ||
48a18b3c | 1384 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1385 | ISADevice **rtc_state, |
fd53c87c | 1386 | bool create_fdctrl, |
7a10ef51 | 1387 | bool no_vmport, |
feddd2fd | 1388 | bool has_pit, |
3a87d009 | 1389 | uint32_t hpet_irqs) |
ffe513da IY |
1390 | { |
1391 | int i; | |
ce967e2f JK |
1392 | DeviceState *hpet = NULL; |
1393 | int pit_isa_irq = 0; | |
1394 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1395 | qemu_irq rtc_irq = NULL; |
ac64273c | 1396 | ISADevice *pit = NULL; |
258711c6 JG |
1397 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1398 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1399 | |
2c9b15ca | 1400 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1401 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1402 | |
2c9b15ca | 1403 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1404 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1405 | |
5d17c0d2 JK |
1406 | /* |
1407 | * Check if an HPET shall be created. | |
1408 | * | |
1409 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1410 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1411 | */ | |
1412 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1413 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1414 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1415 | if (hpet) { |
7a10ef51 LPF |
1416 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1417 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1418 | * IRQ8 and IRQ2. | |
1419 | */ | |
5d7fb0f2 | 1420 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1421 | HPET_INTCAP, NULL); |
1422 | if (!compat) { | |
1423 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1424 | } | |
1425 | qdev_init_nofail(hpet); | |
1426 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1427 | ||
b881fbe9 | 1428 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1429 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1430 | } |
ce967e2f JK |
1431 | pit_isa_irq = -1; |
1432 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1433 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1434 | } |
ffe513da | 1435 | } |
6c646a11 | 1436 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1437 | |
1438 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1439 | ||
feddd2fd | 1440 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1441 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1442 | pit = kvm_pit_init(isa_bus, 0x40); |
1443 | } else { | |
acf695ec | 1444 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1445 | } |
1446 | if (hpet) { | |
1447 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1448 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1449 | } |
1450 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1451 | } |
ffe513da | 1452 | |
55f613ac | 1453 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1454 | |
ac64273c PMD |
1455 | /* Super I/O */ |
1456 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
ffe513da IY |
1457 | } |
1458 | ||
4b9c264b | 1459 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1460 | { |
1461 | int i; | |
1462 | ||
bab47d9a | 1463 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1464 | for (i = 0; i < nb_nics; i++) { |
1465 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1466 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1467 | |
4b9c264b | 1468 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1469 | pc_init_ne2k_isa(isa_bus, nd); |
1470 | } else { | |
4b9c264b | 1471 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1472 | } |
1473 | } | |
bab47d9a | 1474 | rom_reset_order_override(); |
9011a1a7 IY |
1475 | } |
1476 | ||
4501d317 PMD |
1477 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1478 | { | |
1479 | qemu_irq *i8259; | |
1480 | ||
1481 | if (kvm_pic_in_kernel()) { | |
1482 | i8259 = kvm_i8259_init(isa_bus); | |
1483 | } else if (xen_enabled()) { | |
1484 | i8259 = xen_interrupt_controller_init(); | |
1485 | } else { | |
1486 | i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); | |
1487 | } | |
1488 | ||
1489 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1490 | i8259_irqs[i] = i8259[i]; | |
1491 | } | |
1492 | ||
1493 | g_free(i8259); | |
1494 | } | |
1495 | ||
a39e3564 JB |
1496 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) |
1497 | { | |
1498 | DeviceState *dev; | |
1499 | SysBusDevice *d; | |
1500 | unsigned int i; | |
1501 | ||
15eafc2e | 1502 | if (kvm_ioapic_in_kernel()) { |
34bec7a8 | 1503 | dev = qdev_create(NULL, TYPE_KVM_IOAPIC); |
a39e3564 | 1504 | } else { |
34bec7a8 | 1505 | dev = qdev_create(NULL, TYPE_IOAPIC); |
a39e3564 JB |
1506 | } |
1507 | if (parent_name) { | |
1508 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1509 | "ioapic", OBJECT(dev), NULL); | |
1510 | } | |
1511 | qdev_init_nofail(dev); | |
1356b98d | 1512 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1513 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1514 | |
1515 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1516 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1517 | } | |
1518 | } | |
d5747cac | 1519 | |
d468115b DH |
1520 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1521 | Error **errp) | |
1522 | { | |
1523 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
b0e62443 | 1524 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1525 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1526 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1527 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1528 | Error *local_err = NULL; |
d468115b DH |
1529 | |
1530 | /* | |
1531 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1532 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1533 | * addition to cover this case. | |
1534 | */ | |
1535 | if (!pcms->acpi_dev || !acpi_enabled) { | |
1536 | error_setg(errp, | |
1537 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1538 | return; | |
1539 | } | |
1540 | ||
f6a0d06b | 1541 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1542 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1543 | return; | |
1544 | } | |
8f1ffe5b | 1545 | |
ae909496 TH |
1546 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); |
1547 | if (local_err) { | |
1548 | error_propagate(errp, local_err); | |
1549 | return; | |
1550 | } | |
1551 | ||
fd3416f5 | 1552 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1553 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1554 | } |
1555 | ||
bb6e2f7a DH |
1556 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1557 | DeviceState *dev, Error **errp) | |
95bee274 IM |
1558 | { |
1559 | Error *local_err = NULL; | |
1560 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f6a0d06b | 1561 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1562 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1563 | |
fd3416f5 | 1564 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); |
43bbb49e | 1565 | if (local_err) { |
b8865591 IM |
1566 | goto out; |
1567 | } | |
1568 | ||
7f3cf2d6 | 1569 | if (is_nvdimm) { |
f6a0d06b | 1570 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1571 | } |
1572 | ||
473ac567 | 1573 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1574 | out: |
1575 | error_propagate(errp, local_err); | |
1576 | } | |
1577 | ||
bb6e2f7a DH |
1578 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1579 | DeviceState *dev, Error **errp) | |
64fec58e | 1580 | { |
64fec58e TC |
1581 | Error *local_err = NULL; |
1582 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1583 | ||
8cd91ace HZ |
1584 | /* |
1585 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1586 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1587 | * addition to cover this case. | |
1588 | */ | |
1589 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1590 | error_setg(&local_err, |
8cd91ace | 1591 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1592 | goto out; |
1593 | } | |
1594 | ||
b097cc52 XG |
1595 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1596 | error_setg(&local_err, | |
1597 | "nvdimm device hot unplug is not supported yet."); | |
1598 | goto out; | |
1599 | } | |
1600 | ||
473ac567 DH |
1601 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1602 | &local_err); | |
64fec58e TC |
1603 | out: |
1604 | error_propagate(errp, local_err); | |
1605 | } | |
1606 | ||
bb6e2f7a DH |
1607 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1608 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1609 | { |
1610 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f7d3e29d TC |
1611 | Error *local_err = NULL; |
1612 | ||
473ac567 | 1613 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
f7d3e29d TC |
1614 | if (local_err) { |
1615 | goto out; | |
1616 | } | |
1617 | ||
fd3416f5 | 1618 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
07578b0a | 1619 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
f7d3e29d TC |
1620 | out: |
1621 | error_propagate(errp, local_err); | |
1622 | } | |
1623 | ||
3811ef14 IM |
1624 | static int pc_apic_cmp(const void *a, const void *b) |
1625 | { | |
1626 | CPUArchId *apic_a = (CPUArchId *)a; | |
1627 | CPUArchId *apic_b = (CPUArchId *)b; | |
1628 | ||
1629 | return apic_a->arch_id - apic_b->arch_id; | |
1630 | } | |
1631 | ||
7baef5cf | 1632 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1633 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1634 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1635 | */ |
1ea69c0e | 1636 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1637 | { |
7baef5cf IM |
1638 | CPUArchId apic_id, *found_cpu; |
1639 | ||
1ea69c0e | 1640 | apic_id.arch_id = id; |
38690a1c IM |
1641 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1642 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1643 | pc_apic_cmp); |
1644 | if (found_cpu && idx) { | |
38690a1c | 1645 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1646 | } |
1647 | return found_cpu; | |
1648 | } | |
1649 | ||
5279569e GZ |
1650 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1651 | DeviceState *dev, Error **errp) | |
1652 | { | |
7baef5cf | 1653 | CPUArchId *found_cpu; |
5279569e | 1654 | Error *local_err = NULL; |
1ea69c0e | 1655 | X86CPU *cpu = X86_CPU(dev); |
5279569e | 1656 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1657 | X86MachineState *x86ms = X86_MACHINE(pcms); |
5279569e | 1658 | |
a44a49db | 1659 | if (pcms->acpi_dev) { |
473ac567 | 1660 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
a44a49db IM |
1661 | if (local_err) { |
1662 | goto out; | |
1663 | } | |
5279569e GZ |
1664 | } |
1665 | ||
e3cadac0 | 1666 | /* increment the number of CPUs */ |
f0bb276b PB |
1667 | x86ms->boot_cpus++; |
1668 | if (x86ms->rtc) { | |
1669 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); | |
26ef65be | 1670 | } |
f0bb276b PB |
1671 | if (x86ms->fw_cfg) { |
1672 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
2d996150 GZ |
1673 | } |
1674 | ||
1ea69c0e | 1675 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1676 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1677 | out: |
1678 | error_propagate(errp, local_err); | |
1679 | } | |
8872c25a IM |
1680 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1681 | DeviceState *dev, Error **errp) | |
1682 | { | |
73360e27 | 1683 | int idx = -1; |
8872c25a | 1684 | Error *local_err = NULL; |
1ea69c0e | 1685 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1686 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1687 | ||
75ba2ddb IM |
1688 | if (!pcms->acpi_dev) { |
1689 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
1690 | goto out; | |
1691 | } | |
1692 | ||
1ea69c0e | 1693 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1694 | assert(idx != -1); |
1695 | if (idx == 0) { | |
1696 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1697 | goto out; | |
1698 | } | |
1699 | ||
473ac567 DH |
1700 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1701 | &local_err); | |
8872c25a IM |
1702 | if (local_err) { |
1703 | goto out; | |
1704 | } | |
1705 | ||
1706 | out: | |
1707 | error_propagate(errp, local_err); | |
1708 | ||
1709 | } | |
1710 | ||
1711 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1712 | DeviceState *dev, Error **errp) | |
1713 | { | |
8fe6374e | 1714 | CPUArchId *found_cpu; |
8872c25a | 1715 | Error *local_err = NULL; |
1ea69c0e | 1716 | X86CPU *cpu = X86_CPU(dev); |
8872c25a | 1717 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1718 | X86MachineState *x86ms = X86_MACHINE(pcms); |
8872c25a | 1719 | |
473ac567 | 1720 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
8872c25a IM |
1721 | if (local_err) { |
1722 | goto out; | |
1723 | } | |
1724 | ||
1ea69c0e | 1725 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e | 1726 | found_cpu->cpu = NULL; |
07578b0a | 1727 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
8872c25a | 1728 | |
e3cadac0 | 1729 | /* decrement the number of CPUs */ |
f0bb276b | 1730 | x86ms->boot_cpus--; |
e3cadac0 | 1731 | /* Update the number of CPUs in CMOS */ |
f0bb276b PB |
1732 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
1733 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
8872c25a IM |
1734 | out: |
1735 | error_propagate(errp, local_err); | |
1736 | } | |
5279569e | 1737 | |
4ec60c76 IM |
1738 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1739 | DeviceState *dev, Error **errp) | |
1740 | { | |
1741 | int idx; | |
a15d2728 | 1742 | CPUState *cs; |
e8f7b83e | 1743 | CPUArchId *cpu_slot; |
d89c2b8b | 1744 | X86CPUTopoInfo topo; |
4ec60c76 | 1745 | X86CPU *cpu = X86_CPU(dev); |
cabea7dc | 1746 | CPUX86State *env = &cpu->env; |
6970c5ff | 1747 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 1748 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1749 | X86MachineState *x86ms = X86_MACHINE(pcms); |
0e11fc69 LX |
1750 | unsigned int smp_cores = ms->smp.cores; |
1751 | unsigned int smp_threads = ms->smp.threads; | |
4ec60c76 | 1752 | |
6970c5ff IM |
1753 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
1754 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
1755 | ms->cpu_type); | |
1756 | return; | |
1757 | } | |
1758 | ||
f0bb276b | 1759 | env->nr_dies = x86ms->smp_dies; |
cabea7dc | 1760 | |
c26ae610 LX |
1761 | /* |
1762 | * If APIC ID is not set, | |
1763 | * set it based on socket/die/core/thread properties. | |
1764 | */ | |
e8f7b83e | 1765 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { |
c26ae610 | 1766 | int max_socket = (ms->smp.max_cpus - 1) / |
f0bb276b | 1767 | smp_threads / smp_cores / x86ms->smp_dies; |
e8f7b83e | 1768 | |
fea374e7 EH |
1769 | /* |
1770 | * die-id was optional in QEMU 4.0 and older, so keep it optional | |
1771 | * if there's only one die per socket. | |
1772 | */ | |
f0bb276b | 1773 | if (cpu->die_id < 0 && x86ms->smp_dies == 1) { |
fea374e7 EH |
1774 | cpu->die_id = 0; |
1775 | } | |
1776 | ||
e8f7b83e IM |
1777 | if (cpu->socket_id < 0) { |
1778 | error_setg(errp, "CPU socket-id is not set"); | |
1779 | return; | |
1780 | } else if (cpu->socket_id > max_socket) { | |
1781 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1782 | cpu->socket_id, max_socket); | |
1783 | return; | |
23d9cff4 EH |
1784 | } |
1785 | if (cpu->die_id < 0) { | |
1786 | error_setg(errp, "CPU die-id is not set"); | |
1787 | return; | |
f0bb276b | 1788 | } else if (cpu->die_id > x86ms->smp_dies - 1) { |
176d2cda | 1789 | error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", |
f0bb276b | 1790 | cpu->die_id, x86ms->smp_dies - 1); |
176d2cda | 1791 | return; |
e8f7b83e IM |
1792 | } |
1793 | if (cpu->core_id < 0) { | |
1794 | error_setg(errp, "CPU core-id is not set"); | |
1795 | return; | |
1796 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1797 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1798 | cpu->core_id, smp_cores - 1); | |
1799 | return; | |
1800 | } | |
1801 | if (cpu->thread_id < 0) { | |
1802 | error_setg(errp, "CPU thread-id is not set"); | |
1803 | return; | |
1804 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1805 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1806 | cpu->thread_id, smp_threads - 1); | |
1807 | return; | |
1808 | } | |
1809 | ||
1810 | topo.pkg_id = cpu->socket_id; | |
176d2cda | 1811 | topo.die_id = cpu->die_id; |
e8f7b83e IM |
1812 | topo.core_id = cpu->core_id; |
1813 | topo.smt_id = cpu->thread_id; | |
f0bb276b | 1814 | cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, |
d65af288 | 1815 | smp_threads, &topo); |
e8f7b83e IM |
1816 | } |
1817 | ||
1ea69c0e | 1818 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1819 | if (!cpu_slot) { |
38690a1c IM |
1820 | MachineState *ms = MACHINE(pcms); |
1821 | ||
f0bb276b | 1822 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 LX |
1823 | smp_cores, smp_threads, &topo); |
1824 | error_setg(errp, | |
1825 | "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" | |
1826 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1827 | topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, | |
1828 | cpu->apic_id, ms->possible_cpus->len - 1); | |
4ec60c76 IM |
1829 | return; |
1830 | } | |
1831 | ||
1832 | if (cpu_slot->cpu) { | |
1833 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1834 | idx, cpu->apic_id); | |
1835 | return; | |
1836 | } | |
d89c2b8b IM |
1837 | |
1838 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1839 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1840 | */ |
1841 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1842 | * once -smp refactoring is complete and there will be CPU private | |
1843 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
f0bb276b | 1844 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 | 1845 | smp_cores, smp_threads, &topo); |
d89c2b8b IM |
1846 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { |
1847 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1848 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1849 | return; | |
1850 | } | |
1851 | cpu->socket_id = topo.pkg_id; | |
1852 | ||
176d2cda LX |
1853 | if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { |
1854 | error_setg(errp, "property die-id: %u doesn't match set apic-id:" | |
1855 | " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); | |
1856 | return; | |
1857 | } | |
1858 | cpu->die_id = topo.die_id; | |
1859 | ||
d89c2b8b IM |
1860 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { |
1861 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1862 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1863 | return; | |
1864 | } | |
1865 | cpu->core_id = topo.core_id; | |
1866 | ||
1867 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1868 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1869 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1870 | return; | |
1871 | } | |
1872 | cpu->thread_id = topo.smt_id; | |
a15d2728 | 1873 | |
2d384d7c VK |
1874 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && |
1875 | !kvm_hv_vpindex_settable()) { | |
e9688fab RK |
1876 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); |
1877 | return; | |
1878 | } | |
1879 | ||
a15d2728 IM |
1880 | cs = CPU(cpu); |
1881 | cs->cpu_index = idx; | |
93b2a8cb | 1882 | |
a0ceb640 | 1883 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
1884 | } |
1885 | ||
a0a49813 DH |
1886 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, |
1887 | DeviceState *dev, Error **errp) | |
1888 | { | |
1889 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1890 | Error *local_err = NULL; | |
1891 | ||
1892 | if (!hotplug_dev2) { | |
1893 | /* | |
1894 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
1895 | * order. This should never be the case on x86, however better add | |
1896 | * a safety net. | |
1897 | */ | |
1898 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
1899 | return; | |
1900 | } | |
1901 | /* | |
1902 | * First, see if we can plug this memory device at all. If that | |
1903 | * succeeds, branch of to the actual hotplug handler. | |
1904 | */ | |
1905 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1906 | &local_err); | |
1907 | if (!local_err) { | |
1908 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
1909 | } | |
1910 | error_propagate(errp, local_err); | |
1911 | } | |
1912 | ||
1913 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
1914 | DeviceState *dev, Error **errp) | |
1915 | { | |
1916 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1917 | Error *local_err = NULL; | |
1918 | ||
1919 | /* | |
1920 | * Plug the memory device first and then branch off to the actual | |
1921 | * hotplug handler. If that one fails, we can easily undo the memory | |
1922 | * device bits. | |
1923 | */ | |
1924 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1925 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
1926 | if (local_err) { | |
1927 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1928 | } | |
1929 | error_propagate(errp, local_err); | |
1930 | } | |
1931 | ||
1932 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
1933 | DeviceState *dev, Error **errp) | |
1934 | { | |
1935 | /* We don't support virtio pmem hot unplug */ | |
1936 | error_setg(errp, "virtio pmem device unplug not supported."); | |
1937 | } | |
1938 | ||
1939 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
1940 | DeviceState *dev, Error **errp) | |
1941 | { | |
1942 | /* We don't support virtio pmem hot unplug */ | |
1943 | } | |
1944 | ||
4ec60c76 IM |
1945 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1946 | DeviceState *dev, Error **errp) | |
1947 | { | |
d468115b DH |
1948 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1949 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1950 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
4ec60c76 | 1951 | pc_cpu_pre_plug(hotplug_dev, dev, errp); |
a0a49813 DH |
1952 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1953 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1954 | } |
1955 | } | |
1956 | ||
95bee274 IM |
1957 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1958 | DeviceState *dev, Error **errp) | |
1959 | { | |
1960 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1961 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e GZ |
1962 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1963 | pc_cpu_plug(hotplug_dev, dev, errp); | |
a0a49813 DH |
1964 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1965 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1966 | } |
1967 | } | |
1968 | ||
d9c5c5b8 TC |
1969 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1970 | DeviceState *dev, Error **errp) | |
1971 | { | |
64fec58e | 1972 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1973 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a IM |
1974 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1975 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1976 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1977 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
64fec58e TC |
1978 | } else { |
1979 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1980 | " type: %s", object_get_typename(OBJECT(dev))); | |
1981 | } | |
d9c5c5b8 TC |
1982 | } |
1983 | ||
232391c1 TC |
1984 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1985 | DeviceState *dev, Error **errp) | |
1986 | { | |
f7d3e29d | 1987 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1988 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a IM |
1989 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1990 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1991 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1992 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
f7d3e29d TC |
1993 | } else { |
1994 | error_setg(errp, "acpi: device unplug for not supported device" | |
1995 | " type: %s", object_get_typename(OBJECT(dev))); | |
1996 | } | |
232391c1 TC |
1997 | } |
1998 | ||
285816d7 | 1999 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
2000 | DeviceState *dev) |
2001 | { | |
5279569e | 2002 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 DH |
2003 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
2004 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
95bee274 IM |
2005 | return HOTPLUG_HANDLER(machine); |
2006 | } | |
2007 | ||
38aefb57 | 2008 | return NULL; |
95bee274 IM |
2009 | } |
2010 | ||
bf1e8939 | 2011 | static void |
f2ffbe2b DH |
2012 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
2013 | const char *name, void *opaque, | |
2014 | Error **errp) | |
bf1e8939 | 2015 | { |
b0c14ec4 | 2016 | MachineState *ms = MACHINE(obj); |
fc3b77e2 IM |
2017 | int64_t value = 0; |
2018 | ||
2019 | if (ms->device_memory) { | |
2020 | value = memory_region_size(&ms->device_memory->mr); | |
2021 | } | |
bf1e8939 | 2022 | |
51e72bc1 | 2023 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2024 | } |
2025 | ||
d7bce999 EB |
2026 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2027 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2028 | { |
2029 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2030 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2031 | |
51e72bc1 | 2032 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2033 | } |
2034 | ||
d7bce999 EB |
2035 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2036 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2037 | { |
2038 | PCMachineState *pcms = PC_MACHINE(obj); | |
2039 | ||
51e72bc1 | 2040 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2041 | } |
2042 | ||
355023f2 PB |
2043 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
2044 | { | |
2045 | bool smm_available = false; | |
2046 | ||
2047 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2048 | return false; | |
2049 | } | |
2050 | ||
2051 | if (tcg_enabled() || qtest_enabled()) { | |
2052 | smm_available = true; | |
2053 | } else if (kvm_enabled()) { | |
2054 | smm_available = kvm_has_smm(); | |
2055 | } | |
2056 | ||
2057 | if (smm_available) { | |
2058 | return true; | |
2059 | } | |
2060 | ||
2061 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2062 | error_report("System Management Mode not supported by this hypervisor."); | |
2063 | exit(1); | |
2064 | } | |
2065 | return false; | |
2066 | } | |
2067 | ||
d7bce999 EB |
2068 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
2069 | void *opaque, Error **errp) | |
355023f2 PB |
2070 | { |
2071 | PCMachineState *pcms = PC_MACHINE(obj); | |
2072 | OnOffAuto smm = pcms->smm; | |
2073 | ||
51e72bc1 | 2074 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
2075 | } |
2076 | ||
d7bce999 EB |
2077 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
2078 | void *opaque, Error **errp) | |
355023f2 PB |
2079 | { |
2080 | PCMachineState *pcms = PC_MACHINE(obj); | |
2081 | ||
51e72bc1 | 2082 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
2083 | } |
2084 | ||
be232eb0 CP |
2085 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2086 | { | |
2087 | PCMachineState *pcms = PC_MACHINE(obj); | |
2088 | ||
f5878b03 | 2089 | return pcms->smbus_enabled; |
be232eb0 CP |
2090 | } |
2091 | ||
2092 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2093 | { | |
2094 | PCMachineState *pcms = PC_MACHINE(obj); | |
2095 | ||
f5878b03 | 2096 | pcms->smbus_enabled = value; |
be232eb0 CP |
2097 | } |
2098 | ||
272f0428 CP |
2099 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2100 | { | |
2101 | PCMachineState *pcms = PC_MACHINE(obj); | |
2102 | ||
f5878b03 | 2103 | return pcms->sata_enabled; |
272f0428 CP |
2104 | } |
2105 | ||
2106 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2107 | { | |
2108 | PCMachineState *pcms = PC_MACHINE(obj); | |
2109 | ||
f5878b03 | 2110 | pcms->sata_enabled = value; |
272f0428 CP |
2111 | } |
2112 | ||
feddd2fd CP |
2113 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2114 | { | |
2115 | PCMachineState *pcms = PC_MACHINE(obj); | |
2116 | ||
f5878b03 | 2117 | return pcms->pit_enabled; |
feddd2fd CP |
2118 | } |
2119 | ||
2120 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2121 | { | |
2122 | PCMachineState *pcms = PC_MACHINE(obj); | |
2123 | ||
f5878b03 | 2124 | pcms->pit_enabled = value; |
feddd2fd CP |
2125 | } |
2126 | ||
bf1e8939 IM |
2127 | static void pc_machine_initfn(Object *obj) |
2128 | { | |
c87b1520 DS |
2129 | PCMachineState *pcms = PC_MACHINE(obj); |
2130 | ||
355023f2 | 2131 | pcms->smm = ON_OFF_AUTO_AUTO; |
97fd1ea8 | 2132 | #ifdef CONFIG_VMPORT |
d1048bef | 2133 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
2134 | #else |
2135 | pcms->vmport = ON_OFF_AUTO_OFF; | |
2136 | #endif /* CONFIG_VMPORT */ | |
021746c1 WL |
2137 | /* acpi build is enabled by default if machine supports it */ |
2138 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
2139 | pcms->smbus_enabled = true; |
2140 | pcms->sata_enabled = true; | |
2141 | pcms->pit_enabled = true; | |
ebc29e1b MA |
2142 | |
2143 | pc_system_flash_create(pcms); | |
bf1e8939 IM |
2144 | } |
2145 | ||
a0628599 | 2146 | static void pc_machine_reset(MachineState *machine) |
ae50c55a ZG |
2147 | { |
2148 | CPUState *cs; | |
2149 | X86CPU *cpu; | |
2150 | ||
2151 | qemu_devices_reset(); | |
2152 | ||
2153 | /* Reset APIC after devices have been reset to cancel | |
2154 | * any changes that qemu_devices_reset() might have done. | |
2155 | */ | |
2156 | CPU_FOREACH(cs) { | |
2157 | cpu = X86_CPU(cs); | |
2158 | ||
2159 | if (cpu->apic_state) { | |
2160 | device_reset(cpu->apic_state); | |
2161 | } | |
2162 | } | |
2163 | } | |
2164 | ||
c508bd12 NP |
2165 | static void pc_machine_wakeup(MachineState *machine) |
2166 | { | |
2167 | cpu_synchronize_all_states(); | |
2168 | pc_machine_reset(machine); | |
2169 | cpu_synchronize_all_post_reset(); | |
2170 | } | |
2171 | ||
c6cbc29d PX |
2172 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
2173 | { | |
2174 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
2175 | IntelIOMMUState *intel_iommu; | |
2176 | ||
2177 | if (iommu && | |
2178 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
2179 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
2180 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
2181 | if (!intel_iommu->caching_mode) { | |
2182 | error_setg(errp, "Device assignment is not allowed without " | |
2183 | "enabling caching-mode=on for Intel IOMMU."); | |
2184 | return false; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | return true; | |
2189 | } | |
2190 | ||
95bee274 IM |
2191 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2192 | { | |
2193 | MachineClass *mc = MACHINE_CLASS(oc); | |
2194 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2195 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2196 | ||
7102fa70 EH |
2197 | pcmc->pci_enabled = true; |
2198 | pcmc->has_acpi_build = true; | |
2199 | pcmc->rsdp_in_ram = true; | |
2200 | pcmc->smbios_defaults = true; | |
2201 | pcmc->smbios_uuid_encoded = true; | |
2202 | pcmc->gigabyte_align = true; | |
2203 | pcmc->has_reserved_memory = true; | |
2204 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2205 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2206 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2207 | * to be used at the moment, 32K should be enough for a while. */ | |
2208 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2209 | pcmc->save_tsc_khz = true; |
98e753a6 | 2210 | pcmc->linuxboot_dma_enabled = true; |
fda672b5 | 2211 | pcmc->pvh_enabled = true; |
debbdc00 | 2212 | assert(!mc->get_hotplug_handler); |
285816d7 | 2213 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 2214 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
2215 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
2216 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
2217 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 2218 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 2219 | mc->has_hotpluggable_cpus = true; |
41742767 | 2220 | mc->default_boot_order = "cad"; |
4458fb3a | 2221 | mc->hot_add_cpu = pc_hot_add_cpu; |
6f479566 | 2222 | mc->smp_parse = pc_smp_parse; |
2059839b | 2223 | mc->block_default_type = IF_IDE; |
4458fb3a | 2224 | mc->max_cpus = 255; |
ae50c55a | 2225 | mc->reset = pc_machine_reset; |
c508bd12 | 2226 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 2227 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2228 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2229 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2230 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 2231 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 2232 | mc->nvdimm_supported = true; |
cd5ff833 | 2233 | mc->numa_mem_supported = true; |
0efc257d | 2234 | |
f2ffbe2b DH |
2235 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
2236 | pc_machine_get_device_memory_region_size, NULL, | |
0efc257d EH |
2237 | NULL, NULL, &error_abort); |
2238 | ||
0efc257d EH |
2239 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", |
2240 | pc_machine_get_smm, pc_machine_set_smm, | |
2241 | NULL, NULL, &error_abort); | |
2242 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2243 | "Enable SMM (pc & q35)", &error_abort); | |
2244 | ||
2245 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2246 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2247 | NULL, NULL, &error_abort); | |
2248 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2249 | "Enable vmport (pc & q35)", &error_abort); | |
2250 | ||
be232eb0 CP |
2251 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
2252 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2253 | |
2254 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2255 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2256 | |
2257 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2258 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2259 | } |
2260 | ||
d5747cac IM |
2261 | static const TypeInfo pc_machine_info = { |
2262 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 2263 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
2264 | .abstract = true, |
2265 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2266 | .instance_init = pc_machine_initfn, |
d5747cac | 2267 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2268 | .class_init = pc_machine_class_init, |
2269 | .interfaces = (InterfaceInfo[]) { | |
2270 | { TYPE_HOTPLUG_HANDLER }, | |
2271 | { } | |
2272 | }, | |
d5747cac IM |
2273 | }; |
2274 | ||
2275 | static void pc_machine_register_types(void) | |
2276 | { | |
2277 | type_register_static(&pc_machine_info); | |
2278 | } | |
2279 | ||
2280 | type_init(pc_machine_register_types) |