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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3cce6243 | 34 | #include "fw_cfg.h" |
1baffa46 | 35 | #include "sysbus.h" |
977e1244 | 36 | #include "ide.h" |
3475187d | 37 | |
9d926598 BS |
38 | //#define DEBUG_IRQ |
39 | ||
40 | #ifdef DEBUG_IRQ | |
001faf32 BS |
41 | #define DPRINTF(fmt, ...) \ |
42 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
9d926598 | 43 | #else |
001faf32 | 44 | #define DPRINTF(fmt, ...) |
9d926598 BS |
45 | #endif |
46 | ||
83469015 FB |
47 | #define KERNEL_LOAD_ADDR 0x00404000 |
48 | #define CMDLINE_ADDR 0x003ff000 | |
49 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 50 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 51 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 52 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
53 | #define APB_MEM_BASE 0x1ff00000000ULL |
54 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
55 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 56 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 57 | #define MAX_IDE_BUS 2 |
3cce6243 | 58 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
59 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
60 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
61 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 62 | |
9d926598 BS |
63 | #define MAX_PILS 16 |
64 | ||
8fa211e8 BS |
65 | #define TICK_INT_DIS 0x8000000000000000ULL |
66 | #define TICK_MAX 0x7fffffffffffffffULL | |
67 | ||
c7ba218d BS |
68 | struct hwdef { |
69 | const char * const default_cpu_model; | |
905fdcb5 | 70 | uint16_t machine_id; |
e87231d4 BS |
71 | uint64_t prom_addr; |
72 | uint64_t console_serial_base; | |
c7ba218d BS |
73 | }; |
74 | ||
3475187d FB |
75 | int DMA_get_channel_mode (int nchan) |
76 | { | |
77 | return 0; | |
78 | } | |
79 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
80 | { | |
81 | return 0; | |
82 | } | |
83 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
84 | { | |
85 | return 0; | |
86 | } | |
87 | void DMA_hold_DREQ (int nchan) {} | |
88 | void DMA_release_DREQ (int nchan) {} | |
89 | void DMA_schedule(int nchan) {} | |
3475187d FB |
90 | void DMA_init (int high_page_enable) {} |
91 | void DMA_register_channel (int nchan, | |
92 | DMA_transfer_handler transfer_handler, | |
93 | void *opaque) | |
94 | { | |
95 | } | |
96 | ||
513f789f | 97 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 98 | { |
513f789f | 99 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
100 | return 0; |
101 | } | |
102 | ||
d2c63fc1 | 103 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
e7fb1406 | 104 | const char *arch, |
77f193da BS |
105 | ram_addr_t RAM_size, |
106 | const char *boot_devices, | |
d2c63fc1 BS |
107 | uint32_t kernel_image, uint32_t kernel_size, |
108 | const char *cmdline, | |
109 | uint32_t initrd_image, uint32_t initrd_size, | |
110 | uint32_t NVRAM_image, | |
0d31cb99 BS |
111 | int width, int height, int depth, |
112 | const uint8_t *macaddr) | |
83469015 | 113 | { |
66508601 BS |
114 | unsigned int i; |
115 | uint32_t start, end; | |
d2c63fc1 | 116 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
117 | struct OpenBIOS_nvpart_v1 *part_header; |
118 | ||
119 | memset(image, '\0', sizeof(image)); | |
120 | ||
513f789f | 121 | start = 0; |
83469015 | 122 | |
66508601 BS |
123 | // OpenBIOS nvram variables |
124 | // Variable partition | |
d2c63fc1 BS |
125 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
126 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 127 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 128 | |
d2c63fc1 | 129 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 130 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
131 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
132 | ||
133 | // End marker | |
134 | image[end++] = '\0'; | |
66508601 | 135 | |
66508601 | 136 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 137 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
138 | |
139 | // free partition | |
140 | start = end; | |
d2c63fc1 BS |
141 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
142 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 143 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
144 | |
145 | end = 0x1fd0; | |
d2c63fc1 BS |
146 | OpenBIOS_finish_partition(part_header, end - start); |
147 | ||
0d31cb99 BS |
148 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
149 | ||
d2c63fc1 BS |
150 | for (i = 0; i < sizeof(image); i++) |
151 | m48t59_write(nvram, i, image[i]); | |
66508601 | 152 | |
83469015 | 153 | return 0; |
3475187d | 154 | } |
636aa70a BS |
155 | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
156 | const char *initrd_filename, | |
157 | ram_addr_t RAM_size, long *initrd_size) | |
158 | { | |
159 | int linux_boot; | |
160 | unsigned int i; | |
161 | long kernel_size; | |
162 | ||
163 | linux_boot = (kernel_filename != NULL); | |
164 | ||
165 | kernel_size = 0; | |
166 | if (linux_boot) { | |
167 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); | |
168 | if (kernel_size < 0) | |
169 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, | |
170 | RAM_size - KERNEL_LOAD_ADDR); | |
171 | if (kernel_size < 0) | |
172 | kernel_size = load_image_targphys(kernel_filename, | |
173 | KERNEL_LOAD_ADDR, | |
174 | RAM_size - KERNEL_LOAD_ADDR); | |
175 | if (kernel_size < 0) { | |
176 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
177 | kernel_filename); | |
178 | exit(1); | |
179 | } | |
180 | ||
181 | /* load initrd */ | |
182 | *initrd_size = 0; | |
183 | if (initrd_filename) { | |
184 | *initrd_size = load_image_targphys(initrd_filename, | |
185 | INITRD_LOAD_ADDR, | |
186 | RAM_size - INITRD_LOAD_ADDR); | |
187 | if (*initrd_size < 0) { | |
188 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
189 | initrd_filename); | |
190 | exit(1); | |
191 | } | |
192 | } | |
193 | if (*initrd_size > 0) { | |
194 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
195 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS | |
196 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
197 | stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size); | |
198 | break; | |
199 | } | |
200 | } | |
201 | } | |
202 | } | |
203 | return kernel_size; | |
204 | } | |
3475187d | 205 | |
b4950060 | 206 | void pic_info(Monitor *mon) |
3475187d FB |
207 | { |
208 | } | |
209 | ||
b4950060 | 210 | void irq_info(Monitor *mon) |
3475187d FB |
211 | { |
212 | } | |
213 | ||
9d926598 BS |
214 | void cpu_check_irqs(CPUState *env) |
215 | { | |
216 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | | |
217 | ((env->softint & SOFTINT_TIMER) << 14); | |
218 | ||
219 | if (pil && (env->interrupt_index == 0 || | |
220 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
221 | unsigned int i; | |
222 | ||
223 | for (i = 15; i > 0; i--) { | |
224 | if (pil & (1 << i)) { | |
225 | int old_interrupt = env->interrupt_index; | |
226 | ||
227 | env->interrupt_index = TT_EXTINT | i; | |
228 | if (old_interrupt != env->interrupt_index) { | |
229 | DPRINTF("Set CPU IRQ %d\n", i); | |
230 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
231 | } | |
232 | break; | |
233 | } | |
234 | } | |
235 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { | |
236 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); | |
237 | env->interrupt_index = 0; | |
238 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
239 | } | |
240 | } | |
241 | ||
242 | static void cpu_set_irq(void *opaque, int irq, int level) | |
243 | { | |
244 | CPUState *env = opaque; | |
245 | ||
246 | if (level) { | |
247 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
248 | env->halted = 0; | |
249 | env->pil_in |= 1 << irq; | |
250 | cpu_check_irqs(env); | |
251 | } else { | |
252 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
253 | env->pil_in &= ~(1 << irq); | |
254 | cpu_check_irqs(env); | |
255 | } | |
256 | } | |
257 | ||
e87231d4 BS |
258 | typedef struct ResetData { |
259 | CPUState *env; | |
260 | uint64_t reset_addr; | |
261 | } ResetData; | |
262 | ||
c68ea704 FB |
263 | static void main_cpu_reset(void *opaque) |
264 | { | |
e87231d4 BS |
265 | ResetData *s = (ResetData *)opaque; |
266 | CPUState *env = s->env; | |
20c9f095 | 267 | |
c68ea704 | 268 | cpu_reset(env); |
8fa211e8 BS |
269 | env->tick_cmpr = TICK_INT_DIS | 0; |
270 | ptimer_set_limit(env->tick, TICK_MAX, 1); | |
2f43e00e | 271 | ptimer_run(env->tick, 1); |
8fa211e8 BS |
272 | env->stick_cmpr = TICK_INT_DIS | 0; |
273 | ptimer_set_limit(env->stick, TICK_MAX, 1); | |
2f43e00e | 274 | ptimer_run(env->stick, 1); |
8fa211e8 BS |
275 | env->hstick_cmpr = TICK_INT_DIS | 0; |
276 | ptimer_set_limit(env->hstick, TICK_MAX, 1); | |
2f43e00e | 277 | ptimer_run(env->hstick, 1); |
e87231d4 BS |
278 | env->gregs[1] = 0; // Memory start |
279 | env->gregs[2] = ram_size; // Memory size | |
280 | env->gregs[3] = 0; // Machine description XXX | |
281 | env->pc = s->reset_addr; | |
282 | env->npc = env->pc + 4; | |
20c9f095 BS |
283 | } |
284 | ||
22548760 | 285 | static void tick_irq(void *opaque) |
20c9f095 BS |
286 | { |
287 | CPUState *env = opaque; | |
288 | ||
8fa211e8 BS |
289 | if (!(env->tick_cmpr & TICK_INT_DIS)) { |
290 | env->softint |= SOFTINT_TIMER; | |
291 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
292 | } | |
20c9f095 BS |
293 | } |
294 | ||
22548760 | 295 | static void stick_irq(void *opaque) |
20c9f095 BS |
296 | { |
297 | CPUState *env = opaque; | |
298 | ||
8fa211e8 BS |
299 | if (!(env->stick_cmpr & TICK_INT_DIS)) { |
300 | env->softint |= SOFTINT_STIMER; | |
301 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
302 | } | |
20c9f095 BS |
303 | } |
304 | ||
22548760 | 305 | static void hstick_irq(void *opaque) |
20c9f095 BS |
306 | { |
307 | CPUState *env = opaque; | |
308 | ||
8fa211e8 BS |
309 | if (!(env->hstick_cmpr & TICK_INT_DIS)) { |
310 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
311 | } | |
c68ea704 FB |
312 | } |
313 | ||
f4b1a842 BS |
314 | void cpu_tick_set_count(void *opaque, uint64_t count) |
315 | { | |
316 | ptimer_set_count(opaque, -count); | |
317 | } | |
318 | ||
319 | uint64_t cpu_tick_get_count(void *opaque) | |
320 | { | |
321 | return -ptimer_get_count(opaque); | |
322 | } | |
323 | ||
324 | void cpu_tick_set_limit(void *opaque, uint64_t limit) | |
325 | { | |
326 | ptimer_set_limit(opaque, -limit, 0); | |
327 | } | |
328 | ||
83469015 FB |
329 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
330 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
331 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 332 | |
83469015 FB |
333 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
334 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
335 | ||
336 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
337 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
338 | ||
339 | static fdctrl_t *floppy_controller; | |
3475187d | 340 | |
c190ea07 BS |
341 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
342 | uint32_t addr, uint32_t size, int type) | |
343 | { | |
344 | DPRINTF("Mapping region %d registers at %08x\n", region_num, addr); | |
345 | switch (region_num) { | |
346 | case 0: | |
347 | isa_mmio_init(addr, 0x1000000); | |
348 | break; | |
349 | case 1: | |
350 | isa_mmio_init(addr, 0x800000); | |
351 | break; | |
352 | } | |
353 | } | |
354 | ||
355 | /* EBUS (Eight bit bus) bridge */ | |
356 | static void | |
357 | pci_ebus_init(PCIBus *bus, int devfn) | |
358 | { | |
53e3c4f9 BS |
359 | pci_create_simple(bus, devfn, "ebus"); |
360 | } | |
c190ea07 | 361 | |
81a322d4 | 362 | static int |
53e3c4f9 BS |
363 | pci_ebus_init1(PCIDevice *s) |
364 | { | |
0c5b8d83 BS |
365 | isa_bus_new(&s->qdev); |
366 | ||
deb54399 AL |
367 | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
368 | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); | |
c190ea07 BS |
369 | s->config[0x04] = 0x06; // command = bus master, pci mem |
370 | s->config[0x05] = 0x00; | |
371 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
372 | s->config[0x07] = 0x03; // status = medium devsel | |
373 | s->config[0x08] = 0x01; // revision | |
374 | s->config[0x09] = 0x00; // programming i/f | |
173a543b | 375 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
c190ea07 | 376 | s->config[0x0D] = 0x0a; // latency_timer |
6407f373 | 377 | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
c190ea07 | 378 | |
28c2c264 | 379 | pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 | 380 | ebus_mmio_mapfunc); |
28c2c264 | 381 | pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 | 382 | ebus_mmio_mapfunc); |
81a322d4 | 383 | return 0; |
c190ea07 BS |
384 | } |
385 | ||
53e3c4f9 BS |
386 | static PCIDeviceInfo ebus_info = { |
387 | .qdev.name = "ebus", | |
388 | .qdev.size = sizeof(PCIDevice), | |
389 | .init = pci_ebus_init1, | |
390 | }; | |
391 | ||
392 | static void pci_ebus_register(void) | |
393 | { | |
394 | pci_qdev_register(&ebus_info); | |
395 | } | |
396 | ||
397 | device_init(pci_ebus_register); | |
398 | ||
1baffa46 BS |
399 | /* Boot PROM (OpenBIOS) */ |
400 | static void prom_init(target_phys_addr_t addr, const char *bios_name) | |
401 | { | |
402 | DeviceState *dev; | |
403 | SysBusDevice *s; | |
404 | char *filename; | |
405 | int ret; | |
406 | ||
407 | dev = qdev_create(NULL, "openprom"); | |
408 | qdev_init(dev); | |
409 | s = sysbus_from_qdev(dev); | |
410 | ||
411 | sysbus_mmio_map(s, 0, addr); | |
412 | ||
413 | /* load boot prom */ | |
414 | if (bios_name == NULL) { | |
415 | bios_name = PROM_FILENAME; | |
416 | } | |
417 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
418 | if (filename) { | |
419 | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); | |
420 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
421 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
422 | } | |
423 | qemu_free(filename); | |
424 | } else { | |
425 | ret = -1; | |
426 | } | |
427 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
428 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
429 | exit(1); | |
430 | } | |
431 | } | |
432 | ||
81a322d4 | 433 | static int prom_init1(SysBusDevice *dev) |
1baffa46 BS |
434 | { |
435 | ram_addr_t prom_offset; | |
436 | ||
437 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); | |
438 | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); | |
81a322d4 | 439 | return 0; |
1baffa46 BS |
440 | } |
441 | ||
442 | static SysBusDeviceInfo prom_info = { | |
443 | .init = prom_init1, | |
444 | .qdev.name = "openprom", | |
445 | .qdev.size = sizeof(SysBusDevice), | |
446 | .qdev.props = (Property[]) { | |
447 | {/* end of property list */} | |
448 | } | |
449 | }; | |
450 | ||
451 | static void prom_register_devices(void) | |
452 | { | |
453 | sysbus_register_withprop(&prom_info); | |
454 | } | |
455 | ||
456 | device_init(prom_register_devices); | |
457 | ||
bda42033 BS |
458 | |
459 | typedef struct RamDevice | |
460 | { | |
461 | SysBusDevice busdev; | |
04843626 | 462 | uint64_t size; |
bda42033 BS |
463 | } RamDevice; |
464 | ||
465 | /* System RAM */ | |
81a322d4 | 466 | static int ram_init1(SysBusDevice *dev) |
bda42033 BS |
467 | { |
468 | ram_addr_t RAM_size, ram_offset; | |
469 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); | |
470 | ||
471 | RAM_size = d->size; | |
472 | ||
473 | ram_offset = qemu_ram_alloc(RAM_size); | |
474 | sysbus_init_mmio(dev, RAM_size, ram_offset); | |
81a322d4 | 475 | return 0; |
bda42033 BS |
476 | } |
477 | ||
478 | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) | |
479 | { | |
480 | DeviceState *dev; | |
481 | SysBusDevice *s; | |
482 | RamDevice *d; | |
483 | ||
484 | /* allocate RAM */ | |
485 | dev = qdev_create(NULL, "memory"); | |
486 | s = sysbus_from_qdev(dev); | |
487 | ||
488 | d = FROM_SYSBUS(RamDevice, s); | |
489 | d->size = RAM_size; | |
490 | qdev_init(dev); | |
491 | ||
492 | sysbus_mmio_map(s, 0, addr); | |
493 | } | |
494 | ||
495 | static SysBusDeviceInfo ram_info = { | |
496 | .init = ram_init1, | |
497 | .qdev.name = "memory", | |
498 | .qdev.size = sizeof(RamDevice), | |
499 | .qdev.props = (Property[]) { | |
32a7ee98 GH |
500 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
501 | DEFINE_PROP_END_OF_LIST(), | |
bda42033 BS |
502 | } |
503 | }; | |
504 | ||
505 | static void ram_register_devices(void) | |
506 | { | |
507 | sysbus_register_withprop(&ram_info); | |
508 | } | |
509 | ||
510 | device_init(ram_register_devices); | |
511 | ||
7b833f5b | 512 | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
3475187d | 513 | { |
c68ea704 | 514 | CPUState *env; |
20c9f095 | 515 | QEMUBH *bh; |
e87231d4 | 516 | ResetData *reset_info; |
3475187d | 517 | |
c7ba218d BS |
518 | if (!cpu_model) |
519 | cpu_model = hwdef->default_cpu_model; | |
aaed909a FB |
520 | env = cpu_init(cpu_model); |
521 | if (!env) { | |
62724a37 BS |
522 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
523 | exit(1); | |
524 | } | |
20c9f095 BS |
525 | bh = qemu_bh_new(tick_irq, env); |
526 | env->tick = ptimer_init(bh); | |
527 | ptimer_set_period(env->tick, 1ULL); | |
528 | ||
529 | bh = qemu_bh_new(stick_irq, env); | |
530 | env->stick = ptimer_init(bh); | |
531 | ptimer_set_period(env->stick, 1ULL); | |
532 | ||
533 | bh = qemu_bh_new(hstick_irq, env); | |
534 | env->hstick = ptimer_init(bh); | |
535 | ptimer_set_period(env->hstick, 1ULL); | |
e87231d4 BS |
536 | |
537 | reset_info = qemu_mallocz(sizeof(ResetData)); | |
538 | reset_info->env = env; | |
539 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL; | |
a08d4367 | 540 | qemu_register_reset(main_cpu_reset, reset_info); |
e87231d4 BS |
541 | main_cpu_reset(reset_info); |
542 | // Override warm reset address with cold start address | |
543 | env->pc = hwdef->prom_addr + 0x20ULL; | |
544 | env->npc = env->pc + 4; | |
c68ea704 | 545 | |
7b833f5b BS |
546 | return env; |
547 | } | |
548 | ||
549 | static void sun4uv_init(ram_addr_t RAM_size, | |
550 | const char *boot_devices, | |
551 | const char *kernel_filename, const char *kernel_cmdline, | |
552 | const char *initrd_filename, const char *cpu_model, | |
553 | const struct hwdef *hwdef) | |
554 | { | |
555 | CPUState *env; | |
556 | m48t59_t *nvram; | |
7b833f5b BS |
557 | unsigned int i; |
558 | long initrd_size, kernel_size; | |
559 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; | |
560 | qemu_irq *irq; | |
7b833f5b BS |
561 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
562 | BlockDriverState *fd[MAX_FD]; | |
563 | void *fw_cfg; | |
751c6a17 | 564 | DriveInfo *dinfo; |
7b833f5b | 565 | |
7b833f5b BS |
566 | /* init CPUs */ |
567 | env = cpu_devinit(cpu_model, hwdef); | |
568 | ||
bda42033 BS |
569 | /* set up devices */ |
570 | ram_init(0, RAM_size); | |
3475187d | 571 | |
1baffa46 | 572 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 573 | |
7d55273f IK |
574 | |
575 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
576 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, | |
c190ea07 | 577 | &pci_bus3); |
83469015 | 578 | isa_mem_base = VGA_BASE; |
fbe1b595 | 579 | pci_vga_init(pci_bus, 0, 0); |
83469015 | 580 | |
c190ea07 BS |
581 | // XXX Should be pci_bus3 |
582 | pci_ebus_init(pci_bus, -1); | |
583 | ||
e87231d4 BS |
584 | i = 0; |
585 | if (hwdef->console_serial_base) { | |
586 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, | |
587 | serial_hds[i], 1); | |
588 | i++; | |
589 | } | |
590 | for(; i < MAX_SERIAL_PORTS; i++) { | |
83469015 | 591 | if (serial_hds[i]) { |
cbf5c748 BS |
592 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
593 | serial_hds[i]); | |
83469015 FB |
594 | } |
595 | } | |
596 | ||
597 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
598 | if (parallel_hds[i]) { | |
77f193da BS |
599 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
600 | parallel_hds[i]); | |
83469015 FB |
601 | } |
602 | } | |
603 | ||
cb457d76 | 604 | for(i = 0; i < nb_nics; i++) |
6d53bfd1 | 605 | pci_nic_init(&nd_table[i], "ne2k_pci", NULL); |
83469015 | 606 | |
e4bcb14c TS |
607 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
608 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
609 | exit(1); | |
610 | } | |
611 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
751c6a17 GH |
612 | dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
613 | i % MAX_IDE_DEVS); | |
614 | hd[i] = dinfo ? dinfo->bdrv : NULL; | |
e4bcb14c TS |
615 | } |
616 | ||
3b898dda BS |
617 | pci_cmd646_ide_init(pci_bus, hd, 1); |
618 | ||
d537cf6c PB |
619 | /* FIXME: wire up interrupts. */ |
620 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 621 | for(i = 0; i < MAX_FD; i++) { |
751c6a17 GH |
622 | dinfo = drive_get(IF_FLOPPY, 0, i); |
623 | fd[i] = dinfo ? dinfo->bdrv : NULL; | |
e4bcb14c | 624 | } |
2091ba23 | 625 | floppy_controller = fdctrl_init_isa(6, 2, 0x3f0, fd); |
d537cf6c | 626 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
636aa70a BS |
627 | |
628 | initrd_size = 0; | |
629 | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, | |
630 | ram_size, &initrd_size); | |
631 | ||
22548760 | 632 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
0d31cb99 BS |
633 | KERNEL_LOAD_ADDR, kernel_size, |
634 | kernel_cmdline, | |
635 | INITRD_LOAD_ADDR, initrd_size, | |
636 | /* XXX: need an option to load a NVRAM image */ | |
637 | 0, | |
638 | graphic_width, graphic_height, graphic_depth, | |
639 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 640 | |
3cce6243 BS |
641 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
642 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
643 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
644 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
645 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
646 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
647 | if (kernel_cmdline) { | |
648 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
649 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
650 | } else { | |
651 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
652 | } | |
653 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
654 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
655 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]); | |
7589690c BS |
656 | |
657 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
658 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
659 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
660 | ||
513f789f | 661 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
662 | } |
663 | ||
905fdcb5 BS |
664 | enum { |
665 | sun4u_id = 0, | |
666 | sun4v_id = 64, | |
e87231d4 | 667 | niagara_id, |
905fdcb5 BS |
668 | }; |
669 | ||
c7ba218d BS |
670 | static const struct hwdef hwdefs[] = { |
671 | /* Sun4u generic PC-like machine */ | |
672 | { | |
673 | .default_cpu_model = "TI UltraSparc II", | |
905fdcb5 | 674 | .machine_id = sun4u_id, |
e87231d4 BS |
675 | .prom_addr = 0x1fff0000000ULL, |
676 | .console_serial_base = 0, | |
c7ba218d BS |
677 | }, |
678 | /* Sun4v generic PC-like machine */ | |
679 | { | |
680 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 681 | .machine_id = sun4v_id, |
e87231d4 BS |
682 | .prom_addr = 0x1fff0000000ULL, |
683 | .console_serial_base = 0, | |
684 | }, | |
685 | /* Sun4v generic Niagara machine */ | |
686 | { | |
687 | .default_cpu_model = "Sun UltraSparc T1", | |
688 | .machine_id = niagara_id, | |
689 | .prom_addr = 0xfff0000000ULL, | |
690 | .console_serial_base = 0xfff0c2c000ULL, | |
c7ba218d BS |
691 | }, |
692 | }; | |
693 | ||
694 | /* Sun4u hardware initialisation */ | |
fbe1b595 | 695 | static void sun4u_init(ram_addr_t RAM_size, |
3023f332 | 696 | const char *boot_devices, |
c7ba218d BS |
697 | const char *kernel_filename, const char *kernel_cmdline, |
698 | const char *initrd_filename, const char *cpu_model) | |
699 | { | |
fbe1b595 | 700 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
701 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); |
702 | } | |
703 | ||
704 | /* Sun4v hardware initialisation */ | |
fbe1b595 | 705 | static void sun4v_init(ram_addr_t RAM_size, |
3023f332 | 706 | const char *boot_devices, |
c7ba218d BS |
707 | const char *kernel_filename, const char *kernel_cmdline, |
708 | const char *initrd_filename, const char *cpu_model) | |
709 | { | |
fbe1b595 | 710 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
711 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); |
712 | } | |
713 | ||
e87231d4 | 714 | /* Niagara hardware initialisation */ |
fbe1b595 | 715 | static void niagara_init(ram_addr_t RAM_size, |
3023f332 | 716 | const char *boot_devices, |
e87231d4 BS |
717 | const char *kernel_filename, const char *kernel_cmdline, |
718 | const char *initrd_filename, const char *cpu_model) | |
719 | { | |
fbe1b595 | 720 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
e87231d4 BS |
721 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]); |
722 | } | |
723 | ||
f80f9ec9 | 724 | static QEMUMachine sun4u_machine = { |
66de733b BS |
725 | .name = "sun4u", |
726 | .desc = "Sun4u platform", | |
727 | .init = sun4u_init, | |
1bcee014 | 728 | .max_cpus = 1, // XXX for now |
0c257437 | 729 | .is_default = 1, |
3475187d | 730 | }; |
c7ba218d | 731 | |
f80f9ec9 | 732 | static QEMUMachine sun4v_machine = { |
66de733b BS |
733 | .name = "sun4v", |
734 | .desc = "Sun4v platform", | |
735 | .init = sun4v_init, | |
1bcee014 | 736 | .max_cpus = 1, // XXX for now |
c7ba218d | 737 | }; |
e87231d4 | 738 | |
f80f9ec9 | 739 | static QEMUMachine niagara_machine = { |
e87231d4 BS |
740 | .name = "Niagara", |
741 | .desc = "Sun4v platform, Niagara", | |
742 | .init = niagara_init, | |
1bcee014 | 743 | .max_cpus = 1, // XXX for now |
e87231d4 | 744 | }; |
f80f9ec9 AL |
745 | |
746 | static void sun4u_machine_init(void) | |
747 | { | |
748 | qemu_register_machine(&sun4u_machine); | |
749 | qemu_register_machine(&sun4v_machine); | |
750 | qemu_register_machine(&niagara_machine); | |
751 | } | |
752 | ||
753 | machine_init(sun4u_machine_init); |