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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
b941329d | 29 | #include "qemu/units.h" |
da34e65c | 30 | #include "qapi/error.h" |
4771d756 | 31 | #include "cpu.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
0200db65 | 35 | #include "elf.h" |
022c62cb PB |
36 | #include "exec/memory.h" |
37 | #include "exec/address-spaces.h" | |
0d09e41a | 38 | #include "hw/char/serial.h" |
1422e32d | 39 | #include "net/net.h" |
83c9f4ca | 40 | #include "hw/sysbus.h" |
0d09e41a | 41 | #include "hw/block/flash.h" |
8228e353 | 42 | #include "chardev/char.h" |
996dfe98 | 43 | #include "sysemu/device_tree.h" |
8488ab02 | 44 | #include "qemu/error-report.h" |
922a01a0 | 45 | #include "qemu/option.h" |
b707ab75 | 46 | #include "bootparam.h" |
e53fa62c | 47 | #include "xtensa_memory.h" |
82b25dc8 | 48 | |
740ad9f7 MF |
49 | typedef struct XtfpgaFlashDesc { |
50 | hwaddr base; | |
51 | size_t size; | |
52 | size_t boot_base; | |
53 | size_t sector_size; | |
54 | } XtfpgaFlashDesc; | |
55 | ||
188ce01d | 56 | typedef struct XtfpgaBoardDesc { |
740ad9f7 | 57 | const XtfpgaFlashDesc *flash; |
82b25dc8 | 58 | size_t sram_size; |
85e2d8d5 | 59 | const hwaddr *io; |
188ce01d | 60 | } XtfpgaBoardDesc; |
0200db65 | 61 | |
188ce01d | 62 | typedef struct XtfpgaFpgaState { |
0200db65 MF |
63 | MemoryRegion iomem; |
64 | uint32_t leds; | |
65 | uint32_t switches; | |
188ce01d | 66 | } XtfpgaFpgaState; |
0200db65 | 67 | |
188ce01d | 68 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 69 | { |
188ce01d | 70 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
71 | |
72 | s->leds = 0; | |
73 | s->switches = 0; | |
74 | } | |
75 | ||
188ce01d | 76 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
77 | unsigned size) |
78 | { | |
188ce01d | 79 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
80 | |
81 | switch (addr) { | |
82 | case 0x0: /*build date code*/ | |
556ba668 | 83 | return 0x09272011; |
0200db65 MF |
84 | |
85 | case 0x4: /*processor clock frequency, Hz*/ | |
86 | return 10000000; | |
87 | ||
88 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
89 | return s->leds; | |
90 | ||
91 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
92 | return s->switches; | |
93 | } | |
94 | return 0; | |
95 | } | |
96 | ||
188ce01d | 97 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
98 | uint64_t val, unsigned size) |
99 | { | |
188ce01d | 100 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
101 | |
102 | switch (addr) { | |
103 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
104 | s->leds = val; | |
105 | break; | |
106 | ||
107 | case 0x10: /*board reset*/ | |
108 | if (val == 0xdead) { | |
cf83f140 | 109 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
110 | } |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
188ce01d MF |
115 | static const MemoryRegionOps xtfpga_fpga_ops = { |
116 | .read = xtfpga_fpga_read, | |
117 | .write = xtfpga_fpga_write, | |
0200db65 MF |
118 | .endianness = DEVICE_NATIVE_ENDIAN, |
119 | }; | |
120 | ||
188ce01d | 121 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
a8170e5e | 122 | hwaddr base) |
0200db65 | 123 | { |
188ce01d | 124 | XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); |
0200db65 | 125 | |
188ce01d MF |
126 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
127 | "xtfpga.fpga", 0x10000); | |
0200db65 | 128 | memory_region_add_subregion(address_space, base, &s->iomem); |
188ce01d MF |
129 | xtfpga_fpga_reset(s); |
130 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
131 | return s; |
132 | } | |
133 | ||
188ce01d | 134 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
135 | hwaddr base, |
136 | hwaddr descriptors, | |
137 | hwaddr buffers, | |
0200db65 MF |
138 | qemu_irq irq, NICInfo *nd) |
139 | { | |
140 | DeviceState *dev; | |
141 | SysBusDevice *s; | |
142 | MemoryRegion *ram; | |
143 | ||
144 | dev = qdev_create(NULL, "open_eth"); | |
145 | qdev_set_nic_properties(dev, nd); | |
146 | qdev_init_nofail(dev); | |
147 | ||
1356b98d | 148 | s = SYS_BUS_DEVICE(dev); |
0200db65 MF |
149 | sysbus_connect_irq(s, 0, irq); |
150 | memory_region_add_subregion(address_space, base, | |
151 | sysbus_mmio_get_region(s, 0)); | |
152 | memory_region_add_subregion(address_space, descriptors, | |
153 | sysbus_mmio_get_region(s, 1)); | |
154 | ||
155 | ram = g_malloc(sizeof(*ram)); | |
b941329d | 156 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, |
f8ed85ac | 157 | &error_fatal); |
c5705a77 | 158 | vmstate_register_ram_global(ram); |
0200db65 MF |
159 | memory_region_add_subregion(address_space, buffers, ram); |
160 | } | |
161 | ||
68931a40 | 162 | static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, |
188ce01d | 163 | const XtfpgaBoardDesc *board, |
68931a40 MF |
164 | DriveInfo *dinfo, int be) |
165 | { | |
166 | SysBusDevice *s; | |
167 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
168 | ||
169 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
170 | &error_abort); | |
171 | qdev_prop_set_uint32(dev, "num-blocks", | |
740ad9f7 MF |
172 | board->flash->size / board->flash->sector_size); |
173 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); | |
f9a555e4 | 174 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 175 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 176 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 MF |
177 | qdev_init_nofail(dev); |
178 | s = SYS_BUS_DEVICE(dev); | |
740ad9f7 | 179 | memory_region_add_subregion(address_space, board->flash->base, |
68931a40 MF |
180 | sysbus_mmio_get_region(s, 0)); |
181 | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); | |
182 | } | |
183 | ||
00b941e5 | 184 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 185 | { |
00b941e5 AF |
186 | XtensaCPU *cpu = opaque; |
187 | ||
188 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
189 | } |
190 | ||
188ce01d | 191 | static void xtfpga_reset(void *opaque) |
0200db65 | 192 | { |
eded1267 | 193 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 194 | |
eded1267 | 195 | cpu_reset(CPU(cpu)); |
0200db65 MF |
196 | } |
197 | ||
188ce01d | 198 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
199 | unsigned size) |
200 | { | |
201 | return 0; | |
202 | } | |
203 | ||
188ce01d | 204 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
205 | uint64_t val, unsigned size) |
206 | { | |
207 | } | |
208 | ||
188ce01d MF |
209 | static const MemoryRegionOps xtfpga_io_ops = { |
210 | .read = xtfpga_io_read, | |
211 | .write = xtfpga_io_write, | |
8bb3b575 MF |
212 | .endianness = DEVICE_NATIVE_ENDIAN, |
213 | }; | |
214 | ||
188ce01d | 215 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 MF |
216 | { |
217 | #ifdef TARGET_WORDS_BIGENDIAN | |
218 | int be = 1; | |
219 | #else | |
220 | int be = 0; | |
221 | #endif | |
222 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 223 | XtensaCPU *cpu = NULL; |
5bfcb36e | 224 | CPUXtensaState *env = NULL; |
e53fa62c | 225 | MemoryRegion *system_io; |
82b25dc8 MF |
226 | DriveInfo *dinfo; |
227 | pflash_t *flash = NULL; | |
37b259d0 | 228 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
37b259d0 MF |
229 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
230 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 231 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 232 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
b941329d | 233 | const unsigned system_io_size = 224 * MiB; |
0200db65 MF |
234 | int n; |
235 | ||
236 | for (n = 0; n < smp_cpus; n++) { | |
f83eb10d | 237 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
adbb0f75 AF |
238 | env = &cpu->env; |
239 | ||
0200db65 | 240 | env->sregs[PRID] = n; |
188ce01d | 241 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
242 | /* Need MMU initialized prior to ELF loading, |
243 | * so that ELF gets loaded into virtual addresses | |
244 | */ | |
adbb0f75 | 245 | cpu_reset(CPU(cpu)); |
0200db65 MF |
246 | } |
247 | ||
e53fa62c MF |
248 | if (env) { |
249 | XtensaMemory sysram = env->config->sysram; | |
250 | ||
251 | sysram.location[0].size = machine->ram_size; | |
252 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
253 | system_memory); | |
254 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
255 | system_memory); | |
256 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
257 | system_memory); | |
258 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
259 | system_memory); | |
260 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
261 | system_memory); | |
262 | } | |
0200db65 | 263 | |
0200db65 | 264 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 265 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
85e2d8d5 MF |
266 | system_io_size); |
267 | memory_region_add_subregion(system_memory, board->io[0], system_io); | |
268 | if (board->io[1]) { | |
269 | MemoryRegion *io = g_malloc(sizeof(*io)); | |
270 | ||
271 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", | |
272 | system_io, 0, system_io_size); | |
273 | memory_region_add_subregion(system_memory, board->io[1], io); | |
274 | } | |
188ce01d | 275 | xtfpga_fpga_init(system_io, 0x0d020000); |
a005d073 | 276 | if (nd_table[0].used) { |
188ce01d | 277 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
0200db65 MF |
278 | xtensa_get_extint(env, 1), nd_table); |
279 | } | |
280 | ||
0200db65 | 281 | serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), |
9bca0edb | 282 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
0200db65 | 283 | |
82b25dc8 MF |
284 | dinfo = drive_get(IF_PFLASH, 0, 0); |
285 | if (dinfo) { | |
68931a40 | 286 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
287 | } |
288 | ||
289 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 290 | if (kernel_filename) { |
364d4802 | 291 | uint32_t entry_point = env->pc; |
b6edea8b | 292 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
293 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
294 | board->sram_size; | |
a9a28591 | 295 | uint32_t cur_tagptr; |
b6edea8b MF |
296 | BpMemInfo memory_location = { |
297 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
298 | .start = tswap32(env->config->sysram.location[0].addr), |
299 | .end = tswap32(env->config->sysram.location[0].addr + | |
300 | machine->ram_size), | |
b6edea8b | 301 | }; |
996dfe98 MF |
302 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
303 | machine->ram_size : 0x08000000; | |
304 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 305 | |
e53fa62c MF |
306 | lowmem_end += env->config->sysram.location[0].addr; |
307 | cur_lowmem += env->config->sysram.location[0].addr; | |
308 | ||
309 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
310 | system_memory); | |
292627bb | 311 | |
a9a28591 MF |
312 | if (kernel_cmdline) { |
313 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
314 | } | |
996dfe98 MF |
315 | if (dtb_filename) { |
316 | bp_size += get_tag_size(sizeof(uint32_t)); | |
317 | } | |
f55b32e7 MF |
318 | if (initrd_filename) { |
319 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
320 | } | |
a9a28591 | 321 | |
292627bb | 322 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
323 | tagptr = (tagptr - bp_size) & ~0xff; |
324 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
325 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
326 | sizeof(memory_location), &memory_location); | |
a9a28591 | 327 | |
292627bb | 328 | if (kernel_cmdline) { |
a9a28591 MF |
329 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
330 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 331 | } |
0e80359e | 332 | #ifdef CONFIG_FDT |
996dfe98 MF |
333 | if (dtb_filename) { |
334 | int fdt_size; | |
335 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
336 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
337 | ||
338 | if (!fdt) { | |
ebbb419a | 339 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
340 | exit(EXIT_FAILURE); |
341 | } | |
342 | ||
343 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
344 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
345 | sizeof(dtb_addr), &dtb_addr); | |
b941329d | 346 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); |
996dfe98 | 347 | } |
0e80359e MF |
348 | #else |
349 | if (dtb_filename) { | |
350 | error_report("could not load DTB '%s': " | |
351 | "FDT support is not configured in QEMU", | |
352 | dtb_filename); | |
353 | exit(EXIT_FAILURE); | |
354 | } | |
355 | #endif | |
f55b32e7 MF |
356 | if (initrd_filename) { |
357 | BpMemInfo initrd_location = { 0 }; | |
358 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
359 | lowmem_end - cur_lowmem); | |
360 | ||
361 | if (initrd_size < 0) { | |
362 | initrd_size = load_image_targphys(initrd_filename, | |
363 | cur_lowmem, | |
364 | lowmem_end - cur_lowmem); | |
365 | } | |
366 | if (initrd_size < 0) { | |
ebbb419a | 367 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
368 | exit(EXIT_FAILURE); |
369 | } | |
370 | initrd_location.start = tswap32(cur_lowmem); | |
371 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
372 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
373 | sizeof(initrd_location), &initrd_location); | |
b941329d | 374 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); |
f55b32e7 | 375 | } |
a9a28591 MF |
376 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
377 | env->regs[2] = tagptr; | |
378 | ||
0200db65 MF |
379 | uint64_t elf_entry; |
380 | uint64_t elf_lowaddr; | |
00b941e5 | 381 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
7ef295ea | 382 | &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); |
0200db65 | 383 | if (success > 0) { |
364d4802 MF |
384 | entry_point = elf_entry; |
385 | } else { | |
386 | hwaddr ep; | |
387 | int is_linux; | |
25bda50a | 388 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 389 | translate_phys_addr, cpu); |
364d4802 MF |
390 | if (success > 0 && is_linux) { |
391 | entry_point = ep; | |
392 | } else { | |
ebbb419a | 393 | error_report("could not load kernel '%s'", |
364d4802 MF |
394 | kernel_filename); |
395 | exit(EXIT_FAILURE); | |
396 | } | |
397 | } | |
398 | if (entry_point != env->pc) { | |
339ef8fb | 399 | uint8_t boot[] = { |
364d4802 | 400 | #ifdef TARGET_WORDS_BIGENDIAN |
339ef8fb MF |
401 | 0x60, 0x00, 0x08, /* j 1f */ |
402 | 0x00, /* .literal_position */ | |
403 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
404 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
405 | /* 1: */ | |
406 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
407 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
408 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 409 | #else |
339ef8fb MF |
410 | 0x06, 0x02, 0x00, /* j 1f */ |
411 | 0x00, /* .literal_position */ | |
412 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
413 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
414 | /* 1: */ | |
415 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
416 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
417 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
418 | #endif |
419 | }; | |
339ef8fb MF |
420 | uint32_t entry_pc = tswap32(entry_point); |
421 | uint32_t entry_a2 = tswap32(tagptr); | |
422 | ||
423 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
424 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
425 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 426 | } |
82b25dc8 MF |
427 | } else { |
428 | if (flash) { | |
429 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
430 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
431 | uint32_t size = env->config->sysrom.location[0].size; |
432 | ||
740ad9f7 MF |
433 | if (board->flash->size - board->flash->boot_base < size) { |
434 | size = board->flash->size - board->flash->boot_base; | |
e53fa62c | 435 | } |
82b25dc8 | 436 | |
188ce01d | 437 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
740ad9f7 | 438 | flash_mr, board->flash->boot_base, size); |
e53fa62c MF |
439 | memory_region_add_subregion(system_memory, |
440 | env->config->sysrom.location[0].addr, | |
441 | flash_io); | |
442 | } else { | |
443 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
444 | system_memory); | |
82b25dc8 | 445 | } |
0200db65 MF |
446 | } |
447 | } | |
448 | ||
59b5e9bb MF |
449 | #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) |
450 | ||
85e2d8d5 MF |
451 | static const hwaddr xtfpga_mmu_io[2] = { |
452 | 0xf0000000, | |
453 | }; | |
454 | ||
455 | static const hwaddr xtfpga_nommu_io[2] = { | |
456 | 0x90000000, | |
457 | 0x70000000, | |
458 | }; | |
459 | ||
740ad9f7 MF |
460 | static const XtfpgaFlashDesc lx60_flash = { |
461 | .base = 0x08000000, | |
462 | .size = 0x00400000, | |
463 | .sector_size = 0x10000, | |
464 | }; | |
465 | ||
188ce01d | 466 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 467 | { |
188ce01d | 468 | static const XtfpgaBoardDesc lx60_board = { |
740ad9f7 | 469 | .flash = &lx60_flash, |
82b25dc8 | 470 | .sram_size = 0x20000, |
85e2d8d5 MF |
471 | .io = xtfpga_mmu_io, |
472 | }; | |
473 | xtfpga_init(&lx60_board, machine); | |
474 | } | |
475 | ||
476 | static void xtfpga_lx60_nommu_init(MachineState *machine) | |
477 | { | |
478 | static const XtfpgaBoardDesc lx60_board = { | |
479 | .flash = &lx60_flash, | |
480 | .sram_size = 0x20000, | |
481 | .io = xtfpga_nommu_io, | |
82b25dc8 | 482 | }; |
188ce01d | 483 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
484 | } |
485 | ||
740ad9f7 MF |
486 | static const XtfpgaFlashDesc lx200_flash = { |
487 | .base = 0x08000000, | |
488 | .size = 0x01000000, | |
489 | .sector_size = 0x20000, | |
490 | }; | |
491 | ||
188ce01d | 492 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 493 | { |
188ce01d | 494 | static const XtfpgaBoardDesc lx200_board = { |
740ad9f7 | 495 | .flash = &lx200_flash, |
82b25dc8 | 496 | .sram_size = 0x2000000, |
85e2d8d5 MF |
497 | .io = xtfpga_mmu_io, |
498 | }; | |
499 | xtfpga_init(&lx200_board, machine); | |
500 | } | |
501 | ||
502 | static void xtfpga_lx200_nommu_init(MachineState *machine) | |
503 | { | |
504 | static const XtfpgaBoardDesc lx200_board = { | |
505 | .flash = &lx200_flash, | |
506 | .sram_size = 0x2000000, | |
507 | .io = xtfpga_nommu_io, | |
82b25dc8 | 508 | }; |
188ce01d | 509 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
510 | } |
511 | ||
740ad9f7 MF |
512 | static const XtfpgaFlashDesc ml605_flash = { |
513 | .base = 0x08000000, | |
514 | .size = 0x01000000, | |
515 | .sector_size = 0x20000, | |
516 | }; | |
517 | ||
188ce01d | 518 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 519 | { |
188ce01d | 520 | static const XtfpgaBoardDesc ml605_board = { |
740ad9f7 | 521 | .flash = &ml605_flash, |
e0db904d | 522 | .sram_size = 0x2000000, |
85e2d8d5 MF |
523 | .io = xtfpga_mmu_io, |
524 | }; | |
525 | xtfpga_init(&ml605_board, machine); | |
526 | } | |
527 | ||
528 | static void xtfpga_ml605_nommu_init(MachineState *machine) | |
529 | { | |
530 | static const XtfpgaBoardDesc ml605_board = { | |
531 | .flash = &ml605_flash, | |
532 | .sram_size = 0x2000000, | |
533 | .io = xtfpga_nommu_io, | |
e0db904d | 534 | }; |
188ce01d | 535 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
536 | } |
537 | ||
740ad9f7 MF |
538 | static const XtfpgaFlashDesc kc705_flash = { |
539 | .base = 0x00000000, | |
540 | .size = 0x08000000, | |
541 | .boot_base = 0x06000000, | |
542 | .sector_size = 0x20000, | |
543 | }; | |
544 | ||
188ce01d | 545 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 546 | { |
188ce01d | 547 | static const XtfpgaBoardDesc kc705_board = { |
740ad9f7 | 548 | .flash = &kc705_flash, |
e0db904d | 549 | .sram_size = 0x2000000, |
85e2d8d5 MF |
550 | .io = xtfpga_mmu_io, |
551 | }; | |
552 | xtfpga_init(&kc705_board, machine); | |
553 | } | |
554 | ||
555 | static void xtfpga_kc705_nommu_init(MachineState *machine) | |
556 | { | |
557 | static const XtfpgaBoardDesc kc705_board = { | |
558 | .flash = &kc705_flash, | |
559 | .sram_size = 0x2000000, | |
560 | .io = xtfpga_nommu_io, | |
e0db904d | 561 | }; |
188ce01d | 562 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
563 | } |
564 | ||
188ce01d | 565 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 566 | { |
8a661aea AF |
567 | MachineClass *mc = MACHINE_CLASS(oc); |
568 | ||
e264d29d | 569 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 570 | mc->init = xtfpga_lx60_init; |
e264d29d | 571 | mc->max_cpus = 4; |
f83eb10d | 572 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 573 | mc->default_ram_size = 64 * MiB; |
e264d29d | 574 | } |
0200db65 | 575 | |
188ce01d | 576 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
577 | .name = MACHINE_TYPE_NAME("lx60"), |
578 | .parent = TYPE_MACHINE, | |
188ce01d | 579 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 580 | }; |
82b25dc8 | 581 | |
85e2d8d5 MF |
582 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) |
583 | { | |
584 | MachineClass *mc = MACHINE_CLASS(oc); | |
585 | ||
a3c5e49d | 586 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
587 | mc->init = xtfpga_lx60_nommu_init; |
588 | mc->max_cpus = 4; | |
a3c5e49d | 589 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 590 | mc->default_ram_size = 64 * MiB; |
85e2d8d5 MF |
591 | } |
592 | ||
593 | static const TypeInfo xtfpga_lx60_nommu_type = { | |
594 | .name = MACHINE_TYPE_NAME("lx60-nommu"), | |
595 | .parent = TYPE_MACHINE, | |
596 | .class_init = xtfpga_lx60_nommu_class_init, | |
597 | }; | |
598 | ||
188ce01d | 599 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 600 | { |
8a661aea AF |
601 | MachineClass *mc = MACHINE_CLASS(oc); |
602 | ||
e264d29d | 603 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 604 | mc->init = xtfpga_lx200_init; |
e264d29d | 605 | mc->max_cpus = 4; |
f83eb10d | 606 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 607 | mc->default_ram_size = 96 * MiB; |
e264d29d | 608 | } |
e0db904d | 609 | |
188ce01d | 610 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
611 | .name = MACHINE_TYPE_NAME("lx200"), |
612 | .parent = TYPE_MACHINE, | |
188ce01d | 613 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 614 | }; |
e264d29d | 615 | |
85e2d8d5 MF |
616 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) |
617 | { | |
618 | MachineClass *mc = MACHINE_CLASS(oc); | |
619 | ||
a3c5e49d | 620 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
621 | mc->init = xtfpga_lx200_nommu_init; |
622 | mc->max_cpus = 4; | |
a3c5e49d | 623 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 624 | mc->default_ram_size = 96 * MiB; |
85e2d8d5 MF |
625 | } |
626 | ||
627 | static const TypeInfo xtfpga_lx200_nommu_type = { | |
628 | .name = MACHINE_TYPE_NAME("lx200-nommu"), | |
629 | .parent = TYPE_MACHINE, | |
630 | .class_init = xtfpga_lx200_nommu_class_init, | |
631 | }; | |
632 | ||
188ce01d | 633 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 634 | { |
8a661aea AF |
635 | MachineClass *mc = MACHINE_CLASS(oc); |
636 | ||
e264d29d | 637 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 638 | mc->init = xtfpga_ml605_init; |
e264d29d | 639 | mc->max_cpus = 4; |
f83eb10d | 640 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 641 | mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
e264d29d EH |
642 | } |
643 | ||
188ce01d | 644 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
645 | .name = MACHINE_TYPE_NAME("ml605"), |
646 | .parent = TYPE_MACHINE, | |
188ce01d | 647 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 648 | }; |
e0db904d | 649 | |
85e2d8d5 MF |
650 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) |
651 | { | |
652 | MachineClass *mc = MACHINE_CLASS(oc); | |
653 | ||
a3c5e49d | 654 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
655 | mc->init = xtfpga_ml605_nommu_init; |
656 | mc->max_cpus = 4; | |
a3c5e49d | 657 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 658 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
659 | } |
660 | ||
661 | static const TypeInfo xtfpga_ml605_nommu_type = { | |
662 | .name = MACHINE_TYPE_NAME("ml605-nommu"), | |
663 | .parent = TYPE_MACHINE, | |
664 | .class_init = xtfpga_ml605_nommu_class_init, | |
665 | }; | |
666 | ||
188ce01d | 667 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 668 | { |
8a661aea AF |
669 | MachineClass *mc = MACHINE_CLASS(oc); |
670 | ||
e264d29d | 671 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 672 | mc->init = xtfpga_kc705_init; |
e264d29d | 673 | mc->max_cpus = 4; |
f83eb10d | 674 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 675 | mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
0200db65 MF |
676 | } |
677 | ||
188ce01d | 678 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
679 | .name = MACHINE_TYPE_NAME("kc705"), |
680 | .parent = TYPE_MACHINE, | |
188ce01d | 681 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
682 | }; |
683 | ||
85e2d8d5 MF |
684 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) |
685 | { | |
686 | MachineClass *mc = MACHINE_CLASS(oc); | |
687 | ||
a3c5e49d | 688 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
689 | mc->init = xtfpga_kc705_nommu_init; |
690 | mc->max_cpus = 4; | |
a3c5e49d | 691 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 692 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
693 | } |
694 | ||
695 | static const TypeInfo xtfpga_kc705_nommu_type = { | |
696 | .name = MACHINE_TYPE_NAME("kc705-nommu"), | |
697 | .parent = TYPE_MACHINE, | |
698 | .class_init = xtfpga_kc705_nommu_class_init, | |
699 | }; | |
700 | ||
188ce01d | 701 | static void xtfpga_machines_init(void) |
8a661aea | 702 | { |
188ce01d MF |
703 | type_register_static(&xtfpga_lx60_type); |
704 | type_register_static(&xtfpga_lx200_type); | |
705 | type_register_static(&xtfpga_ml605_type); | |
706 | type_register_static(&xtfpga_kc705_type); | |
85e2d8d5 MF |
707 | type_register_static(&xtfpga_lx60_nommu_type); |
708 | type_register_static(&xtfpga_lx200_nommu_type); | |
709 | type_register_static(&xtfpga_ml605_nommu_type); | |
710 | type_register_static(&xtfpga_kc705_nommu_type); | |
8a661aea AF |
711 | } |
712 | ||
188ce01d | 713 | type_init(xtfpga_machines_init) |