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iommu: Add IOMMU index argument to translate method
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
409ddd01 22#include "qapi/visitor.h"
1de7afc9 23#include "qemu/bitops.h"
8c56c1a5 24#include "qemu/error-report.h"
2c9b15ca 25#include "qom/object.h"
0ab8ed18 26#include "trace-root.h"
093bc2cd 27
022c62cb 28#include "exec/memory-internal.h"
220c3ebd 29#include "exec/ram_addr.h"
8c56c1a5 30#include "sysemu/kvm.h"
e1c57ab8 31#include "sysemu/sysemu.h"
c9356746
FK		 32#include "hw/misc/mmio_interface.h"
33#include "hw/qdev-properties.h"
b08199c6 34#include "migration/vmstate.h"
67d95c15 35
d197063f
PB		 36//#define DEBUG_UNASSIGNED
37
22bde714
JK		 38static unsigned memory_region_transaction_depth;
39static bool memory_region_update_pending;
4dc56152 40static bool ioeventfd_update_pending;
7664e80c
AK		 41static bool global_dirty_log = false;
42
72e22d2f
AK		 43static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 45
0d673e36
AK		 46static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
967dc9b1
AK		 49static GHashTable *flat_views;
50
093bc2cd
AK		 51typedef struct AddrRange AddrRange;
52
8417cebf 53/*
c9cdaa3a 54 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 55 * (large MemoryRegion::alias_offset).
56 */
093bc2cd 57struct AddrRange {
08dafab4
AK		 58 Int128 start;
59 Int128 size;
093bc2cd
AK		 60};
61
08dafab4 62static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 63{
64 return (AddrRange) { start, size };
65}
66
67static bool addrrange_equal(AddrRange r1, AddrRange r2)
68{
08dafab4 69 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 70}
71
08dafab4 72static Int128 addrrange_end(AddrRange r)
093bc2cd 73{
08dafab4 74 return int128_add(r.start, r.size);
093bc2cd
AK		 75}
76
08dafab4 77static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 78{
08dafab4 79 int128_addto(&range.start, delta);
093bc2cd
AK		 80 return range;
81}
82
08dafab4
AK		 83static bool addrrange_contains(AddrRange range, Int128 addr)
84{
85 return int128_ge(addr, range.start)
86 && int128_lt(addr, addrrange_end(range));
87}
88
093bc2cd
AK		 89static bool addrrange_intersects(AddrRange r1, AddrRange r2)
90{
08dafab4
AK		 91 return addrrange_contains(r1, r2.start)
92 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 93}
94
95static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
96{
08dafab4
AK		 97 Int128 start = int128_max(r1.start, r2.start);
98 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
99 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 100}
101
0e0d36b4
AK		 102enum ListenerDirection { Forward, Reverse };
103
7376e582 104#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 105 do { \
106 MemoryListener *_listener; \
107 \
108 switch (_direction) { \
109 case Forward: \
110 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
0e0d36b4
AK		 114 } \
115 break; \
116 case Reverse: \
117 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
118 memory_listeners, link) { \
975aefe0
AK		 119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
0e0d36b4
AK		 122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
9a54635d 129#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 130 do { \
131 MemoryListener *_listener; \
9a54635d 132 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 133 \
134 switch (_direction) { \
135 case Forward: \
9a54635d
PB		 136 QTAILQ_FOREACH(_listener, list, link_as) { \
137 if (_listener->_callback) { \
7376e582
AK		 138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
9a54635d
PB		 143 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
144 link_as) { \
145 if (_listener->_callback) { \
7376e582
AK		 146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
dfde4e6e 155/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 156#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 157 do { \
16620684
AK		 158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
9a54635d 160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 161 } while(0)
0e0d36b4 162
093bc2cd
AK		 163struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166};
167
3e9d69e7
AK		 168struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
753d5e14 172 EventNotifier *e;
3e9d69e7
AK		 173};
174
73bb753d
TB		 175static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
176 MemoryRegionIoeventfd *b)
3e9d69e7 177{
73bb753d 178 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 179 return true;
73bb753d 180 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 181 return false;
73bb753d 182 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 183 return true;
73bb753d 184 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 185 return false;
73bb753d 186 } else if (a->match_data < b->match_data) {
3e9d69e7 187 return true;
73bb753d 188 } else if (a->match_data > b->match_data) {
3e9d69e7 189 return false;
73bb753d
TB		 190 } else if (a->match_data) {
191 if (a->data < b->data) {
3e9d69e7 192 return true;
73bb753d 193 } else if (a->data > b->data) {
3e9d69e7
AK		 194 return false;
195 }
196 }
73bb753d 197 if (a->e < b->e) {
3e9d69e7 198 return true;
73bb753d 199 } else if (a->e > b->e) {
3e9d69e7
AK		 200 return false;
201 }
202 return false;
203}
204
73bb753d
TB		 205static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
206 MemoryRegionIoeventfd *b)
3e9d69e7
AK		 207{
208 return !memory_region_ioeventfd_before(a, b)
209 && !memory_region_ioeventfd_before(b, a);
210}
211
093bc2cd
AK		 212/* Range of memory in the global map. Addresses are absolute. */
213struct FlatRange {
214 MemoryRegion *mr;
a8170e5e 215 hwaddr offset_in_region;
093bc2cd 216 AddrRange addr;
5a583347 217 uint8_t dirty_log_mask;
b138e654 218 bool romd_mode;
fb1cd6f9 219 bool readonly;
093bc2cd
AK		 220};
221
093bc2cd
AK		 222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB		 231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
235 };
236}
237
093bc2cd
AK		 238static bool flatrange_equal(FlatRange *a, FlatRange *b)
239{
240 return a->mr == b->mr
241 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 242 && a->offset_in_region == b->offset_in_region
b138e654 243 && a->romd_mode == b->romd_mode
fb1cd6f9 244 && a->readonly == b->readonly;
093bc2cd
AK		 245}
246
89c177bb 247static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 248{
cc94cd6d
AK		 249 FlatView *view;
250
251 view = g_new0(FlatView, 1);
856d7245 252 view->ref = 1;
89c177bb
AK		 253 view->root = mr_root;
254 memory_region_ref(mr_root);
02d9651d 255 trace_flatview_new(view, mr_root);
cc94cd6d
AK		 256
257 return view;
093bc2cd
AK		 258}
259
260/* Insert a range into a given position. Caller is responsible for maintaining
261 * sorting order.
262 */
263static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
264{
265 if (view->nr == view->nr_allocated) {
266 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 267 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 268 view->nr_allocated * sizeof(*view->ranges));
269 }
270 memmove(view->ranges + pos + 1, view->ranges + pos,
271 (view->nr - pos) * sizeof(FlatRange));
272 view->ranges[pos] = *range;
dfde4e6e 273 memory_region_ref(range->mr);
093bc2cd
AK		 274 ++view->nr;
275}
276
277static void flatview_destroy(FlatView *view)
278{
dfde4e6e
PB		 279 int i;
280
02d9651d 281 trace_flatview_destroy(view, view->root);
66a6df1d
AK		 282 if (view->dispatch) {
283 address_space_dispatch_free(view->dispatch);
284 }
dfde4e6e
PB		 285 for (i = 0; i < view->nr; i++) {
286 memory_region_unref(view->ranges[i].mr);
287 }
7267c094 288 g_free(view->ranges);
89c177bb 289 memory_region_unref(view->root);
a9a0c06d 290 g_free(view);
093bc2cd
AK		 291}
292
447b0d0b 293static bool flatview_ref(FlatView *view)
856d7245 294{
447b0d0b 295 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 296}
297
48564041 298void flatview_unref(FlatView *view)
856d7245
PB		 299{
300 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 301 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 302 assert(view->root);
66a6df1d 303 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 304 }
305}
306
3d8e6bf9
AK		 307static bool can_merge(FlatRange *r1, FlatRange *r2)
308{
08dafab4 309 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 310 && r1->mr == r2->mr
08dafab4
AK		 311 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
312 r1->addr.size),
313 int128_make64(r2->offset_in_region))
d0a9b5bc 314 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 315 && r1->romd_mode == r2->romd_mode
fb1cd6f9 316 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 317}
318
8508e024 319/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 320static void flatview_simplify(FlatView *view)
321{
322 unsigned i, j;
323
324 i = 0;
325 while (i < view->nr) {
326 j = i + 1;
327 while (j < view->nr
328 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 329 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 330 ++j;
331 }
332 ++i;
333 memmove(&view->ranges[i], &view->ranges[j],
334 (view->nr - j) * sizeof(view->ranges[j]));
335 view->nr -= j - i;
336 }
337}
338
e7342aa3
PB		 339static bool memory_region_big_endian(MemoryRegion *mr)
340{
341#ifdef TARGET_WORDS_BIGENDIAN
342 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
343#else
344 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
345#endif
346}
347
e11ef3d1
PB		 348static bool memory_region_wrong_endianness(MemoryRegion *mr)
349{
350#ifdef TARGET_WORDS_BIGENDIAN
351 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
352#else
353 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
354#endif
355}
356
357static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
358{
359 if (memory_region_wrong_endianness(mr)) {
360 switch (size) {
361 case 1:
362 break;
363 case 2:
364 *data = bswap16(*data);
365 break;
366 case 4:
367 *data = bswap32(*data);
368 break;
369 case 8:
370 *data = bswap64(*data);
371 break;
372 default:
373 abort();
374 }
375 }
376}
377
4779dc1d
HB		 378static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
379{
380 MemoryRegion *root;
381 hwaddr abs_addr = offset;
382
383 abs_addr += mr->addr;
384 for (root = mr; root->container; ) {
385 root = root->container;
386 abs_addr += root->addr;
387 }
388
389 return abs_addr;
390}
391
5a68be94
HB		 392static int get_cpu_index(void)
393{
394 if (current_cpu) {
395 return current_cpu->cpu_index;
396 }
397 return -1;
398}
399
cc05c43a
PM		 400static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
401 hwaddr addr,
402 uint64_t *value,
403 unsigned size,
404 unsigned shift,
405 uint64_t mask,
406 MemTxAttrs attrs)
407{
408 uint64_t tmp;
409
410 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 411 if (mr->subpage) {
5a68be94 412 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 413 } else if (mr == &io_mem_notdirty) {
414 /* Accesses to code which has previously been translated into a TB show
415 * up in the MMIO path, as accesses to the io_mem_notdirty
416 * MemoryRegion. */
417 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 418 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
419 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 420 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 421 }
cc05c43a
PM		 422 *value |= (tmp & mask) << shift;
423 return MEMTX_OK;
424}
425
426static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 unsigned shift,
cc05c43a
PM		 431 uint64_t mask,
432 MemTxAttrs attrs)
ce5d2f33 433{
ce5d2f33
PB		 434 uint64_t tmp;
435
cc05c43a 436 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 437 if (mr->subpage) {
5a68be94 438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 439 } else if (mr == &io_mem_notdirty) {
440 /* Accesses to code which has previously been translated into a TB show
441 * up in the MMIO path, as accesses to the io_mem_notdirty
442 * MemoryRegion. */
443 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 444 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
445 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 446 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 447 }
ce5d2f33 448 *value |= (tmp & mask) << shift;
cc05c43a 449 return MEMTX_OK;
ce5d2f33
PB		 450}
451
cc05c43a
PM		 452static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
456 unsigned shift,
457 uint64_t mask,
458 MemTxAttrs attrs)
164a4dcd 459{
cc05c43a
PM		 460 uint64_t tmp = 0;
461 MemTxResult r;
164a4dcd 462
cc05c43a 463 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 464 if (mr->subpage) {
5a68be94 465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 466 } else if (mr == &io_mem_notdirty) {
467 /* Accesses to code which has previously been translated into a TB show
468 * up in the MMIO path, as accesses to the io_mem_notdirty
469 * MemoryRegion. */
470 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 471 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
472 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 473 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 474 }
164a4dcd 475 *value |= (tmp & mask) << shift;
cc05c43a 476 return r;
164a4dcd
AK		 477}
478
cc05c43a
PM		 479static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
480 hwaddr addr,
481 uint64_t *value,
482 unsigned size,
483 unsigned shift,
484 uint64_t mask,
485 MemTxAttrs attrs)
ce5d2f33 486{
ce5d2f33
PB		 487 uint64_t tmp;
488
489 tmp = (*value >> shift) & mask;
23d92d68 490 if (mr->subpage) {
5a68be94 491 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 492 } else if (mr == &io_mem_notdirty) {
493 /* Accesses to code which has previously been translated into a TB show
494 * up in the MMIO path, as accesses to the io_mem_notdirty
495 * MemoryRegion. */
496 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 497 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
498 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 499 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 500 }
ce5d2f33 501 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 502 return MEMTX_OK;
ce5d2f33
PB		 503}
504
cc05c43a
PM		 505static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
506 hwaddr addr,
507 uint64_t *value,
508 unsigned size,
509 unsigned shift,
510 uint64_t mask,
511 MemTxAttrs attrs)
164a4dcd 512{
164a4dcd
AK		 513 uint64_t tmp;
514
515 tmp = (*value >> shift) & mask;
23d92d68 516 if (mr->subpage) {
5a68be94 517 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 518 } else if (mr == &io_mem_notdirty) {
519 /* Accesses to code which has previously been translated into a TB show
520 * up in the MMIO path, as accesses to the io_mem_notdirty
521 * MemoryRegion. */
522 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 523 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
524 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 525 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 526 }
164a4dcd 527 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 528 return MEMTX_OK;
164a4dcd
AK		 529}
530
cc05c43a
PM		 531static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
532 hwaddr addr,
533 uint64_t *value,
534 unsigned size,
535 unsigned shift,
536 uint64_t mask,
537 MemTxAttrs attrs)
538{
539 uint64_t tmp;
540
cc05c43a 541 tmp = (*value >> shift) & mask;
23d92d68 542 if (mr->subpage) {
5a68be94 543 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 544 } else if (mr == &io_mem_notdirty) {
545 /* Accesses to code which has previously been translated into a TB show
546 * up in the MMIO path, as accesses to the io_mem_notdirty
547 * MemoryRegion. */
548 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 549 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
550 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 551 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 552 }
cc05c43a
PM		 553 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
554}
555
556static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 557 uint64_t *value,
558 unsigned size,
559 unsigned access_size_min,
560 unsigned access_size_max,
05e015f7
KF		 561 MemTxResult (*access_fn)
562 (MemoryRegion *mr,
563 hwaddr addr,
564 uint64_t *value,
565 unsigned size,
566 unsigned shift,
567 uint64_t mask,
568 MemTxAttrs attrs),
cc05c43a
PM		 569 MemoryRegion *mr,
570 MemTxAttrs attrs)
164a4dcd
AK		 571{
572 uint64_t access_mask;
573 unsigned access_size;
574 unsigned i;
cc05c43a 575 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 576
577 if (!access_size_min) {
578 access_size_min = 1;
579 }
580 if (!access_size_max) {
581 access_size_max = 4;
582 }
ce5d2f33
PB		 583
584 /* FIXME: support unaligned access? */
164a4dcd
AK		 585 access_size = MAX(MIN(size, access_size_max), access_size_min);
586 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 587 if (memory_region_big_endian(mr)) {
588 for (i = 0; i < size; i += access_size) {
05e015f7 589 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 590 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 591 }
592 } else {
593 for (i = 0; i < size; i += access_size) {
05e015f7 594 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 595 access_mask, attrs);
e7342aa3 596 }
164a4dcd 597 }
cc05c43a 598 return r;
164a4dcd
AK		 599}
600
e2177955
AK		 601static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
602{
0d673e36
AK		 603 AddressSpace *as;
604
feca4ac1
PB		 605 while (mr->container) {
606 mr = mr->container;
e2177955 607 }
0d673e36
AK		 608 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
609 if (mr == as->root) {
610 return as;
611 }
e2177955 612 }
eed2bacf 613 return NULL;
e2177955
AK		 614}
615
093bc2cd
AK		 616/* Render a memory region into the global view. Ranges in @view obscure
617 * ranges in @mr.
618 */
619static void render_memory_region(FlatView *view,
620 MemoryRegion *mr,
08dafab4 621 Int128 base,
fb1cd6f9
AK		 622 AddrRange clip,
623 bool readonly)
093bc2cd
AK		 624{
625 MemoryRegion *subregion;
626 unsigned i;
a8170e5e 627 hwaddr offset_in_region;
08dafab4
AK		 628 Int128 remain;
629 Int128 now;
093bc2cd
AK		 630 FlatRange fr;
631 AddrRange tmp;
632
6bba19ba
AK		 633 if (!mr->enabled) {
634 return;
635 }
636
08dafab4 637 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 638 readonly |= mr->readonly;
093bc2cd
AK		 639
640 tmp = addrrange_make(base, mr->size);
641
642 if (!addrrange_intersects(tmp, clip)) {
643 return;
644 }
645
646 clip = addrrange_intersection(tmp, clip);
647
648 if (mr->alias) {
08dafab4
AK		 649 int128_subfrom(&base, int128_make64(mr->alias->addr));
650 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 651 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 652 return;
653 }
654
655 /* Render subregions in priority order. */
656 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 657 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 658 }
659
14a3c10a 660 if (!mr->terminates) {
093bc2cd
AK		 661 return;
662 }
663
08dafab4 664 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 665 base = clip.start;
666 remain = clip.size;
667
2eb74e1a 668 fr.mr = mr;
6f6a5ef3 669 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 670 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 671 fr.readonly = readonly;
672
093bc2cd 673 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 674 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
675 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 676 continue;
677 }
08dafab4
AK		 678 if (int128_lt(base, view->ranges[i].addr.start)) {
679 now = int128_min(remain,
680 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, now);
683 flatview_insert(view, i, &fr);
684 ++i;
08dafab4
AK		 685 int128_addto(&base, now);
686 offset_in_region += int128_get64(now);
687 int128_subfrom(&remain, now);
093bc2cd 688 }
d26a8cae
AK		 689 now = int128_sub(int128_min(int128_add(base, remain),
690 addrrange_end(view->ranges[i].addr)),
691 base);
692 int128_addto(&base, now);
693 offset_in_region += int128_get64(now);
694 int128_subfrom(&remain, now);
093bc2cd 695 }
08dafab4 696 if (int128_nz(remain)) {
093bc2cd
AK		 697 fr.offset_in_region = offset_in_region;
698 fr.addr = addrrange_make(base, remain);
699 flatview_insert(view, i, &fr);
700 }
701}
702
89c177bb
AK		 703static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
704{
e673ba9a
PB		 705 while (mr->enabled) {
706 if (mr->alias) {
707 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
708 /* The alias is included in its entirety. Use it as
709 * the "real" root, so that we can share more FlatViews.
710 */
711 mr = mr->alias;
712 continue;
713 }
714 } else if (!mr->terminates) {
715 unsigned int found = 0;
716 MemoryRegion *child, *next = NULL;
717 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
718 if (child->enabled) {
719 if (++found > 1) {
720 next = NULL;
721 break;
722 }
723 if (!child->addr && int128_ge(mr->size, child->size)) {
724 /* A child is included in its entirety. If it's the only
725 * enabled one, use it in the hope of finding an alias down the
726 * way. This will also let us share FlatViews.
727 */
728 next = child;
729 }
730 }
731 }
092aa2fc
AK		 732 if (found == 0) {
733 return NULL;
734 }
e673ba9a
PB		 735 if (next) {
736 mr = next;
737 continue;
738 }
739 }
740
092aa2fc 741 return mr;
89c177bb
AK		 742 }
743
092aa2fc 744 return NULL;
89c177bb
AK		 745}
746
093bc2cd 747/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 748static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 749{
9bf561e3 750 int i;
a9a0c06d 751 FlatView *view;
093bc2cd 752
89c177bb 753 view = flatview_new(mr);
093bc2cd 754
83f3c251 755 if (mr) {
a9a0c06d 756 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 757 addrrange_make(int128_zero(), int128_2_64()), false);
758 }
a9a0c06d 759 flatview_simplify(view);
093bc2cd 760
9bf561e3
AK		 761 view->dispatch = address_space_dispatch_new(view);
762 for (i = 0; i < view->nr; i++) {
763 MemoryRegionSection mrs =
764 section_from_flat_range(&view->ranges[i], view);
765 flatview_add_to_dispatch(view, &mrs);
766 }
767 address_space_dispatch_compact(view->dispatch);
967dc9b1 768 g_hash_table_replace(flat_views, mr, view);
9bf561e3 769
093bc2cd
AK		 770 return view;
771}
772
3e9d69e7
AK		 773static void address_space_add_del_ioeventfds(AddressSpace *as,
774 MemoryRegionIoeventfd *fds_new,
775 unsigned fds_new_nb,
776 MemoryRegionIoeventfd *fds_old,
777 unsigned fds_old_nb)
778{
779 unsigned iold, inew;
80a1ea37
AK		 780 MemoryRegionIoeventfd *fd;
781 MemoryRegionSection section;
3e9d69e7
AK		 782
783 /* Generate a symmetric difference of the old and new fd sets, adding
784 * and deleting as necessary.
785 */
786
787 iold = inew = 0;
788 while (iold < fds_old_nb || inew < fds_new_nb) {
789 if (iold < fds_old_nb
790 && (inew == fds_new_nb
73bb753d
TB		 791 || memory_region_ioeventfd_before(&fds_old[iold],
792 &fds_new[inew]))) {
80a1ea37
AK		 793 fd = &fds_old[iold];
794 section = (MemoryRegionSection) {
16620684 795 .fv = address_space_to_flatview(as),
80a1ea37 796 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 797 .size = fd->addr.size,
80a1ea37 798 };
9a54635d 799 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 800 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 801 ++iold;
802 } else if (inew < fds_new_nb
803 && (iold == fds_old_nb
73bb753d
TB		 804 || memory_region_ioeventfd_before(&fds_new[inew],
805 &fds_old[iold]))) {
80a1ea37
AK		 806 fd = &fds_new[inew];
807 section = (MemoryRegionSection) {
16620684 808 .fv = address_space_to_flatview(as),
80a1ea37 809 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 810 .size = fd->addr.size,
80a1ea37 811 };
9a54635d 812 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 813 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 814 ++inew;
815 } else {
816 ++iold;
817 ++inew;
818 }
819 }
820}
821
48564041 822FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB		 823{
824 FlatView *view;
825
374f2981 826 rcu_read_lock();
447b0d0b 827 do {
16620684 828 view = address_space_to_flatview(as);
447b0d0b
PB		 829 /* If somebody has replaced as->current_map concurrently,
830 * flatview_ref returns false.
831 */
832 } while (!flatview_ref(view));
374f2981 833 rcu_read_unlock();
856d7245
PB		 834 return view;
835}
836
3e9d69e7
AK		 837static void address_space_update_ioeventfds(AddressSpace *as)
838{
99e86347 839 FlatView *view;
3e9d69e7
AK		 840 FlatRange *fr;
841 unsigned ioeventfd_nb = 0;
842 MemoryRegionIoeventfd *ioeventfds = NULL;
843 AddrRange tmp;
844 unsigned i;
845
856d7245 846 view = address_space_get_flatview(as);
99e86347 847 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 848 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
849 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 850 int128_sub(fr->addr.start,
851 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 852 if (addrrange_intersects(fr->addr, tmp)) {
853 ++ioeventfd_nb;
7267c094 854 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 855 ioeventfd_nb * sizeof(*ioeventfds));
856 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
857 ioeventfds[ioeventfd_nb-1].addr = tmp;
858 }
859 }
860 }
861
862 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
863 as->ioeventfds, as->ioeventfd_nb);
864
7267c094 865 g_free(as->ioeventfds);
3e9d69e7
AK		 866 as->ioeventfds = ioeventfds;
867 as->ioeventfd_nb = ioeventfd_nb;
856d7245 868 flatview_unref(view);
3e9d69e7
AK		 869}
870
b8af1afb 871static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 872 const FlatView *old_view,
873 const FlatView *new_view,
b8af1afb 874 bool adding)
093bc2cd 875{
093bc2cd
AK		 876 unsigned iold, inew;
877 FlatRange *frold, *frnew;
093bc2cd
AK		 878
879 /* Generate a symmetric difference of the old and new memory maps.
880 * Kill ranges in the old map, and instantiate ranges in the new map.
881 */
882 iold = inew = 0;
a9a0c06d
PB		 883 while (iold < old_view->nr || inew < new_view->nr) {
884 if (iold < old_view->nr) {
885 frold = &old_view->ranges[iold];
093bc2cd
AK		 886 } else {
887 frold = NULL;
888 }
a9a0c06d
PB		 889 if (inew < new_view->nr) {
890 frnew = &new_view->ranges[inew];
093bc2cd
AK		 891 } else {
892 frnew = NULL;
893 }
894
895 if (frold
896 && (!frnew
08dafab4
AK		 897 || int128_lt(frold->addr.start, frnew->addr.start)
898 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 899 && !flatrange_equal(frold, frnew)))) {
41a6e477 900 /* In old but not in new, or in both but attributes changed. */
093bc2cd 901
b8af1afb 902 if (!adding) {
72e22d2f 903 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 904 }
905
093bc2cd
AK		 906 ++iold;
907 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 908 /* In both and unchanged (except logging may have changed) */
093bc2cd 909
b8af1afb 910 if (adding) {
50c1e149 911 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 912 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
913 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
914 frold->dirty_log_mask,
915 frnew->dirty_log_mask);
916 }
917 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
918 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
919 frold->dirty_log_mask,
920 frnew->dirty_log_mask);
b8af1afb 921 }
5a583347
AK		 922 }
923
093bc2cd
AK		 924 ++iold;
925 ++inew;
093bc2cd
AK		 926 } else {
927 /* In new */
928
b8af1afb 929 if (adding) {
72e22d2f 930 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 931 }
932
093bc2cd
AK		 933 ++inew;
934 }
935 }
b8af1afb
AK		 936}
937
967dc9b1
AK		 938static void flatviews_init(void)
939{
092aa2fc
AK		 940 static FlatView *empty_view;
941
967dc9b1
AK		 942 if (flat_views) {
943 return;
944 }
945
946 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
947 (GDestroyNotify) flatview_unref);
092aa2fc
AK		 948 if (!empty_view) {
949 empty_view = generate_memory_topology(NULL);
950 /* We keep it alive forever in the global variable. */
951 flatview_ref(empty_view);
952 } else {
953 g_hash_table_replace(flat_views, NULL, empty_view);
954 flatview_ref(empty_view);
955 }
967dc9b1
AK		 956}
957
958static void flatviews_reset(void)
959{
960 AddressSpace *as;
961
962 if (flat_views) {
963 g_hash_table_unref(flat_views);
964 flat_views = NULL;
965 }
966 flatviews_init();
967
968 /* Render unique FVs */
969 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
970 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
971
972 if (g_hash_table_lookup(flat_views, physmr)) {
973 continue;
974 }
975
976 generate_memory_topology(physmr);
977 }
978}
979
980static void address_space_set_flatview(AddressSpace *as)
b8af1afb 981{
67ace39b 982 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK		 983 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
984 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
985
986 assert(new_view);
987
67ace39b
AK		 988 if (old_view == new_view) {
989 return;
990 }
991
992 if (old_view) {
993 flatview_ref(old_view);
994 }
995
967dc9b1 996 flatview_ref(new_view);
9a62e24f
AK		 997
998 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK		 999 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1000
1001 if (!old_view2) {
1002 old_view2 = &tmpview;
1003 }
1004 address_space_update_topology_pass(as, old_view2, new_view, false);
1005 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1006 }
b8af1afb 1007
374f2981
PB		 1008 /* Writes are protected by the BQL. */
1009 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK		 1010 if (old_view) {
1011 flatview_unref(old_view);
1012 }
856d7245
PB		 1013
1014 /* Note that all the old MemoryRegions are still alive up to this
1015 * point. This relieves most MemoryListeners from the need to
1016 * ref/unref the MemoryRegions they get---unless they use them
1017 * outside the iothread mutex, in which case precise reference
1018 * counting is necessary.
1019 */
67ace39b
AK		 1020 if (old_view) {
1021 flatview_unref(old_view);
1022 }
093bc2cd
AK		 1023}
1024
202fc01b
AK		 1025static void address_space_update_topology(AddressSpace *as)
1026{
1027 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1028
1029 flatviews_init();
1030 if (!g_hash_table_lookup(flat_views, physmr)) {
1031 generate_memory_topology(physmr);
1032 }
1033 address_space_set_flatview(as);
1034}
1035
4ef4db86
AK		 1036void memory_region_transaction_begin(void)
1037{
bb880ded 1038 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 1039 ++memory_region_transaction_depth;
1040}
1041
1042void memory_region_transaction_commit(void)
1043{
0d673e36
AK		 1044 AddressSpace *as;
1045
4ef4db86 1046 assert(memory_region_transaction_depth);
8d04fb55
JK		 1047 assert(qemu_mutex_iothread_locked());
1048
4ef4db86 1049 --memory_region_transaction_depth;
4dc56152
GA		 1050 if (!memory_region_transaction_depth) {
1051 if (memory_region_update_pending) {
967dc9b1
AK		 1052 flatviews_reset();
1053
4dc56152 1054 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1055
4dc56152 1056 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1057 address_space_set_flatview(as);
02218487 1058 address_space_update_ioeventfds(as);
4dc56152 1059 }
ade9c1aa 1060 memory_region_update_pending = false;
0b152095 1061 ioeventfd_update_pending = false;
4dc56152
GA		 1062 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1063 } else if (ioeventfd_update_pending) {
1064 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1065 address_space_update_ioeventfds(as);
1066 }
ade9c1aa 1067 ioeventfd_update_pending = false;
4dc56152 1068 }
4dc56152 1069 }
4ef4db86
AK		 1070}
1071
545e92e0
AK		 1072static void memory_region_destructor_none(MemoryRegion *mr)
1073{
1074}
1075
1076static void memory_region_destructor_ram(MemoryRegion *mr)
1077{
f1060c55 1078 qemu_ram_free(mr->ram_block);
545e92e0
AK		 1079}
1080
b4fefef9
PC		 1081static bool memory_region_need_escape(char c)
1082{
1083 return c == '/' || c == '[' || c == '\\' || c == ']';
1084}
1085
1086static char *memory_region_escape_name(const char *name)
1087{
1088 const char *p;
1089 char *escaped, *q;
1090 uint8_t c;
1091 size_t bytes = 0;
1092
1093 for (p = name; *p; p++) {
1094 bytes += memory_region_need_escape(*p) ? 4 : 1;
1095 }
1096 if (bytes == p - name) {
1097 return g_memdup(name, bytes + 1);
1098 }
1099
1100 escaped = g_malloc(bytes + 1);
1101 for (p = name, q = escaped; *p; p++) {
1102 c = *p;
1103 if (unlikely(memory_region_need_escape(c))) {
1104 *q++ = '\\';
1105 *q++ = 'x';
1106 *q++ = "0123456789abcdef"[c >> 4];
1107 c = "0123456789abcdef"[c & 15];
1108 }
1109 *q++ = c;
1110 }
1111 *q = 0;
1112 return escaped;
1113}
1114
3df9d748
AK		 1115static void memory_region_do_init(MemoryRegion *mr,
1116 Object *owner,
1117 const char *name,
1118 uint64_t size)
093bc2cd 1119{
08dafab4
AK		 1120 mr->size = int128_make64(size);
1121 if (size == UINT64_MAX) {
1122 mr->size = int128_2_64();
1123 }
302fa283 1124 mr->name = g_strdup(name);
612263cf 1125 mr->owner = owner;
58eaa217 1126 mr->ram_block = NULL;
b4fefef9
PC		 1127
1128 if (name) {
843ef73a
PC		 1129 char *escaped_name = memory_region_escape_name(name);
1130 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1131
1132 if (!owner) {
1133 owner = container_get(qdev_get_machine(), "/unattached");
1134 }
1135
843ef73a 1136 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1137 object_unref(OBJECT(mr));
843ef73a
PC		 1138 g_free(name_array);
1139 g_free(escaped_name);
b4fefef9
PC		 1140 }
1141}
1142
3df9d748
AK		 1143void memory_region_init(MemoryRegion *mr,
1144 Object *owner,
1145 const char *name,
1146 uint64_t size)
1147{
1148 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1149 memory_region_do_init(mr, owner, name, size);
1150}
1151
d7bce999
EB		 1152static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1153 void *opaque, Error **errp)
409ddd01
PC		 1154{
1155 MemoryRegion *mr = MEMORY_REGION(obj);
1156 uint64_t value = mr->addr;
1157
51e72bc1 1158 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1159}
1160
d7bce999
EB		 1161static void memory_region_get_container(Object *obj, Visitor *v,
1162 const char *name, void *opaque,
1163 Error **errp)
409ddd01
PC		 1164{
1165 MemoryRegion *mr = MEMORY_REGION(obj);
1166 gchar *path = (gchar *)"";
1167
1168 if (mr->container) {
1169 path = object_get_canonical_path(OBJECT(mr->container));
1170 }
51e72bc1 1171 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1172 if (mr->container) {
1173 g_free(path);
1174 }
1175}
1176
1177static Object *memory_region_resolve_container(Object *obj, void *opaque,
1178 const char *part)
1179{
1180 MemoryRegion *mr = MEMORY_REGION(obj);
1181
1182 return OBJECT(mr->container);
1183}
1184
d7bce999
EB		 1185static void memory_region_get_priority(Object *obj, Visitor *v,
1186 const char *name, void *opaque,
1187 Error **errp)
d33382da
PC		 1188{
1189 MemoryRegion *mr = MEMORY_REGION(obj);
1190 int32_t value = mr->priority;
1191
51e72bc1 1192 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1193}
1194
d7bce999
EB		 1195static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1196 void *opaque, Error **errp)
52aef7bb
PC		 1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 uint64_t value = memory_region_size(mr);
1200
51e72bc1 1201 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1202}
1203
b4fefef9
PC		 1204static void memory_region_initfn(Object *obj)
1205{
1206 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1207 ObjectProperty *op;
b4fefef9
PC		 1208
1209 mr->ops = &unassigned_mem_ops;
6bba19ba 1210 mr->enabled = true;
5f9a5ea1 1211 mr->romd_mode = true;
196ea131 1212 mr->global_locking = true;
545e92e0 1213 mr->destructor = memory_region_destructor_none;
093bc2cd 1214 QTAILQ_INIT(&mr->subregions);
093bc2cd 1215 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1216
1217 op = object_property_add(OBJECT(mr), "container",
1218 "link<" TYPE_MEMORY_REGION ">",
1219 memory_region_get_container,
1220 NULL, /* memory_region_set_container */
1221 NULL, NULL, &error_abort);
1222 op->resolve = memory_region_resolve_container;
1223
1224 object_property_add(OBJECT(mr), "addr", "uint64",
1225 memory_region_get_addr,
1226 NULL, /* memory_region_set_addr */
1227 NULL, NULL, &error_abort);
d33382da
PC		 1228 object_property_add(OBJECT(mr), "priority", "uint32",
1229 memory_region_get_priority,
1230 NULL, /* memory_region_set_priority */
1231 NULL, NULL, &error_abort);
52aef7bb
PC		 1232 object_property_add(OBJECT(mr), "size", "uint64",
1233 memory_region_get_size,
1234 NULL, /* memory_region_set_size, */
1235 NULL, NULL, &error_abort);
093bc2cd
AK		 1236}
1237
3df9d748
AK		 1238static void iommu_memory_region_initfn(Object *obj)
1239{
1240 MemoryRegion *mr = MEMORY_REGION(obj);
1241
1242 mr->is_iommu = true;
1243}
1244
b018ddf6
PB		 1245static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1246 unsigned size)
1247{
1248#ifdef DEBUG_UNASSIGNED
1249 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1250#endif
4917cf44
AF		 1251 if (current_cpu != NULL) {
1252 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1253 }
68a7439a 1254 return 0;
b018ddf6
PB		 1255}
1256
1257static void unassigned_mem_write(void *opaque, hwaddr addr,
1258 uint64_t val, unsigned size)
1259{
1260#ifdef DEBUG_UNASSIGNED
1261 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1262#endif
4917cf44
AF		 1263 if (current_cpu != NULL) {
1264 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1265 }
b018ddf6
PB		 1266}
1267
d197063f 1268static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM		 1269 unsigned size, bool is_write,
1270 MemTxAttrs attrs)
d197063f
PB		 1271{
1272 return false;
1273}
1274
1275const MemoryRegionOps unassigned_mem_ops = {
1276 .valid.accepts = unassigned_mem_accepts,
1277 .endianness = DEVICE_NATIVE_ENDIAN,
1278};
1279
4a2e242b
AW		 1280static uint64_t memory_region_ram_device_read(void *opaque,
1281 hwaddr addr, unsigned size)
1282{
1283 MemoryRegion *mr = opaque;
1284 uint64_t data = (uint64_t)~0;
1285
1286 switch (size) {
1287 case 1:
1288 data = *(uint8_t *)(mr->ram_block->host + addr);
1289 break;
1290 case 2:
1291 data = *(uint16_t *)(mr->ram_block->host + addr);
1292 break;
1293 case 4:
1294 data = *(uint32_t *)(mr->ram_block->host + addr);
1295 break;
1296 case 8:
1297 data = *(uint64_t *)(mr->ram_block->host + addr);
1298 break;
1299 }
1300
1301 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1302
1303 return data;
1304}
1305
1306static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1307 uint64_t data, unsigned size)
1308{
1309 MemoryRegion *mr = opaque;
1310
1311 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1312
1313 switch (size) {
1314 case 1:
1315 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1316 break;
1317 case 2:
1318 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1319 break;
1320 case 4:
1321 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1322 break;
1323 case 8:
1324 *(uint64_t *)(mr->ram_block->host + addr) = data;
1325 break;
1326 }
1327}
1328
1329static const MemoryRegionOps ram_device_mem_ops = {
1330 .read = memory_region_ram_device_read,
1331 .write = memory_region_ram_device_write,
c99a29e7 1332 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1333 .valid = {
1334 .min_access_size = 1,
1335 .max_access_size = 8,
1336 .unaligned = true,
1337 },
1338 .impl = {
1339 .min_access_size = 1,
1340 .max_access_size = 8,
1341 .unaligned = true,
1342 },
1343};
1344
d2702032
PB		 1345bool memory_region_access_valid(MemoryRegion *mr,
1346 hwaddr addr,
1347 unsigned size,
6d7b9a6c
PM		 1348 bool is_write,
1349 MemTxAttrs attrs)
093bc2cd 1350{
a014ed07
PB		 1351 int access_size_min, access_size_max;
1352 int access_size, i;
897fa7cf 1353
093bc2cd
AK		 1354 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1355 return false;
1356 }
1357
a014ed07 1358 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1359 return true;
1360 }
1361
a014ed07
PB		 1362 access_size_min = mr->ops->valid.min_access_size;
1363 if (!mr->ops->valid.min_access_size) {
1364 access_size_min = 1;
1365 }
1366
1367 access_size_max = mr->ops->valid.max_access_size;
1368 if (!mr->ops->valid.max_access_size) {
1369 access_size_max = 4;
1370 }
1371
1372 access_size = MAX(MIN(size, access_size_max), access_size_min);
1373 for (i = 0; i < size; i += access_size) {
1374 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1375 is_write, attrs)) {
a014ed07
PB		 1376 return false;
1377 }
093bc2cd 1378 }
a014ed07 1379
093bc2cd
AK		 1380 return true;
1381}
1382
cc05c43a
PM		 1383static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1384 hwaddr addr,
1385 uint64_t *pval,
1386 unsigned size,
1387 MemTxAttrs attrs)
093bc2cd 1388{
cc05c43a 1389 *pval = 0;
093bc2cd 1390
ce5d2f33 1391 if (mr->ops->read) {
cc05c43a
PM		 1392 return access_with_adjusted_size(addr, pval, size,
1393 mr->ops->impl.min_access_size,
1394 mr->ops->impl.max_access_size,
1395 memory_region_read_accessor,
1396 mr, attrs);
1397 } else if (mr->ops->read_with_attrs) {
1398 return access_with_adjusted_size(addr, pval, size,
1399 mr->ops->impl.min_access_size,
1400 mr->ops->impl.max_access_size,
1401 memory_region_read_with_attrs_accessor,
1402 mr, attrs);
ce5d2f33 1403 } else {
cc05c43a
PM		 1404 return access_with_adjusted_size(addr, pval, size, 1, 4,
1405 memory_region_oldmmio_read_accessor,
1406 mr, attrs);
74901c3b 1407 }
093bc2cd
AK		 1408}
1409
3b643495
PM		 1410MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1411 hwaddr addr,
1412 uint64_t *pval,
1413 unsigned size,
1414 MemTxAttrs attrs)
a621f38d 1415{
cc05c43a
PM		 1416 MemTxResult r;
1417
6d7b9a6c 1418 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1419 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1420 return MEMTX_DECODE_ERROR;
791af8c8 1421 }
a621f38d 1422
cc05c43a 1423 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1424 adjust_endianness(mr, pval, size);
cc05c43a 1425 return r;
a621f38d 1426}
093bc2cd 1427
8c56c1a5
PF		 1428/* Return true if an eventfd was signalled */
1429static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1430 hwaddr addr,
1431 uint64_t data,
1432 unsigned size,
1433 MemTxAttrs attrs)
1434{
1435 MemoryRegionIoeventfd ioeventfd = {
1436 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1437 .data = data,
1438 };
1439 unsigned i;
1440
1441 for (i = 0; i < mr->ioeventfd_nb; i++) {
1442 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1443 ioeventfd.e = mr->ioeventfds[i].e;
1444
73bb753d 1445 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF		 1446 event_notifier_set(ioeventfd.e);
1447 return true;
1448 }
1449 }
1450
1451 return false;
1452}
1453
3b643495
PM		 1454MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1455 hwaddr addr,
1456 uint64_t data,
1457 unsigned size,
1458 MemTxAttrs attrs)
a621f38d 1459{
6d7b9a6c 1460 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1461 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1462 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1463 }
1464
a621f38d
AK		 1465 adjust_endianness(mr, &data, size);
1466
8c56c1a5
PF		 1467 if ((!kvm_eventfds_enabled()) &&
1468 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1469 return MEMTX_OK;
1470 }
1471
ce5d2f33 1472 if (mr->ops->write) {
cc05c43a
PM		 1473 return access_with_adjusted_size(addr, &data, size,
1474 mr->ops->impl.min_access_size,
1475 mr->ops->impl.max_access_size,
1476 memory_region_write_accessor, mr,
1477 attrs);
1478 } else if (mr->ops->write_with_attrs) {
1479 return
1480 access_with_adjusted_size(addr, &data, size,
1481 mr->ops->impl.min_access_size,
1482 mr->ops->impl.max_access_size,
1483 memory_region_write_with_attrs_accessor,
1484 mr, attrs);
ce5d2f33 1485 } else {
cc05c43a
PM		 1486 return access_with_adjusted_size(addr, &data, size, 1, 4,
1487 memory_region_oldmmio_write_accessor,
1488 mr, attrs);
74901c3b 1489 }
093bc2cd
AK		 1490}
1491
093bc2cd 1492void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1493 Object *owner,
093bc2cd
AK		 1494 const MemoryRegionOps *ops,
1495 void *opaque,
1496 const char *name,
1497 uint64_t size)
1498{
2c9b15ca 1499 memory_region_init(mr, owner, name, size);
6d6d2abf 1500 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1501 mr->opaque = opaque;
14a3c10a 1502 mr->terminates = true;
093bc2cd
AK		 1503}
1504
1cfe48c1
PM		 1505void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1506 Object *owner,
1507 const char *name,
1508 uint64_t size,
1509 Error **errp)
06329cce
MA		 1510{
1511 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1512}
1513
1514void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1515 Object *owner,
1516 const char *name,
1517 uint64_t size,
1518 bool share,
1519 Error **errp)
093bc2cd 1520{
2c9b15ca 1521 memory_region_init(mr, owner, name, size);
8ea9252a 1522 mr->ram = true;
14a3c10a 1523 mr->terminates = true;
545e92e0 1524 mr->destructor = memory_region_destructor_ram;
06329cce 1525 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
677e7805 1526 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1527}
1528
60786ef3
MT		 1529void memory_region_init_resizeable_ram(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 uint64_t max_size,
1534 void (*resized)(const char*,
1535 uint64_t length,
1536 void *host),
1537 Error **errp)
1538{
1539 memory_region_init(mr, owner, name, size);
1540 mr->ram = true;
1541 mr->terminates = true;
1542 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1543 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1544 mr, errp);
677e7805 1545 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1546}
1547
0b183fc8
PB		 1548#ifdef __linux__
1549void memory_region_init_ram_from_file(MemoryRegion *mr,
1550 struct Object *owner,
1551 const char *name,
1552 uint64_t size,
98376843 1553 uint64_t align,
dbcb8981 1554 bool share,
7f56e740
PB		 1555 const char *path,
1556 Error **errp)
0b183fc8
PB		 1557{
1558 memory_region_init(mr, owner, name, size);
1559 mr->ram = true;
1560 mr->terminates = true;
1561 mr->destructor = memory_region_destructor_ram;
98376843 1562 mr->align = align;
8e41fb63 1563 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1564 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1565}
fea617c5
MAL		 1566
1567void memory_region_init_ram_from_fd(MemoryRegion *mr,
1568 struct Object *owner,
1569 const char *name,
1570 uint64_t size,
1571 bool share,
1572 int fd,
1573 Error **errp)
1574{
1575 memory_region_init(mr, owner, name, size);
1576 mr->ram = true;
1577 mr->terminates = true;
1578 mr->destructor = memory_region_destructor_ram;
1579 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1580 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1581}
0b183fc8 1582#endif
093bc2cd
AK		 1583
1584void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1585 Object *owner,
093bc2cd
AK		 1586 const char *name,
1587 uint64_t size,
1588 void *ptr)
1589{
2c9b15ca 1590 memory_region_init(mr, owner, name, size);
8ea9252a 1591 mr->ram = true;
14a3c10a 1592 mr->terminates = true;
fc3e7665 1593 mr->destructor = memory_region_destructor_ram;
677e7805 1594 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1595
1596 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1597 assert(ptr != NULL);
8e41fb63 1598 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1599}
1600
21e00fa5
AW		 1601void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1602 Object *owner,
1603 const char *name,
1604 uint64_t size,
1605 void *ptr)
e4dc3f59 1606{
21e00fa5
AW		 1607 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1608 mr->ram_device = true;
4a2e242b
AW		 1609 mr->ops = &ram_device_mem_ops;
1610 mr->opaque = mr;
e4dc3f59
ND		 1611}
1612
093bc2cd 1613void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1614 Object *owner,
093bc2cd
AK		 1615 const char *name,
1616 MemoryRegion *orig,
a8170e5e 1617 hwaddr offset,
093bc2cd
AK		 1618 uint64_t size)
1619{
2c9b15ca 1620 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1621 mr->alias = orig;
1622 mr->alias_offset = offset;
1623}
1624
b59821a9
PM		 1625void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1626 struct Object *owner,
1627 const char *name,
1628 uint64_t size,
1629 Error **errp)
a1777f7f
PM		 1630{
1631 memory_region_init(mr, owner, name, size);
1632 mr->ram = true;
1633 mr->readonly = true;
1634 mr->terminates = true;
1635 mr->destructor = memory_region_destructor_ram;
06329cce 1636 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
a1777f7f
PM		 1637 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1638}
1639
b59821a9
PM		 1640void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1641 Object *owner,
1642 const MemoryRegionOps *ops,
1643 void *opaque,
1644 const char *name,
1645 uint64_t size,
1646 Error **errp)
d0a9b5bc 1647{
39e0b03d 1648 assert(ops);
2c9b15ca 1649 memory_region_init(mr, owner, name, size);
7bc2b9cd 1650 mr->ops = ops;
75f5941c 1651 mr->opaque = opaque;
d0a9b5bc 1652 mr->terminates = true;
75c578dc 1653 mr->rom_device = true;
58268c8d 1654 mr->destructor = memory_region_destructor_ram;
06329cce 1655 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
d0a9b5bc
AK		 1656}
1657
1221a474
AK		 1658void memory_region_init_iommu(void *_iommu_mr,
1659 size_t instance_size,
1660 const char *mrtypename,
2c9b15ca 1661 Object *owner,
30951157
AK		 1662 const char *name,
1663 uint64_t size)
1664{
1221a474 1665 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1666 struct MemoryRegion *mr;
1667
1221a474
AK		 1668 object_initialize(_iommu_mr, instance_size, mrtypename);
1669 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1670 memory_region_do_init(mr, owner, name, size);
1671 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1672 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1673 QLIST_INIT(&iommu_mr->iommu_notify);
1674 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1675}
1676
b4fefef9 1677static void memory_region_finalize(Object *obj)
093bc2cd 1678{
b4fefef9
PC		 1679 MemoryRegion *mr = MEMORY_REGION(obj);
1680
2e2b8eb7
PB		 1681 assert(!mr->container);
1682
1683 /* We know the region is not visible in any address space (it
1684 * does not have a container and cannot be a root either because
1685 * it has no references, so we can blindly clear mr->enabled.
1686 * memory_region_set_enabled instead could trigger a transaction
1687 * and cause an infinite loop.
1688 */
1689 mr->enabled = false;
1690 memory_region_transaction_begin();
1691 while (!QTAILQ_EMPTY(&mr->subregions)) {
1692 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1693 memory_region_del_subregion(mr, subregion);
1694 }
1695 memory_region_transaction_commit();
1696
545e92e0 1697 mr->destructor(mr);
093bc2cd 1698 memory_region_clear_coalescing(mr);
302fa283 1699 g_free((char *)mr->name);
7267c094 1700 g_free(mr->ioeventfds);
093bc2cd
AK		 1701}
1702
803c0816
PB		 1703Object *memory_region_owner(MemoryRegion *mr)
1704{
22a893e4
PB		 1705 Object *obj = OBJECT(mr);
1706 return obj->parent;
803c0816
PB		 1707}
1708
46637be2
PB		 1709void memory_region_ref(MemoryRegion *mr)
1710{
22a893e4
PB		 1711 /* MMIO callbacks most likely will access data that belongs
1712 * to the owner, hence the need to ref/unref the owner whenever
1713 * the memory region is in use.
1714 *
1715 * The memory region is a child of its owner. As long as the
1716 * owner doesn't call unparent itself on the memory region,
1717 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1718 * Memory regions without an owner are supposed to never go away;
1719 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1720 */
612263cf
PB		 1721 if (mr && mr->owner) {
1722 object_ref(mr->owner);
46637be2
PB		 1723 }
1724}
1725
1726void memory_region_unref(MemoryRegion *mr)
1727{
612263cf
PB		 1728 if (mr && mr->owner) {
1729 object_unref(mr->owner);
46637be2
PB		 1730 }
1731}
1732
093bc2cd
AK		 1733uint64_t memory_region_size(MemoryRegion *mr)
1734{
08dafab4
AK		 1735 if (int128_eq(mr->size, int128_2_64())) {
1736 return UINT64_MAX;
1737 }
1738 return int128_get64(mr->size);
093bc2cd
AK		 1739}
1740
5d546d4b 1741const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1742{
d1dd32af
PC		 1743 if (!mr->name) {
1744 ((MemoryRegion *)mr)->name =
1745 object_get_canonical_path_component(OBJECT(mr));
1746 }
302fa283 1747 return mr->name;
8991c79b
AK		 1748}
1749
21e00fa5 1750bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1751{
21e00fa5 1752 return mr->ram_device;
e4dc3f59
ND		 1753}
1754
2d1a35be 1755uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1756{
6f6a5ef3 1757 uint8_t mask = mr->dirty_log_mask;
adaad61c 1758 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1759 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1760 }
1761 return mask;
55043ba3
AK		 1762}
1763
2d1a35be
PB		 1764bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1765{
1766 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1767}
1768
3df9d748 1769static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1770{
1771 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1772 IOMMUNotifier *iommu_notifier;
1221a474 1773 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1774
3df9d748 1775 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1776 flags |= iommu_notifier->notifier_flags;
1777 }
1778
1221a474
AK		 1779 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1780 imrc->notify_flag_changed(iommu_mr,
1781 iommu_mr->iommu_notify_flags,
1782 flags);
5bf3d319
PX		 1783 }
1784
3df9d748 1785 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1786}
1787
cdb30812
PX		 1788void memory_region_register_iommu_notifier(MemoryRegion *mr,
1789 IOMMUNotifier *n)
06866575 1790{
3df9d748
AK		 1791 IOMMUMemoryRegion *iommu_mr;
1792
efcd38c5
JW		 1793 if (mr->alias) {
1794 memory_region_register_iommu_notifier(mr->alias, n);
1795 return;
1796 }
1797
cdb30812 1798 /* We need to register for at least one bitfield */
3df9d748 1799 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1800 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1801 assert(n->start <= n->end);
cb1efcf4
PM		 1802 assert(n->iommu_idx >= 0 &&
1803 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1804
3df9d748
AK		 1805 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1806 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1807}
1808
3df9d748 1809uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1810{
1221a474
AK		 1811 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1812
1813 if (imrc->get_min_page_size) {
1814 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1815 }
1816 return TARGET_PAGE_SIZE;
1817}
1818
3df9d748 1819void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1820{
3df9d748 1821 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1822 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1823 hwaddr addr, granularity;
a788f227
DG		 1824 IOMMUTLBEntry iotlb;
1825
faa362e3 1826 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1827 if (imrc->replay) {
1828 imrc->replay(iommu_mr, n);
faa362e3
PX		 1829 return;
1830 }
1831
3df9d748 1832 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1833
a788f227 1834 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1835 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG		 1836 if (iotlb.perm != IOMMU_NONE) {
1837 n->notify(n, &iotlb);
1838 }
1839
1840 /* if (2^64 - MR size) < granularity, it's possible to get an
1841 * infinite loop here. This should catch such a wraparound */
1842 if ((addr + granularity) < addr) {
1843 break;
1844 }
1845 }
1846}
1847
3df9d748 1848void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1849{
1850 IOMMUNotifier *notifier;
1851
3df9d748
AK		 1852 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1853 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1854 }
1855}
1856
cdb30812
PX		 1857void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1858 IOMMUNotifier *n)
06866575 1859{
3df9d748
AK		 1860 IOMMUMemoryRegion *iommu_mr;
1861
efcd38c5
JW		 1862 if (mr->alias) {
1863 memory_region_unregister_iommu_notifier(mr->alias, n);
1864 return;
1865 }
cdb30812 1866 QLIST_REMOVE(n, node);
3df9d748
AK		 1867 iommu_mr = IOMMU_MEMORY_REGION(mr);
1868 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1869}
1870
bd2bfa4c
PX		 1871void memory_region_notify_one(IOMMUNotifier *notifier,
1872 IOMMUTLBEntry *entry)
06866575 1873{
cdb30812
PX		 1874 IOMMUNotifierFlag request_flags;
1875
bd2bfa4c
PX		 1876 /*
1877 * Skip the notification if the notification does not overlap
1878 * with registered range.
1879 */
b021d1c0 1880 if (notifier->start > entry->iova + entry->addr_mask ||
bd2bfa4c
PX		 1881 notifier->end < entry->iova) {
1882 return;
1883 }
cdb30812 1884
bd2bfa4c 1885 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1886 request_flags = IOMMU_NOTIFIER_MAP;
1887 } else {
1888 request_flags = IOMMU_NOTIFIER_UNMAP;
1889 }
1890
bd2bfa4c
PX		 1891 if (notifier->notifier_flags & request_flags) {
1892 notifier->notify(notifier, entry);
1893 }
1894}
1895
3df9d748 1896void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1897 int iommu_idx,
bd2bfa4c
PX		 1898 IOMMUTLBEntry entry)
1899{
1900 IOMMUNotifier *iommu_notifier;
1901
3df9d748 1902 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1903
3df9d748 1904 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM		 1905 if (iommu_notifier->iommu_idx == iommu_idx) {
1906 memory_region_notify_one(iommu_notifier, &entry);
1907 }
cdb30812 1908 }
06866575
DG		 1909}
1910
f1334de6
AK		 1911int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1912 enum IOMMUMemoryRegionAttr attr,
1913 void *data)
1914{
1915 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1916
1917 if (!imrc->get_attr) {
1918 return -EINVAL;
1919 }
1920
1921 return imrc->get_attr(iommu_mr, attr, data);
1922}
1923
21f40209
PM		 1924int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1925 MemTxAttrs attrs)
1926{
1927 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1928
1929 if (!imrc->attrs_to_index) {
1930 return 0;
1931 }
1932
1933 return imrc->attrs_to_index(iommu_mr, attrs);
1934}
1935
1936int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1937{
1938 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1939
1940 if (!imrc->num_indexes) {
1941 return 1;
1942 }
1943
1944 return imrc->num_indexes(iommu_mr);
1945}
1946
093bc2cd
AK		 1947void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1948{
5a583347 1949 uint8_t mask = 1 << client;
deb809ed 1950 uint8_t old_logging;
5a583347 1951
dbddac6d 1952 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1953 old_logging = mr->vga_logging_count;
1954 mr->vga_logging_count += log ? 1 : -1;
1955 if (!!old_logging == !!mr->vga_logging_count) {
1956 return;
1957 }
1958
59023ef4 1959 memory_region_transaction_begin();
5a583347 1960 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1961 memory_region_update_pending |= mr->enabled;
59023ef4 1962 memory_region_transaction_commit();
093bc2cd
AK		 1963}
1964
a8170e5e
AK		 1965bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1966 hwaddr size, unsigned client)
093bc2cd 1967{
8e41fb63
FZ		 1968 assert(mr->ram_block);
1969 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1970 size, client);
093bc2cd
AK		 1971}
1972
a8170e5e
AK		 1973void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1974 hwaddr size)
093bc2cd 1975{
8e41fb63
FZ		 1976 assert(mr->ram_block);
1977 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1978 size,
58d2707e 1979 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1980}
1981
0fe1eca7 1982static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 1983{
0a752eee 1984 MemoryListener *listener;
0d673e36 1985 AddressSpace *as;
0a752eee 1986 FlatView *view;
5a583347
AK		 1987 FlatRange *fr;
1988
0a752eee
PB		 1989 /* If the same address space has multiple log_sync listeners, we
1990 * visit that address space's FlatView multiple times. But because
1991 * log_sync listeners are rare, it's still cheaper than walking each
1992 * address space once.
1993 */
1994 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1995 if (!listener->log_sync) {
1996 continue;
1997 }
1998 as = listener->address_space;
1999 view = address_space_get_flatview(as);
99e86347 2000 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2001 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2002 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2003 listener->log_sync(listener, &mrs);
0d673e36 2004 }
5a583347 2005 }
856d7245 2006 flatview_unref(view);
5a583347 2007 }
093bc2cd
AK		 2008}
2009
0fe1eca7
PB		 2010DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2011 hwaddr addr,
2012 hwaddr size,
2013 unsigned client)
2014{
2015 assert(mr->ram_block);
2016 memory_region_sync_dirty_bitmap(mr);
2017 return cpu_physical_memory_snapshot_and_clear_dirty(
2018 memory_region_get_ram_addr(mr) + addr, size, client);
2019}
2020
2021bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2022 hwaddr addr, hwaddr size)
2023{
2024 assert(mr->ram_block);
2025 return cpu_physical_memory_snapshot_get_dirty(snap,
2026 memory_region_get_ram_addr(mr) + addr, size);
2027}
2028
093bc2cd
AK		 2029void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2030{
fb1cd6f9 2031 if (mr->readonly != readonly) {
59023ef4 2032 memory_region_transaction_begin();
fb1cd6f9 2033 mr->readonly = readonly;
22bde714 2034 memory_region_update_pending |= mr->enabled;
59023ef4 2035 memory_region_transaction_commit();
fb1cd6f9 2036 }
093bc2cd
AK		 2037}
2038
5f9a5ea1 2039void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2040{
5f9a5ea1 2041 if (mr->romd_mode != romd_mode) {
59023ef4 2042 memory_region_transaction_begin();
5f9a5ea1 2043 mr->romd_mode = romd_mode;
22bde714 2044 memory_region_update_pending |= mr->enabled;
59023ef4 2045 memory_region_transaction_commit();
d0a9b5bc
AK		 2046 }
2047}
2048
a8170e5e
AK		 2049void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2050 hwaddr size, unsigned client)
093bc2cd 2051{
8e41fb63
FZ		 2052 assert(mr->ram_block);
2053 cpu_physical_memory_test_and_clear_dirty(
2054 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 2055}
2056
a35ba7be
PB		 2057int memory_region_get_fd(MemoryRegion *mr)
2058{
4ff87573
PB		 2059 int fd;
2060
2061 rcu_read_lock();
2062 while (mr->alias) {
2063 mr = mr->alias;
a35ba7be 2064 }
4ff87573
PB		 2065 fd = mr->ram_block->fd;
2066 rcu_read_unlock();
a35ba7be 2067
4ff87573
PB		 2068 return fd;
2069}
a35ba7be 2070
093bc2cd
AK		 2071void *memory_region_get_ram_ptr(MemoryRegion *mr)
2072{
49b24afc
PB		 2073 void *ptr;
2074 uint64_t offset = 0;
093bc2cd 2075
49b24afc
PB		 2076 rcu_read_lock();
2077 while (mr->alias) {
2078 offset += mr->alias_offset;
2079 mr = mr->alias;
2080 }
8e41fb63 2081 assert(mr->ram_block);
0878d0e1 2082 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2083 rcu_read_unlock();
093bc2cd 2084
0878d0e1 2085 return ptr;
093bc2cd
AK		 2086}
2087
07bdaa41
PB		 2088MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2089{
2090 RAMBlock *block;
2091
2092 block = qemu_ram_block_from_host(ptr, false, offset);
2093 if (!block) {
2094 return NULL;
2095 }
2096
2097 return block->mr;
2098}
2099
7ebb2745
FZ		 2100ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2101{
2102 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2103}
2104
37d7c084
PB		 2105void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2106{
8e41fb63 2107 assert(mr->ram_block);
37d7c084 2108
fa53a0e5 2109 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 2110}
2111
0d673e36 2112static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2113{
99e86347 2114 FlatView *view;
093bc2cd
AK		 2115 FlatRange *fr;
2116 CoalescedMemoryRange *cmr;
2117 AddrRange tmp;
95d2994a 2118 MemoryRegionSection section;
093bc2cd 2119
856d7245 2120 view = address_space_get_flatview(as);
99e86347 2121 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2122 if (fr->mr == mr) {
95d2994a 2123 section = (MemoryRegionSection) {
16620684 2124 .fv = view,
95d2994a 2125 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2126 .size = fr->addr.size,
95d2994a
AK		 2127 };
2128
9a54635d 2129 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 2130 int128_get64(fr->addr.start),
2131 int128_get64(fr->addr.size));
093bc2cd
AK		 2132 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2133 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 2134 int128_sub(fr->addr.start,
2135 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 2136 if (!addrrange_intersects(tmp, fr->addr)) {
2137 continue;
2138 }
2139 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2140 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 2141 int128_get64(tmp.start),
2142 int128_get64(tmp.size));
093bc2cd
AK		 2143 }
2144 }
2145 }
856d7245 2146 flatview_unref(view);
093bc2cd
AK		 2147}
2148
0d673e36
AK		 2149static void memory_region_update_coalesced_range(MemoryRegion *mr)
2150{
2151 AddressSpace *as;
2152
2153 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2154 memory_region_update_coalesced_range_as(mr, as);
2155 }
2156}
2157
093bc2cd
AK		 2158void memory_region_set_coalescing(MemoryRegion *mr)
2159{
2160 memory_region_clear_coalescing(mr);
08dafab4 2161 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2162}
2163
2164void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2165 hwaddr offset,
093bc2cd
AK		 2166 uint64_t size)
2167{
7267c094 2168 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2169
08dafab4 2170 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 2171 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2172 memory_region_update_coalesced_range(mr);
d410515e 2173 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2174}
2175
2176void memory_region_clear_coalescing(MemoryRegion *mr)
2177{
2178 CoalescedMemoryRange *cmr;
ab5b3db5 2179 bool updated = false;
093bc2cd 2180
d410515e
JK		 2181 qemu_flush_coalesced_mmio_buffer();
2182 mr->flush_coalesced_mmio = false;
2183
093bc2cd
AK		 2184 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2185 cmr = QTAILQ_FIRST(&mr->coalesced);
2186 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2187 g_free(cmr);
ab5b3db5
FZ		 2188 updated = true;
2189 }
2190
2191 if (updated) {
2192 memory_region_update_coalesced_range(mr);
093bc2cd 2193 }
093bc2cd
AK		 2194}
2195
d410515e
JK		 2196void memory_region_set_flush_coalesced(MemoryRegion *mr)
2197{
2198 mr->flush_coalesced_mmio = true;
2199}
2200
2201void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2202{
2203 qemu_flush_coalesced_mmio_buffer();
2204 if (QTAILQ_EMPTY(&mr->coalesced)) {
2205 mr->flush_coalesced_mmio = false;
2206 }
2207}
2208
196ea131
JK		 2209void memory_region_clear_global_locking(MemoryRegion *mr)
2210{
2211 mr->global_locking = false;
2212}
2213
8c56c1a5
PF		 2214static bool userspace_eventfd_warning;
2215
3e9d69e7 2216void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2217 hwaddr addr,
3e9d69e7
AK		 2218 unsigned size,
2219 bool match_data,
2220 uint64_t data,
753d5e14 2221 EventNotifier *e)
3e9d69e7
AK		 2222{
2223 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2224 .addr.start = int128_make64(addr),
2225 .addr.size = int128_make64(size),
3e9d69e7
AK		 2226 .match_data = match_data,
2227 .data = data,
753d5e14 2228 .e = e,
3e9d69e7
AK		 2229 };
2230 unsigned i;
2231
8c56c1a5
PF		 2232 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2233 userspace_eventfd_warning))) {
2234 userspace_eventfd_warning = true;
2235 error_report("Using eventfd without MMIO binding in KVM. "
2236 "Suboptimal performance expected");
2237 }
2238
b8aecea2
JW		 2239 if (size) {
2240 adjust_endianness(mr, &mrfd.data, size);
2241 }
59023ef4 2242 memory_region_transaction_begin();
3e9d69e7 2243 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2244 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK		 2245 break;
2246 }
2247 }
2248 ++mr->ioeventfd_nb;
7267c094 2249 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2250 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2251 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2252 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2253 mr->ioeventfds[i] = mrfd;
4dc56152 2254 ioeventfd_update_pending |= mr->enabled;
59023ef4 2255 memory_region_transaction_commit();
3e9d69e7
AK		 2256}
2257
2258void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2259 hwaddr addr,
3e9d69e7
AK		 2260 unsigned size,
2261 bool match_data,
2262 uint64_t data,
753d5e14 2263 EventNotifier *e)
3e9d69e7
AK		 2264{
2265 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2266 .addr.start = int128_make64(addr),
2267 .addr.size = int128_make64(size),
3e9d69e7
AK		 2268 .match_data = match_data,
2269 .data = data,
753d5e14 2270 .e = e,
3e9d69e7
AK		 2271 };
2272 unsigned i;
2273
b8aecea2
JW		 2274 if (size) {
2275 adjust_endianness(mr, &mrfd.data, size);
2276 }
59023ef4 2277 memory_region_transaction_begin();
3e9d69e7 2278 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2279 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK		 2280 break;
2281 }
2282 }
2283 assert(i != mr->ioeventfd_nb);
2284 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2285 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2286 --mr->ioeventfd_nb;
7267c094 2287 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2288 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2289 ioeventfd_update_pending |= mr->enabled;
59023ef4 2290 memory_region_transaction_commit();
3e9d69e7
AK		 2291}
2292
feca4ac1 2293static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2294{
feca4ac1 2295 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2296 MemoryRegion *other;
2297
59023ef4
JK		 2298 memory_region_transaction_begin();
2299
dfde4e6e 2300 memory_region_ref(subregion);
093bc2cd
AK		 2301 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2302 if (subregion->priority >= other->priority) {
2303 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2304 goto done;
2305 }
2306 }
2307 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2308done:
22bde714 2309 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2310 memory_region_transaction_commit();
093bc2cd
AK		 2311}
2312
0598701a
PC		 2313static void memory_region_add_subregion_common(MemoryRegion *mr,
2314 hwaddr offset,
2315 MemoryRegion *subregion)
2316{
feca4ac1
PB		 2317 assert(!subregion->container);
2318 subregion->container = mr;
0598701a 2319 subregion->addr = offset;
feca4ac1 2320 memory_region_update_container_subregions(subregion);
0598701a 2321}
093bc2cd
AK		 2322
2323void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2324 hwaddr offset,
093bc2cd
AK		 2325 MemoryRegion *subregion)
2326{
093bc2cd
AK		 2327 subregion->priority = 0;
2328 memory_region_add_subregion_common(mr, offset, subregion);
2329}
2330
2331void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2332 hwaddr offset,
093bc2cd 2333 MemoryRegion *subregion,
a1ff8ae0 2334 int priority)
093bc2cd 2335{
093bc2cd
AK		 2336 subregion->priority = priority;
2337 memory_region_add_subregion_common(mr, offset, subregion);
2338}
2339
2340void memory_region_del_subregion(MemoryRegion *mr,
2341 MemoryRegion *subregion)
2342{
59023ef4 2343 memory_region_transaction_begin();
feca4ac1
PB		 2344 assert(subregion->container == mr);
2345 subregion->container = NULL;
093bc2cd 2346 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2347 memory_region_unref(subregion);
22bde714 2348 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2349 memory_region_transaction_commit();
6bba19ba
AK		 2350}
2351
2352void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2353{
2354 if (enabled == mr->enabled) {
2355 return;
2356 }
59023ef4 2357 memory_region_transaction_begin();
6bba19ba 2358 mr->enabled = enabled;
22bde714 2359 memory_region_update_pending = true;
59023ef4 2360 memory_region_transaction_commit();
093bc2cd 2361}
1c0ffa58 2362
e7af4c67
MT		 2363void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2364{
2365 Int128 s = int128_make64(size);
2366
2367 if (size == UINT64_MAX) {
2368 s = int128_2_64();
2369 }
2370 if (int128_eq(s, mr->size)) {
2371 return;
2372 }
2373 memory_region_transaction_begin();
2374 mr->size = s;
2375 memory_region_update_pending = true;
2376 memory_region_transaction_commit();
2377}
2378
67891b8a 2379static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2380{
feca4ac1 2381 MemoryRegion *container = mr->container;
2282e1af 2382
feca4ac1 2383 if (container) {
67891b8a
PC		 2384 memory_region_transaction_begin();
2385 memory_region_ref(mr);
feca4ac1
PB		 2386 memory_region_del_subregion(container, mr);
2387 mr->container = container;
2388 memory_region_update_container_subregions(mr);
67891b8a
PC		 2389 memory_region_unref(mr);
2390 memory_region_transaction_commit();
2282e1af 2391 }
67891b8a 2392}
2282e1af 2393
67891b8a
PC		 2394void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2395{
2396 if (addr != mr->addr) {
2397 mr->addr = addr;
2398 memory_region_readd_subregion(mr);
2399 }
2282e1af
AK		 2400}
2401
a8170e5e 2402void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2403{
4703359e 2404 assert(mr->alias);
4703359e 2405
59023ef4 2406 if (offset == mr->alias_offset) {
4703359e
AK		 2407 return;
2408 }
2409
59023ef4
JK		 2410 memory_region_transaction_begin();
2411 mr->alias_offset = offset;
22bde714 2412 memory_region_update_pending |= mr->enabled;
59023ef4 2413 memory_region_transaction_commit();
4703359e
AK		 2414}
2415
a2b257d6
IM		 2416uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2417{
2418 return mr->align;
2419}
2420
e2177955
AK		 2421static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2422{
2423 const AddrRange *addr = addr_;
2424 const FlatRange *fr = fr_;
2425
2426 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2427 return -1;
2428 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2429 return 1;
2430 }
2431 return 0;
2432}
2433
99e86347 2434static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2435{
99e86347 2436 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2437 sizeof(FlatRange), cmp_flatrange_addr);
2438}
2439
eed2bacf
IM		 2440bool memory_region_is_mapped(MemoryRegion *mr)
2441{
2442 return mr->container ? true : false;
2443}
2444
c6742b14
PB		 2445/* Same as memory_region_find, but it does not add a reference to the
2446 * returned region. It must be called from an RCU critical section.
2447 */
2448static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2449 hwaddr addr, uint64_t size)
e2177955 2450{
052e87b0 2451 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2452 MemoryRegion *root;
2453 AddressSpace *as;
2454 AddrRange range;
99e86347 2455 FlatView *view;
73034e9e
PB		 2456 FlatRange *fr;
2457
2458 addr += mr->addr;
feca4ac1
PB		 2459 for (root = mr; root->container; ) {
2460 root = root->container;
73034e9e
PB		 2461 addr += root->addr;
2462 }
e2177955 2463
73034e9e 2464 as = memory_region_to_address_space(root);
eed2bacf
IM		 2465 if (!as) {
2466 return ret;
2467 }
73034e9e 2468 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2469
16620684 2470 view = address_space_to_flatview(as);
99e86347 2471 fr = flatview_lookup(view, range);
e2177955 2472 if (!fr) {
c6742b14 2473 return ret;
e2177955
AK		 2474 }
2475
99e86347 2476 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2477 --fr;
2478 }
2479
2480 ret.mr = fr->mr;
16620684 2481 ret.fv = view;
e2177955
AK		 2482 range = addrrange_intersection(range, fr->addr);
2483 ret.offset_within_region = fr->offset_in_region;
2484 ret.offset_within_region += int128_get64(int128_sub(range.start,
2485 fr->addr.start));
052e87b0 2486 ret.size = range.size;
e2177955 2487 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2488 ret.readonly = fr->readonly;
c6742b14
PB		 2489 return ret;
2490}
2491
2492MemoryRegionSection memory_region_find(MemoryRegion *mr,
2493 hwaddr addr, uint64_t size)
2494{
2495 MemoryRegionSection ret;
2496 rcu_read_lock();
2497 ret = memory_region_find_rcu(mr, addr, size);
2498 if (ret.mr) {
2499 memory_region_ref(ret.mr);
2500 }
2b647668 2501 rcu_read_unlock();
e2177955
AK		 2502 return ret;
2503}
2504
c6742b14
PB		 2505bool memory_region_present(MemoryRegion *container, hwaddr addr)
2506{
2507 MemoryRegion *mr;
2508
2509 rcu_read_lock();
2510 mr = memory_region_find_rcu(container, addr, 1).mr;
2511 rcu_read_unlock();
2512 return mr && mr != container;
2513}
2514
9c1f8f44 2515void memory_global_dirty_log_sync(void)
86e775c6 2516{
3ebb1817 2517 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK		 2518}
2519
19310760
JZ		 2520static VMChangeStateEntry *vmstate_change;
2521
7664e80c
AK		 2522void memory_global_dirty_log_start(void)
2523{
19310760
JZ		 2524 if (vmstate_change) {
2525 qemu_del_vm_change_state_handler(vmstate_change);
2526 vmstate_change = NULL;
2527 }
2528
7664e80c 2529 global_dirty_log = true;
6f6a5ef3 2530
7376e582 2531 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2532
2533 /* Refresh DIRTY_LOG_MIGRATION bit. */
2534 memory_region_transaction_begin();
2535 memory_region_update_pending = true;
2536 memory_region_transaction_commit();
7664e80c
AK		 2537}
2538
19310760 2539static void memory_global_dirty_log_do_stop(void)
7664e80c 2540{
7664e80c 2541 global_dirty_log = false;
6f6a5ef3
PB		 2542
2543 /* Refresh DIRTY_LOG_MIGRATION bit. */
2544 memory_region_transaction_begin();
2545 memory_region_update_pending = true;
2546 memory_region_transaction_commit();
2547
7376e582 2548 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2549}
2550
19310760
JZ		 2551static void memory_vm_change_state_handler(void *opaque, int running,
2552 RunState state)
2553{
2554 if (running) {
2555 memory_global_dirty_log_do_stop();
2556
2557 if (vmstate_change) {
2558 qemu_del_vm_change_state_handler(vmstate_change);
2559 vmstate_change = NULL;
2560 }
2561 }
2562}
2563
2564void memory_global_dirty_log_stop(void)
2565{
2566 if (!runstate_is_running()) {
2567 if (vmstate_change) {
2568 return;
2569 }
2570 vmstate_change = qemu_add_vm_change_state_handler(
2571 memory_vm_change_state_handler, NULL);
2572 return;
2573 }
2574
2575 memory_global_dirty_log_do_stop();
2576}
2577
7664e80c
AK		 2578static void listener_add_address_space(MemoryListener *listener,
2579 AddressSpace *as)
2580{
99e86347 2581 FlatView *view;
7664e80c
AK		 2582 FlatRange *fr;
2583
680a4783
PB		 2584 if (listener->begin) {
2585 listener->begin(listener);
2586 }
7664e80c 2587 if (global_dirty_log) {
975aefe0
AK		 2588 if (listener->log_global_start) {
2589 listener->log_global_start(listener);
2590 }
7664e80c 2591 }
975aefe0 2592
856d7245 2593 view = address_space_get_flatview(as);
99e86347 2594 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH		 2595 MemoryRegionSection section = section_from_flat_range(fr, view);
2596
975aefe0
AK		 2597 if (listener->region_add) {
2598 listener->region_add(listener, &section);
2599 }
ae990e6c
DH		 2600 if (fr->dirty_log_mask && listener->log_start) {
2601 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2602 }
7664e80c 2603 }
680a4783
PB		 2604 if (listener->commit) {
2605 listener->commit(listener);
2606 }
856d7245 2607 flatview_unref(view);
7664e80c
AK		 2608}
2609
d25836ca
PX		 2610static void listener_del_address_space(MemoryListener *listener,
2611 AddressSpace *as)
2612{
2613 FlatView *view;
2614 FlatRange *fr;
2615
2616 if (listener->begin) {
2617 listener->begin(listener);
2618 }
2619 view = address_space_get_flatview(as);
2620 FOR_EACH_FLAT_RANGE(fr, view) {
2621 MemoryRegionSection section = section_from_flat_range(fr, view);
2622
2623 if (fr->dirty_log_mask && listener->log_stop) {
2624 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2625 }
2626 if (listener->region_del) {
2627 listener->region_del(listener, &section);
2628 }
2629 }
2630 if (listener->commit) {
2631 listener->commit(listener);
2632 }
2633 flatview_unref(view);
2634}
2635
d45fa784 2636void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2637{
72e22d2f
AK		 2638 MemoryListener *other = NULL;
2639
d45fa784 2640 listener->address_space = as;
72e22d2f
AK		 2641 if (QTAILQ_EMPTY(&memory_listeners)
2642 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2643 memory_listeners)->priority) {
2644 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2645 } else {
2646 QTAILQ_FOREACH(other, &memory_listeners, link) {
2647 if (listener->priority < other->priority) {
2648 break;
2649 }
2650 }
2651 QTAILQ_INSERT_BEFORE(other, listener, link);
2652 }
0d673e36 2653
9a54635d
PB		 2654 if (QTAILQ_EMPTY(&as->listeners)
2655 || listener->priority >= QTAILQ_LAST(&as->listeners,
2656 memory_listeners)->priority) {
2657 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2658 } else {
2659 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2660 if (listener->priority < other->priority) {
2661 break;
2662 }
2663 }
2664 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2665 }
2666
d45fa784 2667 listener_add_address_space(listener, as);
7664e80c
AK		 2668}
2669
2670void memory_listener_unregister(MemoryListener *listener)
2671{
1d8280c1
PB		 2672 if (!listener->address_space) {
2673 return;
2674 }
2675
d25836ca 2676 listener_del_address_space(listener, listener->address_space);
72e22d2f 2677 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2678 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2679 listener->address_space = NULL;
86e775c6 2680}
e2177955 2681
c9356746
FK		 2682bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2683{
2684 void *host;
2685 unsigned size = 0;
2686 unsigned offset = 0;
2687 Object *new_interface;
2688
2689 if (!mr || !mr->ops->request_ptr) {
2690 return false;
2691 }
2692
2693 /*
2694 * Avoid an update if the request_ptr call
2695 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2696 * a cache.
2697 */
2698 memory_region_transaction_begin();
2699
2700 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2701
2702 if (!host || !size) {
2703 memory_region_transaction_commit();
2704 return false;
2705 }
2706
2707 new_interface = object_new("mmio_interface");
2708 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2709 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2710 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2711 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2712 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2713 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2714
2715 memory_region_transaction_commit();
2716 return true;
2717}
2718
2719typedef struct MMIOPtrInvalidate {
2720 MemoryRegion *mr;
2721 hwaddr offset;
2722 unsigned size;
2723 int busy;
2724 int allocated;
2725} MMIOPtrInvalidate;
2726
2727#define MAX_MMIO_INVALIDATE 10
2728static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2729
2730static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2731 run_on_cpu_data data)
2732{
2733 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2734 MemoryRegion *mr = invalidate_data->mr;
2735 hwaddr offset = invalidate_data->offset;
2736 unsigned size = invalidate_data->size;
2737 MemoryRegionSection section = memory_region_find(mr, offset, size);
2738
2739 qemu_mutex_lock_iothread();
2740
2741 /* Reset dirty so this doesn't happen later. */
2742 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2743
2744 if (section.mr != mr) {
2745 /* memory_region_find add a ref on section.mr */
2746 memory_region_unref(section.mr);
2747 if (MMIO_INTERFACE(section.mr->owner)) {
2748 /* We found the interface just drop it. */
2749 object_property_set_bool(section.mr->owner, false, "realized",
2750 NULL);
2751 object_unref(section.mr->owner);
2752 object_unparent(section.mr->owner);
2753 }
2754 }
2755
2756 qemu_mutex_unlock_iothread();
2757
2758 if (invalidate_data->allocated) {
2759 g_free(invalidate_data);
2760 } else {
2761 invalidate_data->busy = 0;
2762 }
2763}
2764
2765void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2766 unsigned size)
2767{
2768 size_t i;
2769 MMIOPtrInvalidate *invalidate_data = NULL;
2770
2771 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2772 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2773 invalidate_data = &mmio_ptr_invalidate_list[i];
2774 break;
2775 }
2776 }
2777
2778 if (!invalidate_data) {
2779 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2780 invalidate_data->allocated = 1;
2781 }
2782
2783 invalidate_data->mr = mr;
2784 invalidate_data->offset = offset;
2785 invalidate_data->size = size;
2786
2787 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2788 RUN_ON_CPU_HOST_PTR(invalidate_data));
2789}
2790
7dca8043 2791void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2792{
ac95190e 2793 memory_region_ref(root);
8786db7c 2794 as->root = root;
67ace39b 2795 as->current_map = NULL;
4c19eb72
AK		 2796 as->ioeventfd_nb = 0;
2797 as->ioeventfds = NULL;
9a54635d 2798 QTAILQ_INIT(&as->listeners);
0d673e36 2799 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2800 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK		 2801 address_space_update_topology(as);
2802 address_space_update_ioeventfds(as);
1c0ffa58 2803}
658b2224 2804
374f2981 2805static void do_address_space_destroy(AddressSpace *as)
83f3c251 2806{
9a54635d 2807 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2808
856d7245 2809 flatview_unref(as->current_map);
7dca8043 2810 g_free(as->name);
4c19eb72 2811 g_free(as->ioeventfds);
ac95190e 2812 memory_region_unref(as->root);
83f3c251
AK		 2813}
2814
374f2981
PB		 2815void address_space_destroy(AddressSpace *as)
2816{
ac95190e
PB		 2817 MemoryRegion *root = as->root;
2818
374f2981
PB		 2819 /* Flush out anything from MemoryListeners listening in on this */
2820 memory_region_transaction_begin();
2821 as->root = NULL;
2822 memory_region_transaction_commit();
2823 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2824
2825 /* At this point, as->dispatch and as->current_map are dummy
2826 * entries that the guest should never use. Wait for the old
2827 * values to expire before freeing the data.
2828 */
ac95190e 2829 as->root = root;
374f2981
PB		 2830 call_rcu(as, do_address_space_destroy, rcu);
2831}
2832
4e831901
PX		 2833static const char *memory_region_type(MemoryRegion *mr)
2834{
2835 if (memory_region_is_ram_device(mr)) {
2836 return "ramd";
2837 } else if (memory_region_is_romd(mr)) {
2838 return "romd";
2839 } else if (memory_region_is_rom(mr)) {
2840 return "rom";
2841 } else if (memory_region_is_ram(mr)) {
2842 return "ram";
2843 } else {
2844 return "i/o";
2845 }
2846}
2847
314e2987
BS		 2848typedef struct MemoryRegionList MemoryRegionList;
2849
2850struct MemoryRegionList {
2851 const MemoryRegion *mr;
a16878d2 2852 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 2853};
2854
a16878d2 2855typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2856
4e831901
PX		 2857#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2858 int128_sub((size), int128_one())) : 0)
2859#define MTREE_INDENT " "
2860
314e2987
BS		 2861static void mtree_print_mr(fprintf_function mon_printf, void *f,
2862 const MemoryRegion *mr, unsigned int level,
a8170e5e 2863 hwaddr base,
9479c57a 2864 MemoryRegionListHead *alias_print_queue)
314e2987 2865{
9479c57a
JK		 2866 MemoryRegionList *new_ml, *ml, *next_ml;
2867 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2868 const MemoryRegion *submr;
2869 unsigned int i;
b31f8412 2870 hwaddr cur_start, cur_end;
314e2987 2871
f8a9f720 2872 if (!mr) {
314e2987
BS		 2873 return;
2874 }
2875
2876 for (i = 0; i < level; i++) {
4e831901 2877 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2878 }
2879
b31f8412
PX		 2880 cur_start = base + mr->addr;
2881 cur_end = cur_start + MR_SIZE(mr->size);
2882
2883 /*
2884 * Try to detect overflow of memory region. This should never
2885 * happen normally. When it happens, we dump something to warn the
2886 * user who is observing this.
2887 */
2888 if (cur_start < base || cur_end < cur_start) {
2889 mon_printf(f, "[DETECTED OVERFLOW!] ");
2890 }
2891
314e2987
BS		 2892 if (mr->alias) {
2893 MemoryRegionList *ml;
2894 bool found = false;
2895
2896 /* check if the alias is already in the queue */
a16878d2 2897 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2898 if (ml->mr == mr->alias) {
314e2987
BS		 2899 found = true;
2900 }
2901 }
2902
2903 if (!found) {
2904 ml = g_new(MemoryRegionList, 1);
2905 ml->mr = mr->alias;
a16878d2 2906 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2907 }
4896d74b 2908 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2909 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2910 "-" TARGET_FMT_plx "%s\n",
b31f8412 2911 cur_start, cur_end,
4b474ba7 2912 mr->priority,
4e831901 2913 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2914 memory_region_name(mr),
2915 memory_region_name(mr->alias),
314e2987 2916 mr->alias_offset,
4e831901 2917 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2918 mr->enabled ? "" : " [disabled]");
314e2987 2919 } else {
4896d74b 2920 mon_printf(f,
4e831901 2921 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2922 cur_start, cur_end,
4b474ba7 2923 mr->priority,
4e831901 2924 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2925 memory_region_name(mr),
2926 mr->enabled ? "" : " [disabled]");
314e2987 2927 }
9479c57a
JK		 2928
2929 QTAILQ_INIT(&submr_print_queue);
2930
314e2987 2931 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2932 new_ml = g_new(MemoryRegionList, 1);
2933 new_ml->mr = submr;
a16878d2 2934 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 2935 if (new_ml->mr->addr < ml->mr->addr ||
2936 (new_ml->mr->addr == ml->mr->addr &&
2937 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2938 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 2939 new_ml = NULL;
2940 break;
2941 }
2942 }
2943 if (new_ml) {
a16878d2 2944 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 2945 }
2946 }
2947
a16878d2 2948 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2949 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2950 alias_print_queue);
2951 }
2952
a16878d2 2953 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2954 g_free(ml);
314e2987
BS		 2955 }
2956}
2957
5e8fd947
AK		 2958struct FlatViewInfo {
2959 fprintf_function mon_printf;
2960 void *f;
2961 int counter;
2962 bool dispatch_tree;
2963};
2964
2965static void mtree_print_flatview(gpointer key, gpointer value,
2966 gpointer user_data)
57bb40c9 2967{
5e8fd947
AK		 2968 FlatView *view = key;
2969 GArray *fv_address_spaces = value;
2970 struct FlatViewInfo *fvi = user_data;
2971 fprintf_function p = fvi->mon_printf;
2972 void *f = fvi->f;
57bb40c9
PX		 2973 FlatRange *range = &view->ranges[0];
2974 MemoryRegion *mr;
2975 int n = view->nr;
5e8fd947
AK		 2976 int i;
2977 AddressSpace *as;
2978
2979 p(f, "FlatView #%d\n", fvi->counter);
2980 ++fvi->counter;
2981
2982 for (i = 0; i < fv_address_spaces->len; ++i) {
2983 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2984 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2985 if (as->root->alias) {
2986 p(f, ", alias %s", memory_region_name(as->root->alias));
2987 }
2988 p(f, "\n");
2989 }
2990
2991 p(f, " Root memory region: %s\n",
2992 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX		 2993
2994 if (n <= 0) {
5e8fd947 2995 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX		 2996 return;
2997 }
2998
2999 while (n--) {
3000 mr = range->mr;
377a07aa
PB		 3001 if (range->offset_in_region) {
3002 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3003 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
3004 int128_get64(range->addr.start),
3005 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3006 mr->priority,
3007 range->readonly ? "rom" : memory_region_type(mr),
3008 memory_region_name(mr),
3009 range->offset_in_region);
3010 } else {
3011 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3012 TARGET_FMT_plx " (prio %d, %s): %s\n",
3013 int128_get64(range->addr.start),
3014 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3015 mr->priority,
3016 range->readonly ? "rom" : memory_region_type(mr),
3017 memory_region_name(mr));
3018 }
57bb40c9
PX		 3019 range++;
3020 }
3021
5e8fd947
AK		 3022#if !defined(CONFIG_USER_ONLY)
3023 if (fvi->dispatch_tree && view->root) {
3024 mtree_print_dispatch(p, f, view->dispatch, view->root);
3025 }
3026#endif
3027
3028 p(f, "\n");
3029}
3030
3031static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3032 gpointer user_data)
3033{
3034 FlatView *view = key;
3035 GArray *fv_address_spaces = value;
3036
3037 g_array_unref(fv_address_spaces);
57bb40c9 3038 flatview_unref(view);
5e8fd947
AK		 3039
3040 return true;
57bb40c9
PX		 3041}
3042
5e8fd947
AK		 3043void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3044 bool dispatch_tree)
314e2987
BS		 3045{
3046 MemoryRegionListHead ml_head;
3047 MemoryRegionList *ml, *ml2;
0d673e36 3048 AddressSpace *as;
314e2987 3049
57bb40c9 3050 if (flatview) {
5e8fd947
AK		 3051 FlatView *view;
3052 struct FlatViewInfo fvi = {
3053 .mon_printf = mon_printf,
3054 .f = f,
3055 .counter = 0,
3056 .dispatch_tree = dispatch_tree
3057 };
3058 GArray *fv_address_spaces;
3059 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3060
3061 /* Gather all FVs in one table */
57bb40c9 3062 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK		 3063 view = address_space_get_flatview(as);
3064
3065 fv_address_spaces = g_hash_table_lookup(views, view);
3066 if (!fv_address_spaces) {
3067 fv_address_spaces = g_array_new(false, false, sizeof(as));
3068 g_hash_table_insert(views, view, fv_address_spaces);
3069 }
3070
3071 g_array_append_val(fv_address_spaces, as);
57bb40c9 3072 }
5e8fd947
AK		 3073
3074 /* Print */
3075 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3076
3077 /* Free */
3078 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3079 g_hash_table_unref(views);
3080
57bb40c9
PX		 3081 return;
3082 }
3083
314e2987
BS		 3084 QTAILQ_INIT(&ml_head);
3085
0d673e36 3086 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 3087 mon_printf(f, "address-space: %s\n", as->name);
3088 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3089 mon_printf(f, "\n");
b9f9be88
BS		 3090 }
3091
314e2987 3092 /* print aliased regions */
a16878d2 3093 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH		 3094 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3095 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3096 mon_printf(f, "\n");
314e2987
BS		 3097 }
3098
a16878d2 3099 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3100 g_free(ml);
314e2987 3101 }
314e2987 3102}
b4fefef9 3103
b08199c6
PM		 3104void memory_region_init_ram(MemoryRegion *mr,
3105 struct Object *owner,
3106 const char *name,
3107 uint64_t size,
3108 Error **errp)
3109{
3110 DeviceState *owner_dev;
3111 Error *err = NULL;
3112
3113 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3114 if (err) {
3115 error_propagate(errp, err);
3116 return;
3117 }
3118 /* This will assert if owner is neither NULL nor a DeviceState.
3119 * We only want the owner here for the purposes of defining a
3120 * unique name for migration. TODO: Ideally we should implement
3121 * a naming scheme for Objects which are not DeviceStates, in
3122 * which case we can relax this restriction.
3123 */
3124 owner_dev = DEVICE(owner);
3125 vmstate_register_ram(mr, owner_dev);
3126}
3127
3128void memory_region_init_rom(MemoryRegion *mr,
3129 struct Object *owner,
3130 const char *name,
3131 uint64_t size,
3132 Error **errp)
3133{
3134 DeviceState *owner_dev;
3135 Error *err = NULL;
3136
3137 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3138 if (err) {
3139 error_propagate(errp, err);
3140 return;
3141 }
3142 /* This will assert if owner is neither NULL nor a DeviceState.
3143 * We only want the owner here for the purposes of defining a
3144 * unique name for migration. TODO: Ideally we should implement
3145 * a naming scheme for Objects which are not DeviceStates, in
3146 * which case we can relax this restriction.
3147 */
3148 owner_dev = DEVICE(owner);
3149 vmstate_register_ram(mr, owner_dev);
3150}
3151
3152void memory_region_init_rom_device(MemoryRegion *mr,
3153 struct Object *owner,
3154 const MemoryRegionOps *ops,
3155 void *opaque,
3156 const char *name,
3157 uint64_t size,
3158 Error **errp)
3159{
3160 DeviceState *owner_dev;
3161 Error *err = NULL;
3162
3163 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3164 name, size, &err);
3165 if (err) {
3166 error_propagate(errp, err);
3167 return;
3168 }
3169 /* This will assert if owner is neither NULL nor a DeviceState.
3170 * We only want the owner here for the purposes of defining a
3171 * unique name for migration. TODO: Ideally we should implement
3172 * a naming scheme for Objects which are not DeviceStates, in
3173 * which case we can relax this restriction.
3174 */
3175 owner_dev = DEVICE(owner);
3176 vmstate_register_ram(mr, owner_dev);
3177}
3178
b4fefef9
PC		 3179static const TypeInfo memory_region_info = {
3180 .parent = TYPE_OBJECT,
3181 .name = TYPE_MEMORY_REGION,
3182 .instance_size = sizeof(MemoryRegion),
3183 .instance_init = memory_region_initfn,
3184 .instance_finalize = memory_region_finalize,
3185};
3186
3df9d748
AK		 3187static const TypeInfo iommu_memory_region_info = {
3188 .parent = TYPE_MEMORY_REGION,
3189 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3190 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3191 .instance_size = sizeof(IOMMUMemoryRegion),
3192 .instance_init = iommu_memory_region_initfn,
1221a474 3193 .abstract = true,
3df9d748
AK		 3194};
3195
b4fefef9
PC		 3196static void memory_register_types(void)
3197{
3198 type_register_static(&memory_region_info);
3df9d748 3199 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 3200}
3201
3202type_init(memory_register_types)
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