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Commit | Line | Data |
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093bc2cd AK |
1 | /* |
2 | * Physical memory management | |
3 | * | |
4 | * Copyright 2011 Red Hat, Inc. and/or its affiliates | |
5 | * | |
6 | * Authors: | |
7 | * Avi Kivity <avi@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
6b620ca3 PB |
12 | * Contributions after 2012-01-13 are licensed under the terms of the |
13 | * GNU GPL, version 2 or (at your option) any later version. | |
093bc2cd AK |
14 | */ |
15 | ||
d38ea87a | 16 | #include "qemu/osdep.h" |
da34e65c | 17 | #include "qapi/error.h" |
33c11879 | 18 | #include "cpu.h" |
022c62cb PB |
19 | #include "exec/memory.h" |
20 | #include "exec/address-spaces.h" | |
409ddd01 | 21 | #include "qapi/visitor.h" |
1de7afc9 | 22 | #include "qemu/bitops.h" |
8c56c1a5 | 23 | #include "qemu/error-report.h" |
b6b71cb5 | 24 | #include "qemu/qemu-print.h" |
2c9b15ca | 25 | #include "qom/object.h" |
0ab8ed18 | 26 | #include "trace-root.h" |
093bc2cd | 27 | |
022c62cb | 28 | #include "exec/memory-internal.h" |
220c3ebd | 29 | #include "exec/ram_addr.h" |
8c56c1a5 | 30 | #include "sysemu/kvm.h" |
e1c57ab8 | 31 | #include "sysemu/sysemu.h" |
14a48c1d | 32 | #include "sysemu/tcg.h" |
c9356746 | 33 | #include "hw/qdev-properties.h" |
b08199c6 | 34 | #include "migration/vmstate.h" |
67d95c15 | 35 | |
d197063f PB |
36 | //#define DEBUG_UNASSIGNED |
37 | ||
22bde714 JK |
38 | static unsigned memory_region_transaction_depth; |
39 | static bool memory_region_update_pending; | |
4dc56152 | 40 | static bool ioeventfd_update_pending; |
ae7a2bca | 41 | bool global_dirty_log; |
7664e80c | 42 | |
eae3eb3e | 43 | static QTAILQ_HEAD(, MemoryListener) memory_listeners |
72e22d2f | 44 | = QTAILQ_HEAD_INITIALIZER(memory_listeners); |
4ef4db86 | 45 | |
0d673e36 AK |
46 | static QTAILQ_HEAD(, AddressSpace) address_spaces |
47 | = QTAILQ_HEAD_INITIALIZER(address_spaces); | |
48 | ||
967dc9b1 AK |
49 | static GHashTable *flat_views; |
50 | ||
093bc2cd AK |
51 | typedef struct AddrRange AddrRange; |
52 | ||
8417cebf | 53 | /* |
c9cdaa3a | 54 | * Note that signed integers are needed for negative offsetting in aliases |
8417cebf AK |
55 | * (large MemoryRegion::alias_offset). |
56 | */ | |
093bc2cd | 57 | struct AddrRange { |
08dafab4 AK |
58 | Int128 start; |
59 | Int128 size; | |
093bc2cd AK |
60 | }; |
61 | ||
08dafab4 | 62 | static AddrRange addrrange_make(Int128 start, Int128 size) |
093bc2cd AK |
63 | { |
64 | return (AddrRange) { start, size }; | |
65 | } | |
66 | ||
67 | static bool addrrange_equal(AddrRange r1, AddrRange r2) | |
68 | { | |
08dafab4 | 69 | return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size); |
093bc2cd AK |
70 | } |
71 | ||
08dafab4 | 72 | static Int128 addrrange_end(AddrRange r) |
093bc2cd | 73 | { |
08dafab4 | 74 | return int128_add(r.start, r.size); |
093bc2cd AK |
75 | } |
76 | ||
08dafab4 | 77 | static AddrRange addrrange_shift(AddrRange range, Int128 delta) |
093bc2cd | 78 | { |
08dafab4 | 79 | int128_addto(&range.start, delta); |
093bc2cd AK |
80 | return range; |
81 | } | |
82 | ||
08dafab4 AK |
83 | static bool addrrange_contains(AddrRange range, Int128 addr) |
84 | { | |
85 | return int128_ge(addr, range.start) | |
86 | && int128_lt(addr, addrrange_end(range)); | |
87 | } | |
88 | ||
093bc2cd AK |
89 | static bool addrrange_intersects(AddrRange r1, AddrRange r2) |
90 | { | |
08dafab4 AK |
91 | return addrrange_contains(r1, r2.start) |
92 | || addrrange_contains(r2, r1.start); | |
093bc2cd AK |
93 | } |
94 | ||
95 | static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) | |
96 | { | |
08dafab4 AK |
97 | Int128 start = int128_max(r1.start, r2.start); |
98 | Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2)); | |
99 | return addrrange_make(start, int128_sub(end, start)); | |
093bc2cd AK |
100 | } |
101 | ||
0e0d36b4 AK |
102 | enum ListenerDirection { Forward, Reverse }; |
103 | ||
7376e582 | 104 | #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \ |
0e0d36b4 AK |
105 | do { \ |
106 | MemoryListener *_listener; \ | |
107 | \ | |
108 | switch (_direction) { \ | |
109 | case Forward: \ | |
110 | QTAILQ_FOREACH(_listener, &memory_listeners, link) { \ | |
975aefe0 AK |
111 | if (_listener->_callback) { \ |
112 | _listener->_callback(_listener, ##_args); \ | |
113 | } \ | |
0e0d36b4 AK |
114 | } \ |
115 | break; \ | |
116 | case Reverse: \ | |
eae3eb3e | 117 | QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \ |
975aefe0 AK |
118 | if (_listener->_callback) { \ |
119 | _listener->_callback(_listener, ##_args); \ | |
120 | } \ | |
0e0d36b4 AK |
121 | } \ |
122 | break; \ | |
123 | default: \ | |
124 | abort(); \ | |
125 | } \ | |
126 | } while (0) | |
127 | ||
9a54635d | 128 | #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \ |
7376e582 AK |
129 | do { \ |
130 | MemoryListener *_listener; \ | |
131 | \ | |
132 | switch (_direction) { \ | |
133 | case Forward: \ | |
eae3eb3e | 134 | QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 135 | if (_listener->_callback) { \ |
7376e582 AK |
136 | _listener->_callback(_listener, _section, ##_args); \ |
137 | } \ | |
138 | } \ | |
139 | break; \ | |
140 | case Reverse: \ | |
eae3eb3e | 141 | QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 142 | if (_listener->_callback) { \ |
7376e582 AK |
143 | _listener->_callback(_listener, _section, ##_args); \ |
144 | } \ | |
145 | } \ | |
146 | break; \ | |
147 | default: \ | |
148 | abort(); \ | |
149 | } \ | |
150 | } while (0) | |
151 | ||
dfde4e6e | 152 | /* No need to ref/unref .mr, the FlatRange keeps it alive. */ |
b2dfd71c | 153 | #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \ |
9c1f8f44 | 154 | do { \ |
16620684 AK |
155 | MemoryRegionSection mrs = section_from_flat_range(fr, \ |
156 | address_space_to_flatview(as)); \ | |
9a54635d | 157 | MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \ |
9c1f8f44 | 158 | } while(0) |
0e0d36b4 | 159 | |
093bc2cd AK |
160 | struct CoalescedMemoryRange { |
161 | AddrRange addr; | |
162 | QTAILQ_ENTRY(CoalescedMemoryRange) link; | |
163 | }; | |
164 | ||
3e9d69e7 AK |
165 | struct MemoryRegionIoeventfd { |
166 | AddrRange addr; | |
167 | bool match_data; | |
168 | uint64_t data; | |
753d5e14 | 169 | EventNotifier *e; |
3e9d69e7 AK |
170 | }; |
171 | ||
73bb753d TB |
172 | static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a, |
173 | MemoryRegionIoeventfd *b) | |
3e9d69e7 | 174 | { |
73bb753d | 175 | if (int128_lt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 176 | return true; |
73bb753d | 177 | } else if (int128_gt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 178 | return false; |
73bb753d | 179 | } else if (int128_lt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 180 | return true; |
73bb753d | 181 | } else if (int128_gt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 182 | return false; |
73bb753d | 183 | } else if (a->match_data < b->match_data) { |
3e9d69e7 | 184 | return true; |
73bb753d | 185 | } else if (a->match_data > b->match_data) { |
3e9d69e7 | 186 | return false; |
73bb753d TB |
187 | } else if (a->match_data) { |
188 | if (a->data < b->data) { | |
3e9d69e7 | 189 | return true; |
73bb753d | 190 | } else if (a->data > b->data) { |
3e9d69e7 AK |
191 | return false; |
192 | } | |
193 | } | |
73bb753d | 194 | if (a->e < b->e) { |
3e9d69e7 | 195 | return true; |
73bb753d | 196 | } else if (a->e > b->e) { |
3e9d69e7 AK |
197 | return false; |
198 | } | |
199 | return false; | |
200 | } | |
201 | ||
73bb753d TB |
202 | static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a, |
203 | MemoryRegionIoeventfd *b) | |
3e9d69e7 AK |
204 | { |
205 | return !memory_region_ioeventfd_before(a, b) | |
206 | && !memory_region_ioeventfd_before(b, a); | |
207 | } | |
208 | ||
093bc2cd AK |
209 | /* Range of memory in the global map. Addresses are absolute. */ |
210 | struct FlatRange { | |
211 | MemoryRegion *mr; | |
a8170e5e | 212 | hwaddr offset_in_region; |
093bc2cd | 213 | AddrRange addr; |
5a583347 | 214 | uint8_t dirty_log_mask; |
b138e654 | 215 | bool romd_mode; |
fb1cd6f9 | 216 | bool readonly; |
c26763f8 | 217 | bool nonvolatile; |
3ac7d43a | 218 | int has_coalesced_range; |
093bc2cd AK |
219 | }; |
220 | ||
093bc2cd AK |
221 | #define FOR_EACH_FLAT_RANGE(var, view) \ |
222 | for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) | |
223 | ||
9c1f8f44 | 224 | static inline MemoryRegionSection |
16620684 | 225 | section_from_flat_range(FlatRange *fr, FlatView *fv) |
9c1f8f44 PB |
226 | { |
227 | return (MemoryRegionSection) { | |
228 | .mr = fr->mr, | |
16620684 | 229 | .fv = fv, |
9c1f8f44 PB |
230 | .offset_within_region = fr->offset_in_region, |
231 | .size = fr->addr.size, | |
232 | .offset_within_address_space = int128_get64(fr->addr.start), | |
233 | .readonly = fr->readonly, | |
c26763f8 | 234 | .nonvolatile = fr->nonvolatile, |
9c1f8f44 PB |
235 | }; |
236 | } | |
237 | ||
093bc2cd AK |
238 | static bool flatrange_equal(FlatRange *a, FlatRange *b) |
239 | { | |
240 | return a->mr == b->mr | |
241 | && addrrange_equal(a->addr, b->addr) | |
d0a9b5bc | 242 | && a->offset_in_region == b->offset_in_region |
b138e654 | 243 | && a->romd_mode == b->romd_mode |
c26763f8 MAL |
244 | && a->readonly == b->readonly |
245 | && a->nonvolatile == b->nonvolatile; | |
093bc2cd AK |
246 | } |
247 | ||
89c177bb | 248 | static FlatView *flatview_new(MemoryRegion *mr_root) |
093bc2cd | 249 | { |
cc94cd6d AK |
250 | FlatView *view; |
251 | ||
252 | view = g_new0(FlatView, 1); | |
856d7245 | 253 | view->ref = 1; |
89c177bb AK |
254 | view->root = mr_root; |
255 | memory_region_ref(mr_root); | |
02d9651d | 256 | trace_flatview_new(view, mr_root); |
cc94cd6d AK |
257 | |
258 | return view; | |
093bc2cd AK |
259 | } |
260 | ||
261 | /* Insert a range into a given position. Caller is responsible for maintaining | |
262 | * sorting order. | |
263 | */ | |
264 | static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) | |
265 | { | |
266 | if (view->nr == view->nr_allocated) { | |
267 | view->nr_allocated = MAX(2 * view->nr, 10); | |
7267c094 | 268 | view->ranges = g_realloc(view->ranges, |
093bc2cd AK |
269 | view->nr_allocated * sizeof(*view->ranges)); |
270 | } | |
271 | memmove(view->ranges + pos + 1, view->ranges + pos, | |
272 | (view->nr - pos) * sizeof(FlatRange)); | |
273 | view->ranges[pos] = *range; | |
dfde4e6e | 274 | memory_region_ref(range->mr); |
093bc2cd AK |
275 | ++view->nr; |
276 | } | |
277 | ||
278 | static void flatview_destroy(FlatView *view) | |
279 | { | |
dfde4e6e PB |
280 | int i; |
281 | ||
02d9651d | 282 | trace_flatview_destroy(view, view->root); |
66a6df1d AK |
283 | if (view->dispatch) { |
284 | address_space_dispatch_free(view->dispatch); | |
285 | } | |
dfde4e6e PB |
286 | for (i = 0; i < view->nr; i++) { |
287 | memory_region_unref(view->ranges[i].mr); | |
288 | } | |
7267c094 | 289 | g_free(view->ranges); |
89c177bb | 290 | memory_region_unref(view->root); |
a9a0c06d | 291 | g_free(view); |
093bc2cd AK |
292 | } |
293 | ||
447b0d0b | 294 | static bool flatview_ref(FlatView *view) |
856d7245 | 295 | { |
447b0d0b | 296 | return atomic_fetch_inc_nonzero(&view->ref) > 0; |
856d7245 PB |
297 | } |
298 | ||
48564041 | 299 | void flatview_unref(FlatView *view) |
856d7245 PB |
300 | { |
301 | if (atomic_fetch_dec(&view->ref) == 1) { | |
02d9651d | 302 | trace_flatview_destroy_rcu(view, view->root); |
092aa2fc | 303 | assert(view->root); |
66a6df1d | 304 | call_rcu(view, flatview_destroy, rcu); |
856d7245 PB |
305 | } |
306 | } | |
307 | ||
3d8e6bf9 AK |
308 | static bool can_merge(FlatRange *r1, FlatRange *r2) |
309 | { | |
08dafab4 | 310 | return int128_eq(addrrange_end(r1->addr), r2->addr.start) |
3d8e6bf9 | 311 | && r1->mr == r2->mr |
08dafab4 AK |
312 | && int128_eq(int128_add(int128_make64(r1->offset_in_region), |
313 | r1->addr.size), | |
314 | int128_make64(r2->offset_in_region)) | |
d0a9b5bc | 315 | && r1->dirty_log_mask == r2->dirty_log_mask |
b138e654 | 316 | && r1->romd_mode == r2->romd_mode |
c26763f8 MAL |
317 | && r1->readonly == r2->readonly |
318 | && r1->nonvolatile == r2->nonvolatile; | |
3d8e6bf9 AK |
319 | } |
320 | ||
8508e024 | 321 | /* Attempt to simplify a view by merging adjacent ranges */ |
3d8e6bf9 AK |
322 | static void flatview_simplify(FlatView *view) |
323 | { | |
838ec117 | 324 | unsigned i, j, k; |
3d8e6bf9 AK |
325 | |
326 | i = 0; | |
327 | while (i < view->nr) { | |
328 | j = i + 1; | |
329 | while (j < view->nr | |
330 | && can_merge(&view->ranges[j-1], &view->ranges[j])) { | |
08dafab4 | 331 | int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size); |
3d8e6bf9 AK |
332 | ++j; |
333 | } | |
334 | ++i; | |
838ec117 KW |
335 | for (k = i; k < j; k++) { |
336 | memory_region_unref(view->ranges[k].mr); | |
337 | } | |
3d8e6bf9 AK |
338 | memmove(&view->ranges[i], &view->ranges[j], |
339 | (view->nr - j) * sizeof(view->ranges[j])); | |
340 | view->nr -= j - i; | |
341 | } | |
342 | } | |
343 | ||
e7342aa3 PB |
344 | static bool memory_region_big_endian(MemoryRegion *mr) |
345 | { | |
346 | #ifdef TARGET_WORDS_BIGENDIAN | |
347 | return mr->ops->endianness != DEVICE_LITTLE_ENDIAN; | |
348 | #else | |
349 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
350 | #endif | |
351 | } | |
352 | ||
e11ef3d1 PB |
353 | static bool memory_region_wrong_endianness(MemoryRegion *mr) |
354 | { | |
355 | #ifdef TARGET_WORDS_BIGENDIAN | |
356 | return mr->ops->endianness == DEVICE_LITTLE_ENDIAN; | |
357 | #else | |
358 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
359 | #endif | |
360 | } | |
361 | ||
362 | static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size) | |
363 | { | |
364 | if (memory_region_wrong_endianness(mr)) { | |
365 | switch (size) { | |
366 | case 1: | |
367 | break; | |
368 | case 2: | |
369 | *data = bswap16(*data); | |
370 | break; | |
371 | case 4: | |
372 | *data = bswap32(*data); | |
373 | break; | |
374 | case 8: | |
375 | *data = bswap64(*data); | |
376 | break; | |
377 | default: | |
378 | abort(); | |
379 | } | |
380 | } | |
381 | } | |
382 | ||
3c754a93 | 383 | static inline void memory_region_shift_read_access(uint64_t *value, |
98f52cdb | 384 | signed shift, |
3c754a93 PMD |
385 | uint64_t mask, |
386 | uint64_t tmp) | |
387 | { | |
98f52cdb PMD |
388 | if (shift >= 0) { |
389 | *value |= (tmp & mask) << shift; | |
390 | } else { | |
391 | *value |= (tmp & mask) >> -shift; | |
392 | } | |
3c754a93 PMD |
393 | } |
394 | ||
395 | static inline uint64_t memory_region_shift_write_access(uint64_t *value, | |
98f52cdb | 396 | signed shift, |
3c754a93 PMD |
397 | uint64_t mask) |
398 | { | |
98f52cdb PMD |
399 | uint64_t tmp; |
400 | ||
401 | if (shift >= 0) { | |
402 | tmp = (*value >> shift) & mask; | |
403 | } else { | |
404 | tmp = (*value << -shift) & mask; | |
405 | } | |
406 | ||
407 | return tmp; | |
3c754a93 PMD |
408 | } |
409 | ||
4779dc1d HB |
410 | static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset) |
411 | { | |
412 | MemoryRegion *root; | |
413 | hwaddr abs_addr = offset; | |
414 | ||
415 | abs_addr += mr->addr; | |
416 | for (root = mr; root->container; ) { | |
417 | root = root->container; | |
418 | abs_addr += root->addr; | |
419 | } | |
420 | ||
421 | return abs_addr; | |
422 | } | |
423 | ||
5a68be94 HB |
424 | static int get_cpu_index(void) |
425 | { | |
426 | if (current_cpu) { | |
427 | return current_cpu->cpu_index; | |
428 | } | |
429 | return -1; | |
430 | } | |
431 | ||
cc05c43a | 432 | static MemTxResult memory_region_read_accessor(MemoryRegion *mr, |
ce5d2f33 PB |
433 | hwaddr addr, |
434 | uint64_t *value, | |
435 | unsigned size, | |
98f52cdb | 436 | signed shift, |
cc05c43a PM |
437 | uint64_t mask, |
438 | MemTxAttrs attrs) | |
ce5d2f33 | 439 | { |
ce5d2f33 PB |
440 | uint64_t tmp; |
441 | ||
cc05c43a | 442 | tmp = mr->ops->read(mr->opaque, addr, size); |
23d92d68 | 443 | if (mr->subpage) { |
5a68be94 | 444 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
445 | } else if (mr == &io_mem_notdirty) { |
446 | /* Accesses to code which has previously been translated into a TB show | |
447 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
448 | * MemoryRegion. */ | |
449 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
450 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
451 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 452 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 453 | } |
3c754a93 | 454 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 455 | return MEMTX_OK; |
ce5d2f33 PB |
456 | } |
457 | ||
cc05c43a PM |
458 | static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, |
459 | hwaddr addr, | |
460 | uint64_t *value, | |
461 | unsigned size, | |
98f52cdb | 462 | signed shift, |
cc05c43a PM |
463 | uint64_t mask, |
464 | MemTxAttrs attrs) | |
164a4dcd | 465 | { |
cc05c43a PM |
466 | uint64_t tmp = 0; |
467 | MemTxResult r; | |
164a4dcd | 468 | |
cc05c43a | 469 | r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs); |
23d92d68 | 470 | if (mr->subpage) { |
5a68be94 | 471 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
472 | } else if (mr == &io_mem_notdirty) { |
473 | /* Accesses to code which has previously been translated into a TB show | |
474 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
475 | * MemoryRegion. */ | |
476 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
477 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
478 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 479 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 480 | } |
3c754a93 | 481 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 482 | return r; |
164a4dcd AK |
483 | } |
484 | ||
cc05c43a PM |
485 | static MemTxResult memory_region_write_accessor(MemoryRegion *mr, |
486 | hwaddr addr, | |
487 | uint64_t *value, | |
488 | unsigned size, | |
98f52cdb | 489 | signed shift, |
cc05c43a PM |
490 | uint64_t mask, |
491 | MemTxAttrs attrs) | |
164a4dcd | 492 | { |
3c754a93 | 493 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
164a4dcd | 494 | |
23d92d68 | 495 | if (mr->subpage) { |
5a68be94 | 496 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
497 | } else if (mr == &io_mem_notdirty) { |
498 | /* Accesses to code which has previously been translated into a TB show | |
499 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
500 | * MemoryRegion. */ | |
501 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
502 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
503 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 504 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 505 | } |
164a4dcd | 506 | mr->ops->write(mr->opaque, addr, tmp, size); |
cc05c43a | 507 | return MEMTX_OK; |
164a4dcd AK |
508 | } |
509 | ||
cc05c43a PM |
510 | static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, |
511 | hwaddr addr, | |
512 | uint64_t *value, | |
513 | unsigned size, | |
98f52cdb | 514 | signed shift, |
cc05c43a PM |
515 | uint64_t mask, |
516 | MemTxAttrs attrs) | |
517 | { | |
3c754a93 | 518 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
cc05c43a | 519 | |
23d92d68 | 520 | if (mr->subpage) { |
5a68be94 | 521 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
522 | } else if (mr == &io_mem_notdirty) { |
523 | /* Accesses to code which has previously been translated into a TB show | |
524 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
525 | * MemoryRegion. */ | |
526 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
527 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
528 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 529 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 530 | } |
cc05c43a PM |
531 | return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); |
532 | } | |
533 | ||
534 | static MemTxResult access_with_adjusted_size(hwaddr addr, | |
164a4dcd AK |
535 | uint64_t *value, |
536 | unsigned size, | |
537 | unsigned access_size_min, | |
538 | unsigned access_size_max, | |
05e015f7 KF |
539 | MemTxResult (*access_fn) |
540 | (MemoryRegion *mr, | |
541 | hwaddr addr, | |
542 | uint64_t *value, | |
543 | unsigned size, | |
98f52cdb | 544 | signed shift, |
05e015f7 KF |
545 | uint64_t mask, |
546 | MemTxAttrs attrs), | |
cc05c43a PM |
547 | MemoryRegion *mr, |
548 | MemTxAttrs attrs) | |
164a4dcd AK |
549 | { |
550 | uint64_t access_mask; | |
551 | unsigned access_size; | |
552 | unsigned i; | |
cc05c43a | 553 | MemTxResult r = MEMTX_OK; |
164a4dcd AK |
554 | |
555 | if (!access_size_min) { | |
556 | access_size_min = 1; | |
557 | } | |
558 | if (!access_size_max) { | |
559 | access_size_max = 4; | |
560 | } | |
ce5d2f33 PB |
561 | |
562 | /* FIXME: support unaligned access? */ | |
164a4dcd | 563 | access_size = MAX(MIN(size, access_size_max), access_size_min); |
36960b4d | 564 | access_mask = MAKE_64BIT_MASK(0, access_size * 8); |
e7342aa3 PB |
565 | if (memory_region_big_endian(mr)) { |
566 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 567 | r |= access_fn(mr, addr + i, value, access_size, |
cc05c43a | 568 | (size - access_size - i) * 8, access_mask, attrs); |
e7342aa3 PB |
569 | } |
570 | } else { | |
571 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 572 | r |= access_fn(mr, addr + i, value, access_size, i * 8, |
cc05c43a | 573 | access_mask, attrs); |
e7342aa3 | 574 | } |
164a4dcd | 575 | } |
cc05c43a | 576 | return r; |
164a4dcd AK |
577 | } |
578 | ||
e2177955 AK |
579 | static AddressSpace *memory_region_to_address_space(MemoryRegion *mr) |
580 | { | |
0d673e36 AK |
581 | AddressSpace *as; |
582 | ||
feca4ac1 PB |
583 | while (mr->container) { |
584 | mr = mr->container; | |
e2177955 | 585 | } |
0d673e36 AK |
586 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
587 | if (mr == as->root) { | |
588 | return as; | |
589 | } | |
e2177955 | 590 | } |
eed2bacf | 591 | return NULL; |
e2177955 AK |
592 | } |
593 | ||
093bc2cd AK |
594 | /* Render a memory region into the global view. Ranges in @view obscure |
595 | * ranges in @mr. | |
596 | */ | |
597 | static void render_memory_region(FlatView *view, | |
598 | MemoryRegion *mr, | |
08dafab4 | 599 | Int128 base, |
fb1cd6f9 | 600 | AddrRange clip, |
c26763f8 MAL |
601 | bool readonly, |
602 | bool nonvolatile) | |
093bc2cd AK |
603 | { |
604 | MemoryRegion *subregion; | |
605 | unsigned i; | |
a8170e5e | 606 | hwaddr offset_in_region; |
08dafab4 AK |
607 | Int128 remain; |
608 | Int128 now; | |
093bc2cd AK |
609 | FlatRange fr; |
610 | AddrRange tmp; | |
611 | ||
6bba19ba AK |
612 | if (!mr->enabled) { |
613 | return; | |
614 | } | |
615 | ||
08dafab4 | 616 | int128_addto(&base, int128_make64(mr->addr)); |
fb1cd6f9 | 617 | readonly |= mr->readonly; |
c26763f8 | 618 | nonvolatile |= mr->nonvolatile; |
093bc2cd AK |
619 | |
620 | tmp = addrrange_make(base, mr->size); | |
621 | ||
622 | if (!addrrange_intersects(tmp, clip)) { | |
623 | return; | |
624 | } | |
625 | ||
626 | clip = addrrange_intersection(tmp, clip); | |
627 | ||
628 | if (mr->alias) { | |
08dafab4 AK |
629 | int128_subfrom(&base, int128_make64(mr->alias->addr)); |
630 | int128_subfrom(&base, int128_make64(mr->alias_offset)); | |
c26763f8 MAL |
631 | render_memory_region(view, mr->alias, base, clip, |
632 | readonly, nonvolatile); | |
093bc2cd AK |
633 | return; |
634 | } | |
635 | ||
636 | /* Render subregions in priority order. */ | |
637 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
c26763f8 MAL |
638 | render_memory_region(view, subregion, base, clip, |
639 | readonly, nonvolatile); | |
093bc2cd AK |
640 | } |
641 | ||
14a3c10a | 642 | if (!mr->terminates) { |
093bc2cd AK |
643 | return; |
644 | } | |
645 | ||
08dafab4 | 646 | offset_in_region = int128_get64(int128_sub(clip.start, base)); |
093bc2cd AK |
647 | base = clip.start; |
648 | remain = clip.size; | |
649 | ||
2eb74e1a | 650 | fr.mr = mr; |
6f6a5ef3 | 651 | fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
b138e654 | 652 | fr.romd_mode = mr->romd_mode; |
2eb74e1a | 653 | fr.readonly = readonly; |
c26763f8 | 654 | fr.nonvolatile = nonvolatile; |
3ac7d43a | 655 | fr.has_coalesced_range = 0; |
2eb74e1a | 656 | |
093bc2cd | 657 | /* Render the region itself into any gaps left by the current view. */ |
08dafab4 AK |
658 | for (i = 0; i < view->nr && int128_nz(remain); ++i) { |
659 | if (int128_ge(base, addrrange_end(view->ranges[i].addr))) { | |
093bc2cd AK |
660 | continue; |
661 | } | |
08dafab4 AK |
662 | if (int128_lt(base, view->ranges[i].addr.start)) { |
663 | now = int128_min(remain, | |
664 | int128_sub(view->ranges[i].addr.start, base)); | |
093bc2cd AK |
665 | fr.offset_in_region = offset_in_region; |
666 | fr.addr = addrrange_make(base, now); | |
667 | flatview_insert(view, i, &fr); | |
668 | ++i; | |
08dafab4 AK |
669 | int128_addto(&base, now); |
670 | offset_in_region += int128_get64(now); | |
671 | int128_subfrom(&remain, now); | |
093bc2cd | 672 | } |
d26a8cae AK |
673 | now = int128_sub(int128_min(int128_add(base, remain), |
674 | addrrange_end(view->ranges[i].addr)), | |
675 | base); | |
676 | int128_addto(&base, now); | |
677 | offset_in_region += int128_get64(now); | |
678 | int128_subfrom(&remain, now); | |
093bc2cd | 679 | } |
08dafab4 | 680 | if (int128_nz(remain)) { |
093bc2cd AK |
681 | fr.offset_in_region = offset_in_region; |
682 | fr.addr = addrrange_make(base, remain); | |
683 | flatview_insert(view, i, &fr); | |
684 | } | |
685 | } | |
686 | ||
89c177bb AK |
687 | static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr) |
688 | { | |
e673ba9a PB |
689 | while (mr->enabled) { |
690 | if (mr->alias) { | |
691 | if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) { | |
692 | /* The alias is included in its entirety. Use it as | |
693 | * the "real" root, so that we can share more FlatViews. | |
694 | */ | |
695 | mr = mr->alias; | |
696 | continue; | |
697 | } | |
698 | } else if (!mr->terminates) { | |
699 | unsigned int found = 0; | |
700 | MemoryRegion *child, *next = NULL; | |
701 | QTAILQ_FOREACH(child, &mr->subregions, subregions_link) { | |
702 | if (child->enabled) { | |
703 | if (++found > 1) { | |
704 | next = NULL; | |
705 | break; | |
706 | } | |
707 | if (!child->addr && int128_ge(mr->size, child->size)) { | |
708 | /* A child is included in its entirety. If it's the only | |
709 | * enabled one, use it in the hope of finding an alias down the | |
710 | * way. This will also let us share FlatViews. | |
711 | */ | |
712 | next = child; | |
713 | } | |
714 | } | |
715 | } | |
092aa2fc AK |
716 | if (found == 0) { |
717 | return NULL; | |
718 | } | |
e673ba9a PB |
719 | if (next) { |
720 | mr = next; | |
721 | continue; | |
722 | } | |
723 | } | |
724 | ||
092aa2fc | 725 | return mr; |
89c177bb AK |
726 | } |
727 | ||
092aa2fc | 728 | return NULL; |
89c177bb AK |
729 | } |
730 | ||
093bc2cd | 731 | /* Render a memory topology into a list of disjoint absolute ranges. */ |
a9a0c06d | 732 | static FlatView *generate_memory_topology(MemoryRegion *mr) |
093bc2cd | 733 | { |
9bf561e3 | 734 | int i; |
a9a0c06d | 735 | FlatView *view; |
093bc2cd | 736 | |
89c177bb | 737 | view = flatview_new(mr); |
093bc2cd | 738 | |
83f3c251 | 739 | if (mr) { |
a9a0c06d | 740 | render_memory_region(view, mr, int128_zero(), |
c26763f8 MAL |
741 | addrrange_make(int128_zero(), int128_2_64()), |
742 | false, false); | |
83f3c251 | 743 | } |
a9a0c06d | 744 | flatview_simplify(view); |
093bc2cd | 745 | |
9bf561e3 AK |
746 | view->dispatch = address_space_dispatch_new(view); |
747 | for (i = 0; i < view->nr; i++) { | |
748 | MemoryRegionSection mrs = | |
749 | section_from_flat_range(&view->ranges[i], view); | |
750 | flatview_add_to_dispatch(view, &mrs); | |
751 | } | |
752 | address_space_dispatch_compact(view->dispatch); | |
967dc9b1 | 753 | g_hash_table_replace(flat_views, mr, view); |
9bf561e3 | 754 | |
093bc2cd AK |
755 | return view; |
756 | } | |
757 | ||
3e9d69e7 AK |
758 | static void address_space_add_del_ioeventfds(AddressSpace *as, |
759 | MemoryRegionIoeventfd *fds_new, | |
760 | unsigned fds_new_nb, | |
761 | MemoryRegionIoeventfd *fds_old, | |
762 | unsigned fds_old_nb) | |
763 | { | |
764 | unsigned iold, inew; | |
80a1ea37 AK |
765 | MemoryRegionIoeventfd *fd; |
766 | MemoryRegionSection section; | |
3e9d69e7 AK |
767 | |
768 | /* Generate a symmetric difference of the old and new fd sets, adding | |
769 | * and deleting as necessary. | |
770 | */ | |
771 | ||
772 | iold = inew = 0; | |
773 | while (iold < fds_old_nb || inew < fds_new_nb) { | |
774 | if (iold < fds_old_nb | |
775 | && (inew == fds_new_nb | |
73bb753d TB |
776 | || memory_region_ioeventfd_before(&fds_old[iold], |
777 | &fds_new[inew]))) { | |
80a1ea37 AK |
778 | fd = &fds_old[iold]; |
779 | section = (MemoryRegionSection) { | |
16620684 | 780 | .fv = address_space_to_flatview(as), |
80a1ea37 | 781 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 782 | .size = fd->addr.size, |
80a1ea37 | 783 | }; |
9a54635d | 784 | MEMORY_LISTENER_CALL(as, eventfd_del, Forward, §ion, |
753d5e14 | 785 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
786 | ++iold; |
787 | } else if (inew < fds_new_nb | |
788 | && (iold == fds_old_nb | |
73bb753d TB |
789 | || memory_region_ioeventfd_before(&fds_new[inew], |
790 | &fds_old[iold]))) { | |
80a1ea37 AK |
791 | fd = &fds_new[inew]; |
792 | section = (MemoryRegionSection) { | |
16620684 | 793 | .fv = address_space_to_flatview(as), |
80a1ea37 | 794 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 795 | .size = fd->addr.size, |
80a1ea37 | 796 | }; |
9a54635d | 797 | MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, §ion, |
753d5e14 | 798 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
799 | ++inew; |
800 | } else { | |
801 | ++iold; | |
802 | ++inew; | |
803 | } | |
804 | } | |
805 | } | |
806 | ||
48564041 | 807 | FlatView *address_space_get_flatview(AddressSpace *as) |
856d7245 PB |
808 | { |
809 | FlatView *view; | |
810 | ||
374f2981 | 811 | rcu_read_lock(); |
447b0d0b | 812 | do { |
16620684 | 813 | view = address_space_to_flatview(as); |
447b0d0b PB |
814 | /* If somebody has replaced as->current_map concurrently, |
815 | * flatview_ref returns false. | |
816 | */ | |
817 | } while (!flatview_ref(view)); | |
374f2981 | 818 | rcu_read_unlock(); |
856d7245 PB |
819 | return view; |
820 | } | |
821 | ||
3e9d69e7 AK |
822 | static void address_space_update_ioeventfds(AddressSpace *as) |
823 | { | |
99e86347 | 824 | FlatView *view; |
3e9d69e7 AK |
825 | FlatRange *fr; |
826 | unsigned ioeventfd_nb = 0; | |
827 | MemoryRegionIoeventfd *ioeventfds = NULL; | |
828 | AddrRange tmp; | |
829 | unsigned i; | |
830 | ||
856d7245 | 831 | view = address_space_get_flatview(as); |
99e86347 | 832 | FOR_EACH_FLAT_RANGE(fr, view) { |
3e9d69e7 AK |
833 | for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { |
834 | tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, | |
08dafab4 AK |
835 | int128_sub(fr->addr.start, |
836 | int128_make64(fr->offset_in_region))); | |
3e9d69e7 AK |
837 | if (addrrange_intersects(fr->addr, tmp)) { |
838 | ++ioeventfd_nb; | |
7267c094 | 839 | ioeventfds = g_realloc(ioeventfds, |
3e9d69e7 AK |
840 | ioeventfd_nb * sizeof(*ioeventfds)); |
841 | ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; | |
842 | ioeventfds[ioeventfd_nb-1].addr = tmp; | |
843 | } | |
844 | } | |
845 | } | |
846 | ||
847 | address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, | |
848 | as->ioeventfds, as->ioeventfd_nb); | |
849 | ||
7267c094 | 850 | g_free(as->ioeventfds); |
3e9d69e7 AK |
851 | as->ioeventfds = ioeventfds; |
852 | as->ioeventfd_nb = ioeventfd_nb; | |
856d7245 | 853 | flatview_unref(view); |
3e9d69e7 AK |
854 | } |
855 | ||
909bf763 PB |
856 | static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as) |
857 | { | |
1f7af804 PB |
858 | if (!fr->has_coalesced_range) { |
859 | return; | |
860 | } | |
861 | ||
3ac7d43a PB |
862 | if (--fr->has_coalesced_range > 0) { |
863 | return; | |
864 | } | |
865 | ||
909bf763 PB |
866 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del, |
867 | int128_get64(fr->addr.start), | |
868 | int128_get64(fr->addr.size)); | |
869 | } | |
870 | ||
871 | static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as) | |
872 | { | |
873 | MemoryRegion *mr = fr->mr; | |
874 | CoalescedMemoryRange *cmr; | |
875 | AddrRange tmp; | |
876 | ||
1f7af804 PB |
877 | if (QTAILQ_EMPTY(&mr->coalesced)) { |
878 | return; | |
879 | } | |
880 | ||
3ac7d43a PB |
881 | if (fr->has_coalesced_range++) { |
882 | return; | |
883 | } | |
884 | ||
909bf763 PB |
885 | QTAILQ_FOREACH(cmr, &mr->coalesced, link) { |
886 | tmp = addrrange_shift(cmr->addr, | |
887 | int128_sub(fr->addr.start, | |
888 | int128_make64(fr->offset_in_region))); | |
889 | if (!addrrange_intersects(tmp, fr->addr)) { | |
890 | continue; | |
891 | } | |
892 | tmp = addrrange_intersection(tmp, fr->addr); | |
893 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add, | |
894 | int128_get64(tmp.start), | |
895 | int128_get64(tmp.size)); | |
896 | } | |
897 | } | |
898 | ||
b8af1afb | 899 | static void address_space_update_topology_pass(AddressSpace *as, |
a9a0c06d PB |
900 | const FlatView *old_view, |
901 | const FlatView *new_view, | |
b8af1afb | 902 | bool adding) |
093bc2cd | 903 | { |
093bc2cd AK |
904 | unsigned iold, inew; |
905 | FlatRange *frold, *frnew; | |
093bc2cd AK |
906 | |
907 | /* Generate a symmetric difference of the old and new memory maps. | |
908 | * Kill ranges in the old map, and instantiate ranges in the new map. | |
909 | */ | |
910 | iold = inew = 0; | |
a9a0c06d PB |
911 | while (iold < old_view->nr || inew < new_view->nr) { |
912 | if (iold < old_view->nr) { | |
913 | frold = &old_view->ranges[iold]; | |
093bc2cd AK |
914 | } else { |
915 | frold = NULL; | |
916 | } | |
a9a0c06d PB |
917 | if (inew < new_view->nr) { |
918 | frnew = &new_view->ranges[inew]; | |
093bc2cd AK |
919 | } else { |
920 | frnew = NULL; | |
921 | } | |
922 | ||
923 | if (frold | |
924 | && (!frnew | |
08dafab4 AK |
925 | || int128_lt(frold->addr.start, frnew->addr.start) |
926 | || (int128_eq(frold->addr.start, frnew->addr.start) | |
093bc2cd | 927 | && !flatrange_equal(frold, frnew)))) { |
41a6e477 | 928 | /* In old but not in new, or in both but attributes changed. */ |
093bc2cd | 929 | |
b8af1afb | 930 | if (!adding) { |
3ac7d43a | 931 | flat_range_coalesced_io_del(frold, as); |
72e22d2f | 932 | MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del); |
b8af1afb AK |
933 | } |
934 | ||
093bc2cd AK |
935 | ++iold; |
936 | } else if (frold && frnew && flatrange_equal(frold, frnew)) { | |
41a6e477 | 937 | /* In both and unchanged (except logging may have changed) */ |
093bc2cd | 938 | |
4f826024 | 939 | if (adding) { |
50c1e149 | 940 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop); |
b2dfd71c PB |
941 | if (frnew->dirty_log_mask & ~frold->dirty_log_mask) { |
942 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start, | |
943 | frold->dirty_log_mask, | |
944 | frnew->dirty_log_mask); | |
945 | } | |
946 | if (frold->dirty_log_mask & ~frnew->dirty_log_mask) { | |
947 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop, | |
948 | frold->dirty_log_mask, | |
949 | frnew->dirty_log_mask); | |
b8af1afb | 950 | } |
5a583347 AK |
951 | } |
952 | ||
093bc2cd AK |
953 | ++iold; |
954 | ++inew; | |
093bc2cd AK |
955 | } else { |
956 | /* In new */ | |
957 | ||
b8af1afb | 958 | if (adding) { |
72e22d2f | 959 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add); |
3ac7d43a | 960 | flat_range_coalesced_io_add(frnew, as); |
b8af1afb AK |
961 | } |
962 | ||
093bc2cd AK |
963 | ++inew; |
964 | } | |
965 | } | |
b8af1afb AK |
966 | } |
967 | ||
967dc9b1 AK |
968 | static void flatviews_init(void) |
969 | { | |
092aa2fc AK |
970 | static FlatView *empty_view; |
971 | ||
967dc9b1 AK |
972 | if (flat_views) { |
973 | return; | |
974 | } | |
975 | ||
976 | flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL, | |
977 | (GDestroyNotify) flatview_unref); | |
092aa2fc AK |
978 | if (!empty_view) { |
979 | empty_view = generate_memory_topology(NULL); | |
980 | /* We keep it alive forever in the global variable. */ | |
981 | flatview_ref(empty_view); | |
982 | } else { | |
983 | g_hash_table_replace(flat_views, NULL, empty_view); | |
984 | flatview_ref(empty_view); | |
985 | } | |
967dc9b1 AK |
986 | } |
987 | ||
988 | static void flatviews_reset(void) | |
989 | { | |
990 | AddressSpace *as; | |
991 | ||
992 | if (flat_views) { | |
993 | g_hash_table_unref(flat_views); | |
994 | flat_views = NULL; | |
995 | } | |
996 | flatviews_init(); | |
997 | ||
998 | /* Render unique FVs */ | |
999 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1000 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1001 | ||
1002 | if (g_hash_table_lookup(flat_views, physmr)) { | |
1003 | continue; | |
1004 | } | |
1005 | ||
1006 | generate_memory_topology(physmr); | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | static void address_space_set_flatview(AddressSpace *as) | |
b8af1afb | 1011 | { |
67ace39b | 1012 | FlatView *old_view = address_space_to_flatview(as); |
967dc9b1 AK |
1013 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); |
1014 | FlatView *new_view = g_hash_table_lookup(flat_views, physmr); | |
1015 | ||
1016 | assert(new_view); | |
1017 | ||
67ace39b AK |
1018 | if (old_view == new_view) { |
1019 | return; | |
1020 | } | |
1021 | ||
1022 | if (old_view) { | |
1023 | flatview_ref(old_view); | |
1024 | } | |
1025 | ||
967dc9b1 | 1026 | flatview_ref(new_view); |
9a62e24f AK |
1027 | |
1028 | if (!QTAILQ_EMPTY(&as->listeners)) { | |
67ace39b AK |
1029 | FlatView tmpview = { .nr = 0 }, *old_view2 = old_view; |
1030 | ||
1031 | if (!old_view2) { | |
1032 | old_view2 = &tmpview; | |
1033 | } | |
1034 | address_space_update_topology_pass(as, old_view2, new_view, false); | |
1035 | address_space_update_topology_pass(as, old_view2, new_view, true); | |
9a62e24f | 1036 | } |
b8af1afb | 1037 | |
374f2981 PB |
1038 | /* Writes are protected by the BQL. */ |
1039 | atomic_rcu_set(&as->current_map, new_view); | |
67ace39b AK |
1040 | if (old_view) { |
1041 | flatview_unref(old_view); | |
1042 | } | |
856d7245 PB |
1043 | |
1044 | /* Note that all the old MemoryRegions are still alive up to this | |
1045 | * point. This relieves most MemoryListeners from the need to | |
1046 | * ref/unref the MemoryRegions they get---unless they use them | |
1047 | * outside the iothread mutex, in which case precise reference | |
1048 | * counting is necessary. | |
1049 | */ | |
67ace39b AK |
1050 | if (old_view) { |
1051 | flatview_unref(old_view); | |
1052 | } | |
093bc2cd AK |
1053 | } |
1054 | ||
202fc01b AK |
1055 | static void address_space_update_topology(AddressSpace *as) |
1056 | { | |
1057 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1058 | ||
1059 | flatviews_init(); | |
1060 | if (!g_hash_table_lookup(flat_views, physmr)) { | |
1061 | generate_memory_topology(physmr); | |
1062 | } | |
1063 | address_space_set_flatview(as); | |
1064 | } | |
1065 | ||
4ef4db86 AK |
1066 | void memory_region_transaction_begin(void) |
1067 | { | |
bb880ded | 1068 | qemu_flush_coalesced_mmio_buffer(); |
4ef4db86 AK |
1069 | ++memory_region_transaction_depth; |
1070 | } | |
1071 | ||
1072 | void memory_region_transaction_commit(void) | |
1073 | { | |
0d673e36 AK |
1074 | AddressSpace *as; |
1075 | ||
4ef4db86 | 1076 | assert(memory_region_transaction_depth); |
8d04fb55 JK |
1077 | assert(qemu_mutex_iothread_locked()); |
1078 | ||
4ef4db86 | 1079 | --memory_region_transaction_depth; |
4dc56152 GA |
1080 | if (!memory_region_transaction_depth) { |
1081 | if (memory_region_update_pending) { | |
967dc9b1 AK |
1082 | flatviews_reset(); |
1083 | ||
4dc56152 | 1084 | MEMORY_LISTENER_CALL_GLOBAL(begin, Forward); |
02e2b95f | 1085 | |
4dc56152 | 1086 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
967dc9b1 | 1087 | address_space_set_flatview(as); |
02218487 | 1088 | address_space_update_ioeventfds(as); |
4dc56152 | 1089 | } |
ade9c1aa | 1090 | memory_region_update_pending = false; |
0b152095 | 1091 | ioeventfd_update_pending = false; |
4dc56152 GA |
1092 | MEMORY_LISTENER_CALL_GLOBAL(commit, Forward); |
1093 | } else if (ioeventfd_update_pending) { | |
1094 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1095 | address_space_update_ioeventfds(as); | |
1096 | } | |
ade9c1aa | 1097 | ioeventfd_update_pending = false; |
4dc56152 | 1098 | } |
4dc56152 | 1099 | } |
4ef4db86 AK |
1100 | } |
1101 | ||
545e92e0 AK |
1102 | static void memory_region_destructor_none(MemoryRegion *mr) |
1103 | { | |
1104 | } | |
1105 | ||
1106 | static void memory_region_destructor_ram(MemoryRegion *mr) | |
1107 | { | |
f1060c55 | 1108 | qemu_ram_free(mr->ram_block); |
545e92e0 AK |
1109 | } |
1110 | ||
b4fefef9 PC |
1111 | static bool memory_region_need_escape(char c) |
1112 | { | |
1113 | return c == '/' || c == '[' || c == '\\' || c == ']'; | |
1114 | } | |
1115 | ||
1116 | static char *memory_region_escape_name(const char *name) | |
1117 | { | |
1118 | const char *p; | |
1119 | char *escaped, *q; | |
1120 | uint8_t c; | |
1121 | size_t bytes = 0; | |
1122 | ||
1123 | for (p = name; *p; p++) { | |
1124 | bytes += memory_region_need_escape(*p) ? 4 : 1; | |
1125 | } | |
1126 | if (bytes == p - name) { | |
1127 | return g_memdup(name, bytes + 1); | |
1128 | } | |
1129 | ||
1130 | escaped = g_malloc(bytes + 1); | |
1131 | for (p = name, q = escaped; *p; p++) { | |
1132 | c = *p; | |
1133 | if (unlikely(memory_region_need_escape(c))) { | |
1134 | *q++ = '\\'; | |
1135 | *q++ = 'x'; | |
1136 | *q++ = "0123456789abcdef"[c >> 4]; | |
1137 | c = "0123456789abcdef"[c & 15]; | |
1138 | } | |
1139 | *q++ = c; | |
1140 | } | |
1141 | *q = 0; | |
1142 | return escaped; | |
1143 | } | |
1144 | ||
3df9d748 AK |
1145 | static void memory_region_do_init(MemoryRegion *mr, |
1146 | Object *owner, | |
1147 | const char *name, | |
1148 | uint64_t size) | |
093bc2cd | 1149 | { |
08dafab4 AK |
1150 | mr->size = int128_make64(size); |
1151 | if (size == UINT64_MAX) { | |
1152 | mr->size = int128_2_64(); | |
1153 | } | |
302fa283 | 1154 | mr->name = g_strdup(name); |
612263cf | 1155 | mr->owner = owner; |
58eaa217 | 1156 | mr->ram_block = NULL; |
b4fefef9 PC |
1157 | |
1158 | if (name) { | |
843ef73a PC |
1159 | char *escaped_name = memory_region_escape_name(name); |
1160 | char *name_array = g_strdup_printf("%s[*]", escaped_name); | |
612263cf PB |
1161 | |
1162 | if (!owner) { | |
1163 | owner = container_get(qdev_get_machine(), "/unattached"); | |
1164 | } | |
1165 | ||
843ef73a | 1166 | object_property_add_child(owner, name_array, OBJECT(mr), &error_abort); |
b4fefef9 | 1167 | object_unref(OBJECT(mr)); |
843ef73a PC |
1168 | g_free(name_array); |
1169 | g_free(escaped_name); | |
b4fefef9 PC |
1170 | } |
1171 | } | |
1172 | ||
3df9d748 AK |
1173 | void memory_region_init(MemoryRegion *mr, |
1174 | Object *owner, | |
1175 | const char *name, | |
1176 | uint64_t size) | |
1177 | { | |
1178 | object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION); | |
1179 | memory_region_do_init(mr, owner, name, size); | |
1180 | } | |
1181 | ||
d7bce999 EB |
1182 | static void memory_region_get_addr(Object *obj, Visitor *v, const char *name, |
1183 | void *opaque, Error **errp) | |
409ddd01 PC |
1184 | { |
1185 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1186 | uint64_t value = mr->addr; | |
1187 | ||
51e72bc1 | 1188 | visit_type_uint64(v, name, &value, errp); |
409ddd01 PC |
1189 | } |
1190 | ||
d7bce999 EB |
1191 | static void memory_region_get_container(Object *obj, Visitor *v, |
1192 | const char *name, void *opaque, | |
1193 | Error **errp) | |
409ddd01 PC |
1194 | { |
1195 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1196 | gchar *path = (gchar *)""; | |
1197 | ||
1198 | if (mr->container) { | |
1199 | path = object_get_canonical_path(OBJECT(mr->container)); | |
1200 | } | |
51e72bc1 | 1201 | visit_type_str(v, name, &path, errp); |
409ddd01 PC |
1202 | if (mr->container) { |
1203 | g_free(path); | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | static Object *memory_region_resolve_container(Object *obj, void *opaque, | |
1208 | const char *part) | |
1209 | { | |
1210 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1211 | ||
1212 | return OBJECT(mr->container); | |
1213 | } | |
1214 | ||
d7bce999 EB |
1215 | static void memory_region_get_priority(Object *obj, Visitor *v, |
1216 | const char *name, void *opaque, | |
1217 | Error **errp) | |
d33382da PC |
1218 | { |
1219 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1220 | int32_t value = mr->priority; | |
1221 | ||
51e72bc1 | 1222 | visit_type_int32(v, name, &value, errp); |
d33382da PC |
1223 | } |
1224 | ||
d7bce999 EB |
1225 | static void memory_region_get_size(Object *obj, Visitor *v, const char *name, |
1226 | void *opaque, Error **errp) | |
52aef7bb PC |
1227 | { |
1228 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1229 | uint64_t value = memory_region_size(mr); | |
1230 | ||
51e72bc1 | 1231 | visit_type_uint64(v, name, &value, errp); |
52aef7bb PC |
1232 | } |
1233 | ||
b4fefef9 PC |
1234 | static void memory_region_initfn(Object *obj) |
1235 | { | |
1236 | MemoryRegion *mr = MEMORY_REGION(obj); | |
409ddd01 | 1237 | ObjectProperty *op; |
b4fefef9 PC |
1238 | |
1239 | mr->ops = &unassigned_mem_ops; | |
6bba19ba | 1240 | mr->enabled = true; |
5f9a5ea1 | 1241 | mr->romd_mode = true; |
196ea131 | 1242 | mr->global_locking = true; |
545e92e0 | 1243 | mr->destructor = memory_region_destructor_none; |
093bc2cd | 1244 | QTAILQ_INIT(&mr->subregions); |
093bc2cd | 1245 | QTAILQ_INIT(&mr->coalesced); |
409ddd01 PC |
1246 | |
1247 | op = object_property_add(OBJECT(mr), "container", | |
1248 | "link<" TYPE_MEMORY_REGION ">", | |
1249 | memory_region_get_container, | |
1250 | NULL, /* memory_region_set_container */ | |
1251 | NULL, NULL, &error_abort); | |
1252 | op->resolve = memory_region_resolve_container; | |
1253 | ||
1254 | object_property_add(OBJECT(mr), "addr", "uint64", | |
1255 | memory_region_get_addr, | |
1256 | NULL, /* memory_region_set_addr */ | |
1257 | NULL, NULL, &error_abort); | |
d33382da PC |
1258 | object_property_add(OBJECT(mr), "priority", "uint32", |
1259 | memory_region_get_priority, | |
1260 | NULL, /* memory_region_set_priority */ | |
1261 | NULL, NULL, &error_abort); | |
52aef7bb PC |
1262 | object_property_add(OBJECT(mr), "size", "uint64", |
1263 | memory_region_get_size, | |
1264 | NULL, /* memory_region_set_size, */ | |
1265 | NULL, NULL, &error_abort); | |
093bc2cd AK |
1266 | } |
1267 | ||
3df9d748 AK |
1268 | static void iommu_memory_region_initfn(Object *obj) |
1269 | { | |
1270 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1271 | ||
1272 | mr->is_iommu = true; | |
1273 | } | |
1274 | ||
b018ddf6 PB |
1275 | static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, |
1276 | unsigned size) | |
1277 | { | |
1278 | #ifdef DEBUG_UNASSIGNED | |
1279 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
1280 | #endif | |
4917cf44 | 1281 | if (current_cpu != NULL) { |
dbea78a4 PM |
1282 | bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH; |
1283 | cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size); | |
c658b94f | 1284 | } |
68a7439a | 1285 | return 0; |
b018ddf6 PB |
1286 | } |
1287 | ||
1288 | static void unassigned_mem_write(void *opaque, hwaddr addr, | |
1289 | uint64_t val, unsigned size) | |
1290 | { | |
1291 | #ifdef DEBUG_UNASSIGNED | |
1292 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); | |
1293 | #endif | |
4917cf44 AF |
1294 | if (current_cpu != NULL) { |
1295 | cpu_unassigned_access(current_cpu, addr, true, false, 0, size); | |
c658b94f | 1296 | } |
b018ddf6 PB |
1297 | } |
1298 | ||
d197063f | 1299 | static bool unassigned_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1300 | unsigned size, bool is_write, |
1301 | MemTxAttrs attrs) | |
d197063f PB |
1302 | { |
1303 | return false; | |
1304 | } | |
1305 | ||
1306 | const MemoryRegionOps unassigned_mem_ops = { | |
1307 | .valid.accepts = unassigned_mem_accepts, | |
1308 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1309 | }; | |
1310 | ||
4a2e242b AW |
1311 | static uint64_t memory_region_ram_device_read(void *opaque, |
1312 | hwaddr addr, unsigned size) | |
1313 | { | |
1314 | MemoryRegion *mr = opaque; | |
1315 | uint64_t data = (uint64_t)~0; | |
1316 | ||
1317 | switch (size) { | |
1318 | case 1: | |
1319 | data = *(uint8_t *)(mr->ram_block->host + addr); | |
1320 | break; | |
1321 | case 2: | |
1322 | data = *(uint16_t *)(mr->ram_block->host + addr); | |
1323 | break; | |
1324 | case 4: | |
1325 | data = *(uint32_t *)(mr->ram_block->host + addr); | |
1326 | break; | |
1327 | case 8: | |
1328 | data = *(uint64_t *)(mr->ram_block->host + addr); | |
1329 | break; | |
1330 | } | |
1331 | ||
1332 | trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size); | |
1333 | ||
1334 | return data; | |
1335 | } | |
1336 | ||
1337 | static void memory_region_ram_device_write(void *opaque, hwaddr addr, | |
1338 | uint64_t data, unsigned size) | |
1339 | { | |
1340 | MemoryRegion *mr = opaque; | |
1341 | ||
1342 | trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size); | |
1343 | ||
1344 | switch (size) { | |
1345 | case 1: | |
1346 | *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data; | |
1347 | break; | |
1348 | case 2: | |
1349 | *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data; | |
1350 | break; | |
1351 | case 4: | |
1352 | *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data; | |
1353 | break; | |
1354 | case 8: | |
1355 | *(uint64_t *)(mr->ram_block->host + addr) = data; | |
1356 | break; | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | static const MemoryRegionOps ram_device_mem_ops = { | |
1361 | .read = memory_region_ram_device_read, | |
1362 | .write = memory_region_ram_device_write, | |
c99a29e7 | 1363 | .endianness = DEVICE_HOST_ENDIAN, |
4a2e242b AW |
1364 | .valid = { |
1365 | .min_access_size = 1, | |
1366 | .max_access_size = 8, | |
1367 | .unaligned = true, | |
1368 | }, | |
1369 | .impl = { | |
1370 | .min_access_size = 1, | |
1371 | .max_access_size = 8, | |
1372 | .unaligned = true, | |
1373 | }, | |
1374 | }; | |
1375 | ||
d2702032 PB |
1376 | bool memory_region_access_valid(MemoryRegion *mr, |
1377 | hwaddr addr, | |
1378 | unsigned size, | |
6d7b9a6c PM |
1379 | bool is_write, |
1380 | MemTxAttrs attrs) | |
093bc2cd | 1381 | { |
a014ed07 PB |
1382 | int access_size_min, access_size_max; |
1383 | int access_size, i; | |
897fa7cf | 1384 | |
093bc2cd AK |
1385 | if (!mr->ops->valid.unaligned && (addr & (size - 1))) { |
1386 | return false; | |
1387 | } | |
1388 | ||
a014ed07 | 1389 | if (!mr->ops->valid.accepts) { |
093bc2cd AK |
1390 | return true; |
1391 | } | |
1392 | ||
a014ed07 PB |
1393 | access_size_min = mr->ops->valid.min_access_size; |
1394 | if (!mr->ops->valid.min_access_size) { | |
1395 | access_size_min = 1; | |
1396 | } | |
1397 | ||
1398 | access_size_max = mr->ops->valid.max_access_size; | |
1399 | if (!mr->ops->valid.max_access_size) { | |
1400 | access_size_max = 4; | |
1401 | } | |
1402 | ||
1403 | access_size = MAX(MIN(size, access_size_max), access_size_min); | |
1404 | for (i = 0; i < size; i += access_size) { | |
1405 | if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size, | |
8372d383 | 1406 | is_write, attrs)) { |
a014ed07 PB |
1407 | return false; |
1408 | } | |
093bc2cd | 1409 | } |
a014ed07 | 1410 | |
093bc2cd AK |
1411 | return true; |
1412 | } | |
1413 | ||
cc05c43a PM |
1414 | static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, |
1415 | hwaddr addr, | |
1416 | uint64_t *pval, | |
1417 | unsigned size, | |
1418 | MemTxAttrs attrs) | |
093bc2cd | 1419 | { |
cc05c43a | 1420 | *pval = 0; |
093bc2cd | 1421 | |
ce5d2f33 | 1422 | if (mr->ops->read) { |
cc05c43a PM |
1423 | return access_with_adjusted_size(addr, pval, size, |
1424 | mr->ops->impl.min_access_size, | |
1425 | mr->ops->impl.max_access_size, | |
1426 | memory_region_read_accessor, | |
1427 | mr, attrs); | |
62a0db94 | 1428 | } else { |
cc05c43a PM |
1429 | return access_with_adjusted_size(addr, pval, size, |
1430 | mr->ops->impl.min_access_size, | |
1431 | mr->ops->impl.max_access_size, | |
1432 | memory_region_read_with_attrs_accessor, | |
1433 | mr, attrs); | |
74901c3b | 1434 | } |
093bc2cd AK |
1435 | } |
1436 | ||
3b643495 PM |
1437 | MemTxResult memory_region_dispatch_read(MemoryRegion *mr, |
1438 | hwaddr addr, | |
1439 | uint64_t *pval, | |
1440 | unsigned size, | |
1441 | MemTxAttrs attrs) | |
a621f38d | 1442 | { |
cc05c43a PM |
1443 | MemTxResult r; |
1444 | ||
6d7b9a6c | 1445 | if (!memory_region_access_valid(mr, addr, size, false, attrs)) { |
791af8c8 | 1446 | *pval = unassigned_mem_read(mr, addr, size); |
cc05c43a | 1447 | return MEMTX_DECODE_ERROR; |
791af8c8 | 1448 | } |
a621f38d | 1449 | |
cc05c43a | 1450 | r = memory_region_dispatch_read1(mr, addr, pval, size, attrs); |
791af8c8 | 1451 | adjust_endianness(mr, pval, size); |
cc05c43a | 1452 | return r; |
a621f38d | 1453 | } |
093bc2cd | 1454 | |
8c56c1a5 PF |
1455 | /* Return true if an eventfd was signalled */ |
1456 | static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr, | |
1457 | hwaddr addr, | |
1458 | uint64_t data, | |
1459 | unsigned size, | |
1460 | MemTxAttrs attrs) | |
1461 | { | |
1462 | MemoryRegionIoeventfd ioeventfd = { | |
1463 | .addr = addrrange_make(int128_make64(addr), int128_make64(size)), | |
1464 | .data = data, | |
1465 | }; | |
1466 | unsigned i; | |
1467 | ||
1468 | for (i = 0; i < mr->ioeventfd_nb; i++) { | |
1469 | ioeventfd.match_data = mr->ioeventfds[i].match_data; | |
1470 | ioeventfd.e = mr->ioeventfds[i].e; | |
1471 | ||
73bb753d | 1472 | if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) { |
8c56c1a5 PF |
1473 | event_notifier_set(ioeventfd.e); |
1474 | return true; | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | return false; | |
1479 | } | |
1480 | ||
3b643495 PM |
1481 | MemTxResult memory_region_dispatch_write(MemoryRegion *mr, |
1482 | hwaddr addr, | |
1483 | uint64_t data, | |
1484 | unsigned size, | |
1485 | MemTxAttrs attrs) | |
a621f38d | 1486 | { |
6d7b9a6c | 1487 | if (!memory_region_access_valid(mr, addr, size, true, attrs)) { |
b018ddf6 | 1488 | unassigned_mem_write(mr, addr, data, size); |
cc05c43a | 1489 | return MEMTX_DECODE_ERROR; |
093bc2cd AK |
1490 | } |
1491 | ||
a621f38d AK |
1492 | adjust_endianness(mr, &data, size); |
1493 | ||
8c56c1a5 PF |
1494 | if ((!kvm_eventfds_enabled()) && |
1495 | memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) { | |
1496 | return MEMTX_OK; | |
1497 | } | |
1498 | ||
ce5d2f33 | 1499 | if (mr->ops->write) { |
cc05c43a PM |
1500 | return access_with_adjusted_size(addr, &data, size, |
1501 | mr->ops->impl.min_access_size, | |
1502 | mr->ops->impl.max_access_size, | |
1503 | memory_region_write_accessor, mr, | |
1504 | attrs); | |
62a0db94 | 1505 | } else { |
cc05c43a PM |
1506 | return |
1507 | access_with_adjusted_size(addr, &data, size, | |
1508 | mr->ops->impl.min_access_size, | |
1509 | mr->ops->impl.max_access_size, | |
1510 | memory_region_write_with_attrs_accessor, | |
1511 | mr, attrs); | |
74901c3b | 1512 | } |
093bc2cd AK |
1513 | } |
1514 | ||
093bc2cd | 1515 | void memory_region_init_io(MemoryRegion *mr, |
2c9b15ca | 1516 | Object *owner, |
093bc2cd AK |
1517 | const MemoryRegionOps *ops, |
1518 | void *opaque, | |
1519 | const char *name, | |
1520 | uint64_t size) | |
1521 | { | |
2c9b15ca | 1522 | memory_region_init(mr, owner, name, size); |
6d6d2abf | 1523 | mr->ops = ops ? ops : &unassigned_mem_ops; |
093bc2cd | 1524 | mr->opaque = opaque; |
14a3c10a | 1525 | mr->terminates = true; |
093bc2cd AK |
1526 | } |
1527 | ||
1cfe48c1 PM |
1528 | void memory_region_init_ram_nomigrate(MemoryRegion *mr, |
1529 | Object *owner, | |
1530 | const char *name, | |
1531 | uint64_t size, | |
1532 | Error **errp) | |
06329cce MA |
1533 | { |
1534 | memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp); | |
1535 | } | |
1536 | ||
1537 | void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr, | |
1538 | Object *owner, | |
1539 | const char *name, | |
1540 | uint64_t size, | |
1541 | bool share, | |
1542 | Error **errp) | |
093bc2cd | 1543 | { |
1cd3d492 | 1544 | Error *err = NULL; |
2c9b15ca | 1545 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1546 | mr->ram = true; |
14a3c10a | 1547 | mr->terminates = true; |
545e92e0 | 1548 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 | 1549 | mr->ram_block = qemu_ram_alloc(size, share, mr, &err); |
677e7805 | 1550 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1551 | if (err) { |
1552 | mr->size = int128_zero(); | |
1553 | object_unparent(OBJECT(mr)); | |
1554 | error_propagate(errp, err); | |
1555 | } | |
0b183fc8 PB |
1556 | } |
1557 | ||
60786ef3 MT |
1558 | void memory_region_init_resizeable_ram(MemoryRegion *mr, |
1559 | Object *owner, | |
1560 | const char *name, | |
1561 | uint64_t size, | |
1562 | uint64_t max_size, | |
1563 | void (*resized)(const char*, | |
1564 | uint64_t length, | |
1565 | void *host), | |
1566 | Error **errp) | |
1567 | { | |
1cd3d492 | 1568 | Error *err = NULL; |
60786ef3 MT |
1569 | memory_region_init(mr, owner, name, size); |
1570 | mr->ram = true; | |
1571 | mr->terminates = true; | |
1572 | mr->destructor = memory_region_destructor_ram; | |
8e41fb63 | 1573 | mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized, |
1cd3d492 | 1574 | mr, &err); |
677e7805 | 1575 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1576 | if (err) { |
1577 | mr->size = int128_zero(); | |
1578 | object_unparent(OBJECT(mr)); | |
1579 | error_propagate(errp, err); | |
1580 | } | |
60786ef3 MT |
1581 | } |
1582 | ||
d5dbde46 | 1583 | #ifdef CONFIG_POSIX |
0b183fc8 PB |
1584 | void memory_region_init_ram_from_file(MemoryRegion *mr, |
1585 | struct Object *owner, | |
1586 | const char *name, | |
1587 | uint64_t size, | |
98376843 | 1588 | uint64_t align, |
cbfc0171 | 1589 | uint32_t ram_flags, |
7f56e740 PB |
1590 | const char *path, |
1591 | Error **errp) | |
0b183fc8 | 1592 | { |
1cd3d492 | 1593 | Error *err = NULL; |
0b183fc8 PB |
1594 | memory_region_init(mr, owner, name, size); |
1595 | mr->ram = true; | |
1596 | mr->terminates = true; | |
1597 | mr->destructor = memory_region_destructor_ram; | |
98376843 | 1598 | mr->align = align; |
1cd3d492 | 1599 | mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err); |
677e7805 | 1600 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1601 | if (err) { |
1602 | mr->size = int128_zero(); | |
1603 | object_unparent(OBJECT(mr)); | |
1604 | error_propagate(errp, err); | |
1605 | } | |
093bc2cd | 1606 | } |
fea617c5 MAL |
1607 | |
1608 | void memory_region_init_ram_from_fd(MemoryRegion *mr, | |
1609 | struct Object *owner, | |
1610 | const char *name, | |
1611 | uint64_t size, | |
1612 | bool share, | |
1613 | int fd, | |
1614 | Error **errp) | |
1615 | { | |
1cd3d492 | 1616 | Error *err = NULL; |
fea617c5 MAL |
1617 | memory_region_init(mr, owner, name, size); |
1618 | mr->ram = true; | |
1619 | mr->terminates = true; | |
1620 | mr->destructor = memory_region_destructor_ram; | |
cbfc0171 JH |
1621 | mr->ram_block = qemu_ram_alloc_from_fd(size, mr, |
1622 | share ? RAM_SHARED : 0, | |
1cd3d492 | 1623 | fd, &err); |
fea617c5 | 1624 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1625 | if (err) { |
1626 | mr->size = int128_zero(); | |
1627 | object_unparent(OBJECT(mr)); | |
1628 | error_propagate(errp, err); | |
1629 | } | |
fea617c5 | 1630 | } |
0b183fc8 | 1631 | #endif |
093bc2cd AK |
1632 | |
1633 | void memory_region_init_ram_ptr(MemoryRegion *mr, | |
2c9b15ca | 1634 | Object *owner, |
093bc2cd AK |
1635 | const char *name, |
1636 | uint64_t size, | |
1637 | void *ptr) | |
1638 | { | |
2c9b15ca | 1639 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1640 | mr->ram = true; |
14a3c10a | 1641 | mr->terminates = true; |
fc3e7665 | 1642 | mr->destructor = memory_region_destructor_ram; |
677e7805 | 1643 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
ef701d7b HT |
1644 | |
1645 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1646 | assert(ptr != NULL); | |
8e41fb63 | 1647 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); |
093bc2cd AK |
1648 | } |
1649 | ||
21e00fa5 AW |
1650 | void memory_region_init_ram_device_ptr(MemoryRegion *mr, |
1651 | Object *owner, | |
1652 | const char *name, | |
1653 | uint64_t size, | |
1654 | void *ptr) | |
e4dc3f59 | 1655 | { |
2ddb89b0 BS |
1656 | memory_region_init(mr, owner, name, size); |
1657 | mr->ram = true; | |
1658 | mr->terminates = true; | |
21e00fa5 | 1659 | mr->ram_device = true; |
4a2e242b AW |
1660 | mr->ops = &ram_device_mem_ops; |
1661 | mr->opaque = mr; | |
2ddb89b0 BS |
1662 | mr->destructor = memory_region_destructor_ram; |
1663 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; | |
1664 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1665 | assert(ptr != NULL); | |
1666 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); | |
e4dc3f59 ND |
1667 | } |
1668 | ||
093bc2cd | 1669 | void memory_region_init_alias(MemoryRegion *mr, |
2c9b15ca | 1670 | Object *owner, |
093bc2cd AK |
1671 | const char *name, |
1672 | MemoryRegion *orig, | |
a8170e5e | 1673 | hwaddr offset, |
093bc2cd AK |
1674 | uint64_t size) |
1675 | { | |
2c9b15ca | 1676 | memory_region_init(mr, owner, name, size); |
093bc2cd AK |
1677 | mr->alias = orig; |
1678 | mr->alias_offset = offset; | |
1679 | } | |
1680 | ||
b59821a9 PM |
1681 | void memory_region_init_rom_nomigrate(MemoryRegion *mr, |
1682 | struct Object *owner, | |
1683 | const char *name, | |
1684 | uint64_t size, | |
1685 | Error **errp) | |
a1777f7f | 1686 | { |
1cd3d492 | 1687 | Error *err = NULL; |
a1777f7f PM |
1688 | memory_region_init(mr, owner, name, size); |
1689 | mr->ram = true; | |
1690 | mr->readonly = true; | |
1691 | mr->terminates = true; | |
1692 | mr->destructor = memory_region_destructor_ram; | |
1cd3d492 | 1693 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
a1777f7f | 1694 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1695 | if (err) { |
1696 | mr->size = int128_zero(); | |
1697 | object_unparent(OBJECT(mr)); | |
1698 | error_propagate(errp, err); | |
1699 | } | |
a1777f7f PM |
1700 | } |
1701 | ||
b59821a9 PM |
1702 | void memory_region_init_rom_device_nomigrate(MemoryRegion *mr, |
1703 | Object *owner, | |
1704 | const MemoryRegionOps *ops, | |
1705 | void *opaque, | |
1706 | const char *name, | |
1707 | uint64_t size, | |
1708 | Error **errp) | |
d0a9b5bc | 1709 | { |
1cd3d492 | 1710 | Error *err = NULL; |
39e0b03d | 1711 | assert(ops); |
2c9b15ca | 1712 | memory_region_init(mr, owner, name, size); |
7bc2b9cd | 1713 | mr->ops = ops; |
75f5941c | 1714 | mr->opaque = opaque; |
d0a9b5bc | 1715 | mr->terminates = true; |
75c578dc | 1716 | mr->rom_device = true; |
58268c8d | 1717 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 IM |
1718 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
1719 | if (err) { | |
1720 | mr->size = int128_zero(); | |
1721 | object_unparent(OBJECT(mr)); | |
1722 | error_propagate(errp, err); | |
1723 | } | |
d0a9b5bc AK |
1724 | } |
1725 | ||
1221a474 AK |
1726 | void memory_region_init_iommu(void *_iommu_mr, |
1727 | size_t instance_size, | |
1728 | const char *mrtypename, | |
2c9b15ca | 1729 | Object *owner, |
30951157 AK |
1730 | const char *name, |
1731 | uint64_t size) | |
1732 | { | |
1221a474 | 1733 | struct IOMMUMemoryRegion *iommu_mr; |
3df9d748 AK |
1734 | struct MemoryRegion *mr; |
1735 | ||
1221a474 AK |
1736 | object_initialize(_iommu_mr, instance_size, mrtypename); |
1737 | mr = MEMORY_REGION(_iommu_mr); | |
3df9d748 AK |
1738 | memory_region_do_init(mr, owner, name, size); |
1739 | iommu_mr = IOMMU_MEMORY_REGION(mr); | |
30951157 | 1740 | mr->terminates = true; /* then re-forwards */ |
3df9d748 AK |
1741 | QLIST_INIT(&iommu_mr->iommu_notify); |
1742 | iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE; | |
30951157 AK |
1743 | } |
1744 | ||
b4fefef9 | 1745 | static void memory_region_finalize(Object *obj) |
093bc2cd | 1746 | { |
b4fefef9 PC |
1747 | MemoryRegion *mr = MEMORY_REGION(obj); |
1748 | ||
2e2b8eb7 PB |
1749 | assert(!mr->container); |
1750 | ||
1751 | /* We know the region is not visible in any address space (it | |
1752 | * does not have a container and cannot be a root either because | |
1753 | * it has no references, so we can blindly clear mr->enabled. | |
1754 | * memory_region_set_enabled instead could trigger a transaction | |
1755 | * and cause an infinite loop. | |
1756 | */ | |
1757 | mr->enabled = false; | |
1758 | memory_region_transaction_begin(); | |
1759 | while (!QTAILQ_EMPTY(&mr->subregions)) { | |
1760 | MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions); | |
1761 | memory_region_del_subregion(mr, subregion); | |
1762 | } | |
1763 | memory_region_transaction_commit(); | |
1764 | ||
545e92e0 | 1765 | mr->destructor(mr); |
093bc2cd | 1766 | memory_region_clear_coalescing(mr); |
302fa283 | 1767 | g_free((char *)mr->name); |
7267c094 | 1768 | g_free(mr->ioeventfds); |
093bc2cd AK |
1769 | } |
1770 | ||
803c0816 PB |
1771 | Object *memory_region_owner(MemoryRegion *mr) |
1772 | { | |
22a893e4 PB |
1773 | Object *obj = OBJECT(mr); |
1774 | return obj->parent; | |
803c0816 PB |
1775 | } |
1776 | ||
46637be2 PB |
1777 | void memory_region_ref(MemoryRegion *mr) |
1778 | { | |
22a893e4 PB |
1779 | /* MMIO callbacks most likely will access data that belongs |
1780 | * to the owner, hence the need to ref/unref the owner whenever | |
1781 | * the memory region is in use. | |
1782 | * | |
1783 | * The memory region is a child of its owner. As long as the | |
1784 | * owner doesn't call unparent itself on the memory region, | |
1785 | * ref-ing the owner will also keep the memory region alive. | |
612263cf PB |
1786 | * Memory regions without an owner are supposed to never go away; |
1787 | * we do not ref/unref them because it slows down DMA sensibly. | |
22a893e4 | 1788 | */ |
612263cf PB |
1789 | if (mr && mr->owner) { |
1790 | object_ref(mr->owner); | |
46637be2 PB |
1791 | } |
1792 | } | |
1793 | ||
1794 | void memory_region_unref(MemoryRegion *mr) | |
1795 | { | |
612263cf PB |
1796 | if (mr && mr->owner) { |
1797 | object_unref(mr->owner); | |
46637be2 PB |
1798 | } |
1799 | } | |
1800 | ||
093bc2cd AK |
1801 | uint64_t memory_region_size(MemoryRegion *mr) |
1802 | { | |
08dafab4 AK |
1803 | if (int128_eq(mr->size, int128_2_64())) { |
1804 | return UINT64_MAX; | |
1805 | } | |
1806 | return int128_get64(mr->size); | |
093bc2cd AK |
1807 | } |
1808 | ||
5d546d4b | 1809 | const char *memory_region_name(const MemoryRegion *mr) |
8991c79b | 1810 | { |
d1dd32af PC |
1811 | if (!mr->name) { |
1812 | ((MemoryRegion *)mr)->name = | |
1813 | object_get_canonical_path_component(OBJECT(mr)); | |
1814 | } | |
302fa283 | 1815 | return mr->name; |
8991c79b AK |
1816 | } |
1817 | ||
21e00fa5 | 1818 | bool memory_region_is_ram_device(MemoryRegion *mr) |
e4dc3f59 | 1819 | { |
21e00fa5 | 1820 | return mr->ram_device; |
e4dc3f59 ND |
1821 | } |
1822 | ||
2d1a35be | 1823 | uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr) |
55043ba3 | 1824 | { |
6f6a5ef3 | 1825 | uint8_t mask = mr->dirty_log_mask; |
adaad61c | 1826 | if (global_dirty_log && mr->ram_block) { |
6f6a5ef3 PB |
1827 | mask |= (1 << DIRTY_MEMORY_MIGRATION); |
1828 | } | |
1829 | return mask; | |
55043ba3 AK |
1830 | } |
1831 | ||
2d1a35be PB |
1832 | bool memory_region_is_logging(MemoryRegion *mr, uint8_t client) |
1833 | { | |
1834 | return memory_region_get_dirty_log_mask(mr) & (1 << client); | |
1835 | } | |
1836 | ||
3df9d748 | 1837 | static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr) |
5bf3d319 PX |
1838 | { |
1839 | IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE; | |
1840 | IOMMUNotifier *iommu_notifier; | |
1221a474 | 1841 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
5bf3d319 | 1842 | |
3df9d748 | 1843 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
5bf3d319 PX |
1844 | flags |= iommu_notifier->notifier_flags; |
1845 | } | |
1846 | ||
1221a474 AK |
1847 | if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) { |
1848 | imrc->notify_flag_changed(iommu_mr, | |
1849 | iommu_mr->iommu_notify_flags, | |
1850 | flags); | |
5bf3d319 PX |
1851 | } |
1852 | ||
3df9d748 | 1853 | iommu_mr->iommu_notify_flags = flags; |
5bf3d319 PX |
1854 | } |
1855 | ||
cdb30812 PX |
1856 | void memory_region_register_iommu_notifier(MemoryRegion *mr, |
1857 | IOMMUNotifier *n) | |
06866575 | 1858 | { |
3df9d748 AK |
1859 | IOMMUMemoryRegion *iommu_mr; |
1860 | ||
efcd38c5 JW |
1861 | if (mr->alias) { |
1862 | memory_region_register_iommu_notifier(mr->alias, n); | |
1863 | return; | |
1864 | } | |
1865 | ||
cdb30812 | 1866 | /* We need to register for at least one bitfield */ |
3df9d748 | 1867 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
cdb30812 | 1868 | assert(n->notifier_flags != IOMMU_NOTIFIER_NONE); |
698feb5e | 1869 | assert(n->start <= n->end); |
cb1efcf4 PM |
1870 | assert(n->iommu_idx >= 0 && |
1871 | n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr)); | |
1872 | ||
3df9d748 AK |
1873 | QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node); |
1874 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1875 | } |
1876 | ||
3df9d748 | 1877 | uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr) |
a788f227 | 1878 | { |
1221a474 AK |
1879 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
1880 | ||
1881 | if (imrc->get_min_page_size) { | |
1882 | return imrc->get_min_page_size(iommu_mr); | |
f682e9c2 AK |
1883 | } |
1884 | return TARGET_PAGE_SIZE; | |
1885 | } | |
1886 | ||
3df9d748 | 1887 | void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
f682e9c2 | 1888 | { |
3df9d748 | 1889 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); |
1221a474 | 1890 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
f682e9c2 | 1891 | hwaddr addr, granularity; |
a788f227 DG |
1892 | IOMMUTLBEntry iotlb; |
1893 | ||
faa362e3 | 1894 | /* If the IOMMU has its own replay callback, override */ |
1221a474 AK |
1895 | if (imrc->replay) { |
1896 | imrc->replay(iommu_mr, n); | |
faa362e3 PX |
1897 | return; |
1898 | } | |
1899 | ||
3df9d748 | 1900 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); |
f682e9c2 | 1901 | |
a788f227 | 1902 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { |
2c91bcf2 | 1903 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); |
a788f227 DG |
1904 | if (iotlb.perm != IOMMU_NONE) { |
1905 | n->notify(n, &iotlb); | |
1906 | } | |
1907 | ||
1908 | /* if (2^64 - MR size) < granularity, it's possible to get an | |
1909 | * infinite loop here. This should catch such a wraparound */ | |
1910 | if ((addr + granularity) < addr) { | |
1911 | break; | |
1912 | } | |
1913 | } | |
1914 | } | |
1915 | ||
3df9d748 | 1916 | void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr) |
de472e4a PX |
1917 | { |
1918 | IOMMUNotifier *notifier; | |
1919 | ||
3df9d748 AK |
1920 | IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) { |
1921 | memory_region_iommu_replay(iommu_mr, notifier); | |
de472e4a PX |
1922 | } |
1923 | } | |
1924 | ||
cdb30812 PX |
1925 | void memory_region_unregister_iommu_notifier(MemoryRegion *mr, |
1926 | IOMMUNotifier *n) | |
06866575 | 1927 | { |
3df9d748 AK |
1928 | IOMMUMemoryRegion *iommu_mr; |
1929 | ||
efcd38c5 JW |
1930 | if (mr->alias) { |
1931 | memory_region_unregister_iommu_notifier(mr->alias, n); | |
1932 | return; | |
1933 | } | |
cdb30812 | 1934 | QLIST_REMOVE(n, node); |
3df9d748 AK |
1935 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
1936 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1937 | } |
1938 | ||
bd2bfa4c PX |
1939 | void memory_region_notify_one(IOMMUNotifier *notifier, |
1940 | IOMMUTLBEntry *entry) | |
06866575 | 1941 | { |
cdb30812 PX |
1942 | IOMMUNotifierFlag request_flags; |
1943 | ||
bd2bfa4c PX |
1944 | /* |
1945 | * Skip the notification if the notification does not overlap | |
1946 | * with registered range. | |
1947 | */ | |
b021d1c0 | 1948 | if (notifier->start > entry->iova + entry->addr_mask || |
bd2bfa4c PX |
1949 | notifier->end < entry->iova) { |
1950 | return; | |
1951 | } | |
cdb30812 | 1952 | |
bd2bfa4c | 1953 | if (entry->perm & IOMMU_RW) { |
cdb30812 PX |
1954 | request_flags = IOMMU_NOTIFIER_MAP; |
1955 | } else { | |
1956 | request_flags = IOMMU_NOTIFIER_UNMAP; | |
1957 | } | |
1958 | ||
bd2bfa4c PX |
1959 | if (notifier->notifier_flags & request_flags) { |
1960 | notifier->notify(notifier, entry); | |
1961 | } | |
1962 | } | |
1963 | ||
3df9d748 | 1964 | void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, |
cb1efcf4 | 1965 | int iommu_idx, |
bd2bfa4c PX |
1966 | IOMMUTLBEntry entry) |
1967 | { | |
1968 | IOMMUNotifier *iommu_notifier; | |
1969 | ||
3df9d748 | 1970 | assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr))); |
bd2bfa4c | 1971 | |
3df9d748 | 1972 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
cb1efcf4 PM |
1973 | if (iommu_notifier->iommu_idx == iommu_idx) { |
1974 | memory_region_notify_one(iommu_notifier, &entry); | |
1975 | } | |
cdb30812 | 1976 | } |
06866575 DG |
1977 | } |
1978 | ||
f1334de6 AK |
1979 | int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr, |
1980 | enum IOMMUMemoryRegionAttr attr, | |
1981 | void *data) | |
1982 | { | |
1983 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1984 | ||
1985 | if (!imrc->get_attr) { | |
1986 | return -EINVAL; | |
1987 | } | |
1988 | ||
1989 | return imrc->get_attr(iommu_mr, attr, data); | |
1990 | } | |
1991 | ||
21f40209 PM |
1992 | int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr, |
1993 | MemTxAttrs attrs) | |
1994 | { | |
1995 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1996 | ||
1997 | if (!imrc->attrs_to_index) { | |
1998 | return 0; | |
1999 | } | |
2000 | ||
2001 | return imrc->attrs_to_index(iommu_mr, attrs); | |
2002 | } | |
2003 | ||
2004 | int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr) | |
2005 | { | |
2006 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
2007 | ||
2008 | if (!imrc->num_indexes) { | |
2009 | return 1; | |
2010 | } | |
2011 | ||
2012 | return imrc->num_indexes(iommu_mr); | |
2013 | } | |
2014 | ||
093bc2cd AK |
2015 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) |
2016 | { | |
5a583347 | 2017 | uint8_t mask = 1 << client; |
deb809ed | 2018 | uint8_t old_logging; |
5a583347 | 2019 | |
dbddac6d | 2020 | assert(client == DIRTY_MEMORY_VGA); |
deb809ed PB |
2021 | old_logging = mr->vga_logging_count; |
2022 | mr->vga_logging_count += log ? 1 : -1; | |
2023 | if (!!old_logging == !!mr->vga_logging_count) { | |
2024 | return; | |
2025 | } | |
2026 | ||
59023ef4 | 2027 | memory_region_transaction_begin(); |
5a583347 | 2028 | mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); |
22bde714 | 2029 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2030 | memory_region_transaction_commit(); |
093bc2cd AK |
2031 | } |
2032 | ||
a8170e5e AK |
2033 | void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, |
2034 | hwaddr size) | |
093bc2cd | 2035 | { |
8e41fb63 FZ |
2036 | assert(mr->ram_block); |
2037 | cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr, | |
2038 | size, | |
58d2707e | 2039 | memory_region_get_dirty_log_mask(mr)); |
093bc2cd AK |
2040 | } |
2041 | ||
0fe1eca7 | 2042 | static void memory_region_sync_dirty_bitmap(MemoryRegion *mr) |
093bc2cd | 2043 | { |
0a752eee | 2044 | MemoryListener *listener; |
0d673e36 | 2045 | AddressSpace *as; |
0a752eee | 2046 | FlatView *view; |
5a583347 AK |
2047 | FlatRange *fr; |
2048 | ||
0a752eee PB |
2049 | /* If the same address space has multiple log_sync listeners, we |
2050 | * visit that address space's FlatView multiple times. But because | |
2051 | * log_sync listeners are rare, it's still cheaper than walking each | |
2052 | * address space once. | |
2053 | */ | |
2054 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2055 | if (!listener->log_sync) { | |
2056 | continue; | |
2057 | } | |
2058 | as = listener->address_space; | |
2059 | view = address_space_get_flatview(as); | |
99e86347 | 2060 | FOR_EACH_FLAT_RANGE(fr, view) { |
3ebb1817 | 2061 | if (fr->dirty_log_mask && (!mr || fr->mr == mr)) { |
16620684 | 2062 | MemoryRegionSection mrs = section_from_flat_range(fr, view); |
0a752eee | 2063 | listener->log_sync(listener, &mrs); |
0d673e36 | 2064 | } |
5a583347 | 2065 | } |
856d7245 | 2066 | flatview_unref(view); |
5a583347 | 2067 | } |
093bc2cd AK |
2068 | } |
2069 | ||
077874e0 PX |
2070 | void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start, |
2071 | hwaddr len) | |
2072 | { | |
2073 | MemoryRegionSection mrs; | |
2074 | MemoryListener *listener; | |
2075 | AddressSpace *as; | |
2076 | FlatView *view; | |
2077 | FlatRange *fr; | |
2078 | hwaddr sec_start, sec_end, sec_size; | |
2079 | ||
2080 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2081 | if (!listener->log_clear) { | |
2082 | continue; | |
2083 | } | |
2084 | as = listener->address_space; | |
2085 | view = address_space_get_flatview(as); | |
2086 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2087 | if (!fr->dirty_log_mask || fr->mr != mr) { | |
2088 | /* | |
2089 | * Clear dirty bitmap operation only applies to those | |
2090 | * regions whose dirty logging is at least enabled | |
2091 | */ | |
2092 | continue; | |
2093 | } | |
2094 | ||
2095 | mrs = section_from_flat_range(fr, view); | |
2096 | ||
2097 | sec_start = MAX(mrs.offset_within_region, start); | |
2098 | sec_end = mrs.offset_within_region + int128_get64(mrs.size); | |
2099 | sec_end = MIN(sec_end, start + len); | |
2100 | ||
2101 | if (sec_start >= sec_end) { | |
2102 | /* | |
2103 | * If this memory region section has no intersection | |
2104 | * with the requested range, skip. | |
2105 | */ | |
2106 | continue; | |
2107 | } | |
2108 | ||
2109 | /* Valid case; shrink the section if needed */ | |
2110 | mrs.offset_within_address_space += | |
2111 | sec_start - mrs.offset_within_region; | |
2112 | mrs.offset_within_region = sec_start; | |
2113 | sec_size = sec_end - sec_start; | |
2114 | mrs.size = int128_make64(sec_size); | |
2115 | listener->log_clear(listener, &mrs); | |
2116 | } | |
2117 | flatview_unref(view); | |
2118 | } | |
2119 | } | |
2120 | ||
0fe1eca7 PB |
2121 | DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr, |
2122 | hwaddr addr, | |
2123 | hwaddr size, | |
2124 | unsigned client) | |
2125 | { | |
2126 | assert(mr->ram_block); | |
2127 | memory_region_sync_dirty_bitmap(mr); | |
5dea4079 | 2128 | return cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client); |
0fe1eca7 PB |
2129 | } |
2130 | ||
2131 | bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap, | |
2132 | hwaddr addr, hwaddr size) | |
2133 | { | |
2134 | assert(mr->ram_block); | |
2135 | return cpu_physical_memory_snapshot_get_dirty(snap, | |
2136 | memory_region_get_ram_addr(mr) + addr, size); | |
2137 | } | |
2138 | ||
093bc2cd AK |
2139 | void memory_region_set_readonly(MemoryRegion *mr, bool readonly) |
2140 | { | |
fb1cd6f9 | 2141 | if (mr->readonly != readonly) { |
59023ef4 | 2142 | memory_region_transaction_begin(); |
fb1cd6f9 | 2143 | mr->readonly = readonly; |
22bde714 | 2144 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2145 | memory_region_transaction_commit(); |
fb1cd6f9 | 2146 | } |
093bc2cd AK |
2147 | } |
2148 | ||
c26763f8 MAL |
2149 | void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile) |
2150 | { | |
2151 | if (mr->nonvolatile != nonvolatile) { | |
2152 | memory_region_transaction_begin(); | |
2153 | mr->nonvolatile = nonvolatile; | |
2154 | memory_region_update_pending |= mr->enabled; | |
2155 | memory_region_transaction_commit(); | |
2156 | } | |
2157 | } | |
2158 | ||
5f9a5ea1 | 2159 | void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode) |
d0a9b5bc | 2160 | { |
5f9a5ea1 | 2161 | if (mr->romd_mode != romd_mode) { |
59023ef4 | 2162 | memory_region_transaction_begin(); |
5f9a5ea1 | 2163 | mr->romd_mode = romd_mode; |
22bde714 | 2164 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2165 | memory_region_transaction_commit(); |
d0a9b5bc AK |
2166 | } |
2167 | } | |
2168 | ||
a8170e5e AK |
2169 | void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr, |
2170 | hwaddr size, unsigned client) | |
093bc2cd | 2171 | { |
8e41fb63 FZ |
2172 | assert(mr->ram_block); |
2173 | cpu_physical_memory_test_and_clear_dirty( | |
2174 | memory_region_get_ram_addr(mr) + addr, size, client); | |
093bc2cd AK |
2175 | } |
2176 | ||
a35ba7be PB |
2177 | int memory_region_get_fd(MemoryRegion *mr) |
2178 | { | |
4ff87573 PB |
2179 | int fd; |
2180 | ||
2181 | rcu_read_lock(); | |
2182 | while (mr->alias) { | |
2183 | mr = mr->alias; | |
a35ba7be | 2184 | } |
4ff87573 PB |
2185 | fd = mr->ram_block->fd; |
2186 | rcu_read_unlock(); | |
a35ba7be | 2187 | |
4ff87573 PB |
2188 | return fd; |
2189 | } | |
a35ba7be | 2190 | |
093bc2cd AK |
2191 | void *memory_region_get_ram_ptr(MemoryRegion *mr) |
2192 | { | |
49b24afc PB |
2193 | void *ptr; |
2194 | uint64_t offset = 0; | |
093bc2cd | 2195 | |
49b24afc PB |
2196 | rcu_read_lock(); |
2197 | while (mr->alias) { | |
2198 | offset += mr->alias_offset; | |
2199 | mr = mr->alias; | |
2200 | } | |
8e41fb63 | 2201 | assert(mr->ram_block); |
0878d0e1 | 2202 | ptr = qemu_map_ram_ptr(mr->ram_block, offset); |
49b24afc | 2203 | rcu_read_unlock(); |
093bc2cd | 2204 | |
0878d0e1 | 2205 | return ptr; |
093bc2cd AK |
2206 | } |
2207 | ||
07bdaa41 PB |
2208 | MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset) |
2209 | { | |
2210 | RAMBlock *block; | |
2211 | ||
2212 | block = qemu_ram_block_from_host(ptr, false, offset); | |
2213 | if (!block) { | |
2214 | return NULL; | |
2215 | } | |
2216 | ||
2217 | return block->mr; | |
2218 | } | |
2219 | ||
7ebb2745 FZ |
2220 | ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr) |
2221 | { | |
2222 | return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID; | |
2223 | } | |
2224 | ||
37d7c084 PB |
2225 | void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp) |
2226 | { | |
8e41fb63 | 2227 | assert(mr->ram_block); |
37d7c084 | 2228 | |
fa53a0e5 | 2229 | qemu_ram_resize(mr->ram_block, newsize, errp); |
37d7c084 PB |
2230 | } |
2231 | ||
0d673e36 | 2232 | static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as) |
093bc2cd | 2233 | { |
99e86347 | 2234 | FlatView *view; |
093bc2cd | 2235 | FlatRange *fr; |
093bc2cd | 2236 | |
856d7245 | 2237 | view = address_space_get_flatview(as); |
99e86347 | 2238 | FOR_EACH_FLAT_RANGE(fr, view) { |
093bc2cd | 2239 | if (fr->mr == mr) { |
909bf763 PB |
2240 | flat_range_coalesced_io_del(fr, as); |
2241 | flat_range_coalesced_io_add(fr, as); | |
093bc2cd AK |
2242 | } |
2243 | } | |
856d7245 | 2244 | flatview_unref(view); |
093bc2cd AK |
2245 | } |
2246 | ||
0d673e36 AK |
2247 | static void memory_region_update_coalesced_range(MemoryRegion *mr) |
2248 | { | |
2249 | AddressSpace *as; | |
2250 | ||
2251 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
2252 | memory_region_update_coalesced_range_as(mr, as); | |
2253 | } | |
2254 | } | |
2255 | ||
093bc2cd AK |
2256 | void memory_region_set_coalescing(MemoryRegion *mr) |
2257 | { | |
2258 | memory_region_clear_coalescing(mr); | |
08dafab4 | 2259 | memory_region_add_coalescing(mr, 0, int128_get64(mr->size)); |
093bc2cd AK |
2260 | } |
2261 | ||
2262 | void memory_region_add_coalescing(MemoryRegion *mr, | |
a8170e5e | 2263 | hwaddr offset, |
093bc2cd AK |
2264 | uint64_t size) |
2265 | { | |
7267c094 | 2266 | CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr)); |
093bc2cd | 2267 | |
08dafab4 | 2268 | cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size)); |
093bc2cd AK |
2269 | QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); |
2270 | memory_region_update_coalesced_range(mr); | |
d410515e | 2271 | memory_region_set_flush_coalesced(mr); |
093bc2cd AK |
2272 | } |
2273 | ||
2274 | void memory_region_clear_coalescing(MemoryRegion *mr) | |
2275 | { | |
2276 | CoalescedMemoryRange *cmr; | |
ab5b3db5 | 2277 | bool updated = false; |
093bc2cd | 2278 | |
d410515e JK |
2279 | qemu_flush_coalesced_mmio_buffer(); |
2280 | mr->flush_coalesced_mmio = false; | |
2281 | ||
093bc2cd AK |
2282 | while (!QTAILQ_EMPTY(&mr->coalesced)) { |
2283 | cmr = QTAILQ_FIRST(&mr->coalesced); | |
2284 | QTAILQ_REMOVE(&mr->coalesced, cmr, link); | |
7267c094 | 2285 | g_free(cmr); |
ab5b3db5 FZ |
2286 | updated = true; |
2287 | } | |
2288 | ||
2289 | if (updated) { | |
2290 | memory_region_update_coalesced_range(mr); | |
093bc2cd | 2291 | } |
093bc2cd AK |
2292 | } |
2293 | ||
d410515e JK |
2294 | void memory_region_set_flush_coalesced(MemoryRegion *mr) |
2295 | { | |
2296 | mr->flush_coalesced_mmio = true; | |
2297 | } | |
2298 | ||
2299 | void memory_region_clear_flush_coalesced(MemoryRegion *mr) | |
2300 | { | |
2301 | qemu_flush_coalesced_mmio_buffer(); | |
2302 | if (QTAILQ_EMPTY(&mr->coalesced)) { | |
2303 | mr->flush_coalesced_mmio = false; | |
2304 | } | |
2305 | } | |
2306 | ||
196ea131 JK |
2307 | void memory_region_clear_global_locking(MemoryRegion *mr) |
2308 | { | |
2309 | mr->global_locking = false; | |
2310 | } | |
2311 | ||
8c56c1a5 PF |
2312 | static bool userspace_eventfd_warning; |
2313 | ||
3e9d69e7 | 2314 | void memory_region_add_eventfd(MemoryRegion *mr, |
a8170e5e | 2315 | hwaddr addr, |
3e9d69e7 AK |
2316 | unsigned size, |
2317 | bool match_data, | |
2318 | uint64_t data, | |
753d5e14 | 2319 | EventNotifier *e) |
3e9d69e7 AK |
2320 | { |
2321 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2322 | .addr.start = int128_make64(addr), |
2323 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2324 | .match_data = match_data, |
2325 | .data = data, | |
753d5e14 | 2326 | .e = e, |
3e9d69e7 AK |
2327 | }; |
2328 | unsigned i; | |
2329 | ||
8c56c1a5 PF |
2330 | if (kvm_enabled() && (!(kvm_eventfds_enabled() || |
2331 | userspace_eventfd_warning))) { | |
2332 | userspace_eventfd_warning = true; | |
2333 | error_report("Using eventfd without MMIO binding in KVM. " | |
2334 | "Suboptimal performance expected"); | |
2335 | } | |
2336 | ||
b8aecea2 JW |
2337 | if (size) { |
2338 | adjust_endianness(mr, &mrfd.data, size); | |
2339 | } | |
59023ef4 | 2340 | memory_region_transaction_begin(); |
3e9d69e7 | 2341 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2342 | if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2343 | break; |
2344 | } | |
2345 | } | |
2346 | ++mr->ioeventfd_nb; | |
7267c094 | 2347 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 AK |
2348 | sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); |
2349 | memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], | |
2350 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); | |
2351 | mr->ioeventfds[i] = mrfd; | |
4dc56152 | 2352 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2353 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2354 | } |
2355 | ||
2356 | void memory_region_del_eventfd(MemoryRegion *mr, | |
a8170e5e | 2357 | hwaddr addr, |
3e9d69e7 AK |
2358 | unsigned size, |
2359 | bool match_data, | |
2360 | uint64_t data, | |
753d5e14 | 2361 | EventNotifier *e) |
3e9d69e7 AK |
2362 | { |
2363 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2364 | .addr.start = int128_make64(addr), |
2365 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2366 | .match_data = match_data, |
2367 | .data = data, | |
753d5e14 | 2368 | .e = e, |
3e9d69e7 AK |
2369 | }; |
2370 | unsigned i; | |
2371 | ||
b8aecea2 JW |
2372 | if (size) { |
2373 | adjust_endianness(mr, &mrfd.data, size); | |
2374 | } | |
59023ef4 | 2375 | memory_region_transaction_begin(); |
3e9d69e7 | 2376 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2377 | if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2378 | break; |
2379 | } | |
2380 | } | |
2381 | assert(i != mr->ioeventfd_nb); | |
2382 | memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], | |
2383 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); | |
2384 | --mr->ioeventfd_nb; | |
7267c094 | 2385 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 | 2386 | sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); |
4dc56152 | 2387 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2388 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2389 | } |
2390 | ||
feca4ac1 | 2391 | static void memory_region_update_container_subregions(MemoryRegion *subregion) |
093bc2cd | 2392 | { |
feca4ac1 | 2393 | MemoryRegion *mr = subregion->container; |
093bc2cd AK |
2394 | MemoryRegion *other; |
2395 | ||
59023ef4 JK |
2396 | memory_region_transaction_begin(); |
2397 | ||
dfde4e6e | 2398 | memory_region_ref(subregion); |
093bc2cd AK |
2399 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { |
2400 | if (subregion->priority >= other->priority) { | |
2401 | QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); | |
2402 | goto done; | |
2403 | } | |
2404 | } | |
2405 | QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); | |
2406 | done: | |
22bde714 | 2407 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2408 | memory_region_transaction_commit(); |
093bc2cd AK |
2409 | } |
2410 | ||
0598701a PC |
2411 | static void memory_region_add_subregion_common(MemoryRegion *mr, |
2412 | hwaddr offset, | |
2413 | MemoryRegion *subregion) | |
2414 | { | |
feca4ac1 PB |
2415 | assert(!subregion->container); |
2416 | subregion->container = mr; | |
0598701a | 2417 | subregion->addr = offset; |
feca4ac1 | 2418 | memory_region_update_container_subregions(subregion); |
0598701a | 2419 | } |
093bc2cd AK |
2420 | |
2421 | void memory_region_add_subregion(MemoryRegion *mr, | |
a8170e5e | 2422 | hwaddr offset, |
093bc2cd AK |
2423 | MemoryRegion *subregion) |
2424 | { | |
093bc2cd AK |
2425 | subregion->priority = 0; |
2426 | memory_region_add_subregion_common(mr, offset, subregion); | |
2427 | } | |
2428 | ||
2429 | void memory_region_add_subregion_overlap(MemoryRegion *mr, | |
a8170e5e | 2430 | hwaddr offset, |
093bc2cd | 2431 | MemoryRegion *subregion, |
a1ff8ae0 | 2432 | int priority) |
093bc2cd | 2433 | { |
093bc2cd AK |
2434 | subregion->priority = priority; |
2435 | memory_region_add_subregion_common(mr, offset, subregion); | |
2436 | } | |
2437 | ||
2438 | void memory_region_del_subregion(MemoryRegion *mr, | |
2439 | MemoryRegion *subregion) | |
2440 | { | |
59023ef4 | 2441 | memory_region_transaction_begin(); |
feca4ac1 PB |
2442 | assert(subregion->container == mr); |
2443 | subregion->container = NULL; | |
093bc2cd | 2444 | QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); |
dfde4e6e | 2445 | memory_region_unref(subregion); |
22bde714 | 2446 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2447 | memory_region_transaction_commit(); |
6bba19ba AK |
2448 | } |
2449 | ||
2450 | void memory_region_set_enabled(MemoryRegion *mr, bool enabled) | |
2451 | { | |
2452 | if (enabled == mr->enabled) { | |
2453 | return; | |
2454 | } | |
59023ef4 | 2455 | memory_region_transaction_begin(); |
6bba19ba | 2456 | mr->enabled = enabled; |
22bde714 | 2457 | memory_region_update_pending = true; |
59023ef4 | 2458 | memory_region_transaction_commit(); |
093bc2cd | 2459 | } |
1c0ffa58 | 2460 | |
e7af4c67 MT |
2461 | void memory_region_set_size(MemoryRegion *mr, uint64_t size) |
2462 | { | |
2463 | Int128 s = int128_make64(size); | |
2464 | ||
2465 | if (size == UINT64_MAX) { | |
2466 | s = int128_2_64(); | |
2467 | } | |
2468 | if (int128_eq(s, mr->size)) { | |
2469 | return; | |
2470 | } | |
2471 | memory_region_transaction_begin(); | |
2472 | mr->size = s; | |
2473 | memory_region_update_pending = true; | |
2474 | memory_region_transaction_commit(); | |
2475 | } | |
2476 | ||
67891b8a | 2477 | static void memory_region_readd_subregion(MemoryRegion *mr) |
2282e1af | 2478 | { |
feca4ac1 | 2479 | MemoryRegion *container = mr->container; |
2282e1af | 2480 | |
feca4ac1 | 2481 | if (container) { |
67891b8a PC |
2482 | memory_region_transaction_begin(); |
2483 | memory_region_ref(mr); | |
feca4ac1 PB |
2484 | memory_region_del_subregion(container, mr); |
2485 | mr->container = container; | |
2486 | memory_region_update_container_subregions(mr); | |
67891b8a PC |
2487 | memory_region_unref(mr); |
2488 | memory_region_transaction_commit(); | |
2282e1af | 2489 | } |
67891b8a | 2490 | } |
2282e1af | 2491 | |
67891b8a PC |
2492 | void memory_region_set_address(MemoryRegion *mr, hwaddr addr) |
2493 | { | |
2494 | if (addr != mr->addr) { | |
2495 | mr->addr = addr; | |
2496 | memory_region_readd_subregion(mr); | |
2497 | } | |
2282e1af AK |
2498 | } |
2499 | ||
a8170e5e | 2500 | void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset) |
4703359e | 2501 | { |
4703359e | 2502 | assert(mr->alias); |
4703359e | 2503 | |
59023ef4 | 2504 | if (offset == mr->alias_offset) { |
4703359e AK |
2505 | return; |
2506 | } | |
2507 | ||
59023ef4 JK |
2508 | memory_region_transaction_begin(); |
2509 | mr->alias_offset = offset; | |
22bde714 | 2510 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2511 | memory_region_transaction_commit(); |
4703359e AK |
2512 | } |
2513 | ||
a2b257d6 IM |
2514 | uint64_t memory_region_get_alignment(const MemoryRegion *mr) |
2515 | { | |
2516 | return mr->align; | |
2517 | } | |
2518 | ||
e2177955 AK |
2519 | static int cmp_flatrange_addr(const void *addr_, const void *fr_) |
2520 | { | |
2521 | const AddrRange *addr = addr_; | |
2522 | const FlatRange *fr = fr_; | |
2523 | ||
2524 | if (int128_le(addrrange_end(*addr), fr->addr.start)) { | |
2525 | return -1; | |
2526 | } else if (int128_ge(addr->start, addrrange_end(fr->addr))) { | |
2527 | return 1; | |
2528 | } | |
2529 | return 0; | |
2530 | } | |
2531 | ||
99e86347 | 2532 | static FlatRange *flatview_lookup(FlatView *view, AddrRange addr) |
e2177955 | 2533 | { |
99e86347 | 2534 | return bsearch(&addr, view->ranges, view->nr, |
e2177955 AK |
2535 | sizeof(FlatRange), cmp_flatrange_addr); |
2536 | } | |
2537 | ||
eed2bacf IM |
2538 | bool memory_region_is_mapped(MemoryRegion *mr) |
2539 | { | |
2540 | return mr->container ? true : false; | |
2541 | } | |
2542 | ||
c6742b14 PB |
2543 | /* Same as memory_region_find, but it does not add a reference to the |
2544 | * returned region. It must be called from an RCU critical section. | |
2545 | */ | |
2546 | static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr, | |
2547 | hwaddr addr, uint64_t size) | |
e2177955 | 2548 | { |
052e87b0 | 2549 | MemoryRegionSection ret = { .mr = NULL }; |
73034e9e PB |
2550 | MemoryRegion *root; |
2551 | AddressSpace *as; | |
2552 | AddrRange range; | |
99e86347 | 2553 | FlatView *view; |
73034e9e PB |
2554 | FlatRange *fr; |
2555 | ||
2556 | addr += mr->addr; | |
feca4ac1 PB |
2557 | for (root = mr; root->container; ) { |
2558 | root = root->container; | |
73034e9e PB |
2559 | addr += root->addr; |
2560 | } | |
e2177955 | 2561 | |
73034e9e | 2562 | as = memory_region_to_address_space(root); |
eed2bacf IM |
2563 | if (!as) { |
2564 | return ret; | |
2565 | } | |
73034e9e | 2566 | range = addrrange_make(int128_make64(addr), int128_make64(size)); |
99e86347 | 2567 | |
16620684 | 2568 | view = address_space_to_flatview(as); |
99e86347 | 2569 | fr = flatview_lookup(view, range); |
e2177955 | 2570 | if (!fr) { |
c6742b14 | 2571 | return ret; |
e2177955 AK |
2572 | } |
2573 | ||
99e86347 | 2574 | while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) { |
e2177955 AK |
2575 | --fr; |
2576 | } | |
2577 | ||
2578 | ret.mr = fr->mr; | |
16620684 | 2579 | ret.fv = view; |
e2177955 AK |
2580 | range = addrrange_intersection(range, fr->addr); |
2581 | ret.offset_within_region = fr->offset_in_region; | |
2582 | ret.offset_within_region += int128_get64(int128_sub(range.start, | |
2583 | fr->addr.start)); | |
052e87b0 | 2584 | ret.size = range.size; |
e2177955 | 2585 | ret.offset_within_address_space = int128_get64(range.start); |
7a8499e8 | 2586 | ret.readonly = fr->readonly; |
c26763f8 | 2587 | ret.nonvolatile = fr->nonvolatile; |
c6742b14 PB |
2588 | return ret; |
2589 | } | |
2590 | ||
2591 | MemoryRegionSection memory_region_find(MemoryRegion *mr, | |
2592 | hwaddr addr, uint64_t size) | |
2593 | { | |
2594 | MemoryRegionSection ret; | |
2595 | rcu_read_lock(); | |
2596 | ret = memory_region_find_rcu(mr, addr, size); | |
2597 | if (ret.mr) { | |
2598 | memory_region_ref(ret.mr); | |
2599 | } | |
2b647668 | 2600 | rcu_read_unlock(); |
e2177955 AK |
2601 | return ret; |
2602 | } | |
2603 | ||
c6742b14 PB |
2604 | bool memory_region_present(MemoryRegion *container, hwaddr addr) |
2605 | { | |
2606 | MemoryRegion *mr; | |
2607 | ||
2608 | rcu_read_lock(); | |
2609 | mr = memory_region_find_rcu(container, addr, 1).mr; | |
2610 | rcu_read_unlock(); | |
2611 | return mr && mr != container; | |
2612 | } | |
2613 | ||
9c1f8f44 | 2614 | void memory_global_dirty_log_sync(void) |
86e775c6 | 2615 | { |
3ebb1817 | 2616 | memory_region_sync_dirty_bitmap(NULL); |
7664e80c AK |
2617 | } |
2618 | ||
19310760 JZ |
2619 | static VMChangeStateEntry *vmstate_change; |
2620 | ||
7664e80c AK |
2621 | void memory_global_dirty_log_start(void) |
2622 | { | |
19310760 JZ |
2623 | if (vmstate_change) { |
2624 | qemu_del_vm_change_state_handler(vmstate_change); | |
2625 | vmstate_change = NULL; | |
2626 | } | |
2627 | ||
7664e80c | 2628 | global_dirty_log = true; |
6f6a5ef3 | 2629 | |
7376e582 | 2630 | MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward); |
6f6a5ef3 | 2631 | |
39adb536 | 2632 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2633 | memory_region_transaction_begin(); |
2634 | memory_region_update_pending = true; | |
2635 | memory_region_transaction_commit(); | |
7664e80c AK |
2636 | } |
2637 | ||
19310760 | 2638 | static void memory_global_dirty_log_do_stop(void) |
7664e80c | 2639 | { |
7664e80c | 2640 | global_dirty_log = false; |
6f6a5ef3 | 2641 | |
39adb536 | 2642 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2643 | memory_region_transaction_begin(); |
2644 | memory_region_update_pending = true; | |
2645 | memory_region_transaction_commit(); | |
2646 | ||
7376e582 | 2647 | MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse); |
7664e80c AK |
2648 | } |
2649 | ||
19310760 JZ |
2650 | static void memory_vm_change_state_handler(void *opaque, int running, |
2651 | RunState state) | |
2652 | { | |
2653 | if (running) { | |
2654 | memory_global_dirty_log_do_stop(); | |
2655 | ||
2656 | if (vmstate_change) { | |
2657 | qemu_del_vm_change_state_handler(vmstate_change); | |
2658 | vmstate_change = NULL; | |
2659 | } | |
2660 | } | |
2661 | } | |
2662 | ||
2663 | void memory_global_dirty_log_stop(void) | |
2664 | { | |
2665 | if (!runstate_is_running()) { | |
2666 | if (vmstate_change) { | |
2667 | return; | |
2668 | } | |
2669 | vmstate_change = qemu_add_vm_change_state_handler( | |
2670 | memory_vm_change_state_handler, NULL); | |
2671 | return; | |
2672 | } | |
2673 | ||
2674 | memory_global_dirty_log_do_stop(); | |
2675 | } | |
2676 | ||
7664e80c AK |
2677 | static void listener_add_address_space(MemoryListener *listener, |
2678 | AddressSpace *as) | |
2679 | { | |
99e86347 | 2680 | FlatView *view; |
7664e80c AK |
2681 | FlatRange *fr; |
2682 | ||
680a4783 PB |
2683 | if (listener->begin) { |
2684 | listener->begin(listener); | |
2685 | } | |
7664e80c | 2686 | if (global_dirty_log) { |
975aefe0 AK |
2687 | if (listener->log_global_start) { |
2688 | listener->log_global_start(listener); | |
2689 | } | |
7664e80c | 2690 | } |
975aefe0 | 2691 | |
856d7245 | 2692 | view = address_space_get_flatview(as); |
99e86347 | 2693 | FOR_EACH_FLAT_RANGE(fr, view) { |
279836f8 DH |
2694 | MemoryRegionSection section = section_from_flat_range(fr, view); |
2695 | ||
975aefe0 AK |
2696 | if (listener->region_add) { |
2697 | listener->region_add(listener, §ion); | |
2698 | } | |
ae990e6c DH |
2699 | if (fr->dirty_log_mask && listener->log_start) { |
2700 | listener->log_start(listener, §ion, 0, fr->dirty_log_mask); | |
2701 | } | |
7664e80c | 2702 | } |
680a4783 PB |
2703 | if (listener->commit) { |
2704 | listener->commit(listener); | |
2705 | } | |
856d7245 | 2706 | flatview_unref(view); |
7664e80c AK |
2707 | } |
2708 | ||
d25836ca PX |
2709 | static void listener_del_address_space(MemoryListener *listener, |
2710 | AddressSpace *as) | |
2711 | { | |
2712 | FlatView *view; | |
2713 | FlatRange *fr; | |
2714 | ||
2715 | if (listener->begin) { | |
2716 | listener->begin(listener); | |
2717 | } | |
2718 | view = address_space_get_flatview(as); | |
2719 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2720 | MemoryRegionSection section = section_from_flat_range(fr, view); | |
2721 | ||
2722 | if (fr->dirty_log_mask && listener->log_stop) { | |
2723 | listener->log_stop(listener, §ion, fr->dirty_log_mask, 0); | |
2724 | } | |
2725 | if (listener->region_del) { | |
2726 | listener->region_del(listener, §ion); | |
2727 | } | |
2728 | } | |
2729 | if (listener->commit) { | |
2730 | listener->commit(listener); | |
2731 | } | |
2732 | flatview_unref(view); | |
2733 | } | |
2734 | ||
d45fa784 | 2735 | void memory_listener_register(MemoryListener *listener, AddressSpace *as) |
7664e80c | 2736 | { |
72e22d2f AK |
2737 | MemoryListener *other = NULL; |
2738 | ||
d45fa784 | 2739 | listener->address_space = as; |
72e22d2f | 2740 | if (QTAILQ_EMPTY(&memory_listeners) |
eae3eb3e | 2741 | || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) { |
72e22d2f AK |
2742 | QTAILQ_INSERT_TAIL(&memory_listeners, listener, link); |
2743 | } else { | |
2744 | QTAILQ_FOREACH(other, &memory_listeners, link) { | |
2745 | if (listener->priority < other->priority) { | |
2746 | break; | |
2747 | } | |
2748 | } | |
2749 | QTAILQ_INSERT_BEFORE(other, listener, link); | |
2750 | } | |
0d673e36 | 2751 | |
9a54635d | 2752 | if (QTAILQ_EMPTY(&as->listeners) |
eae3eb3e | 2753 | || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) { |
9a54635d PB |
2754 | QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as); |
2755 | } else { | |
2756 | QTAILQ_FOREACH(other, &as->listeners, link_as) { | |
2757 | if (listener->priority < other->priority) { | |
2758 | break; | |
2759 | } | |
2760 | } | |
2761 | QTAILQ_INSERT_BEFORE(other, listener, link_as); | |
2762 | } | |
2763 | ||
d45fa784 | 2764 | listener_add_address_space(listener, as); |
7664e80c AK |
2765 | } |
2766 | ||
2767 | void memory_listener_unregister(MemoryListener *listener) | |
2768 | { | |
1d8280c1 PB |
2769 | if (!listener->address_space) { |
2770 | return; | |
2771 | } | |
2772 | ||
d25836ca | 2773 | listener_del_address_space(listener, listener->address_space); |
72e22d2f | 2774 | QTAILQ_REMOVE(&memory_listeners, listener, link); |
9a54635d | 2775 | QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as); |
1d8280c1 | 2776 | listener->address_space = NULL; |
86e775c6 | 2777 | } |
e2177955 | 2778 | |
a2166410 GK |
2779 | void address_space_remove_listeners(AddressSpace *as) |
2780 | { | |
2781 | while (!QTAILQ_EMPTY(&as->listeners)) { | |
2782 | memory_listener_unregister(QTAILQ_FIRST(&as->listeners)); | |
2783 | } | |
2784 | } | |
2785 | ||
7dca8043 | 2786 | void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name) |
1c0ffa58 | 2787 | { |
ac95190e | 2788 | memory_region_ref(root); |
8786db7c | 2789 | as->root = root; |
67ace39b | 2790 | as->current_map = NULL; |
4c19eb72 AK |
2791 | as->ioeventfd_nb = 0; |
2792 | as->ioeventfds = NULL; | |
9a54635d | 2793 | QTAILQ_INIT(&as->listeners); |
0d673e36 | 2794 | QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link); |
7dca8043 | 2795 | as->name = g_strdup(name ? name : "anonymous"); |
202fc01b AK |
2796 | address_space_update_topology(as); |
2797 | address_space_update_ioeventfds(as); | |
1c0ffa58 | 2798 | } |
658b2224 | 2799 | |
374f2981 | 2800 | static void do_address_space_destroy(AddressSpace *as) |
83f3c251 | 2801 | { |
9a54635d | 2802 | assert(QTAILQ_EMPTY(&as->listeners)); |
078c44f4 | 2803 | |
856d7245 | 2804 | flatview_unref(as->current_map); |
7dca8043 | 2805 | g_free(as->name); |
4c19eb72 | 2806 | g_free(as->ioeventfds); |
ac95190e | 2807 | memory_region_unref(as->root); |
83f3c251 AK |
2808 | } |
2809 | ||
374f2981 PB |
2810 | void address_space_destroy(AddressSpace *as) |
2811 | { | |
ac95190e PB |
2812 | MemoryRegion *root = as->root; |
2813 | ||
374f2981 PB |
2814 | /* Flush out anything from MemoryListeners listening in on this */ |
2815 | memory_region_transaction_begin(); | |
2816 | as->root = NULL; | |
2817 | memory_region_transaction_commit(); | |
2818 | QTAILQ_REMOVE(&address_spaces, as, address_spaces_link); | |
2819 | ||
2820 | /* At this point, as->dispatch and as->current_map are dummy | |
2821 | * entries that the guest should never use. Wait for the old | |
2822 | * values to expire before freeing the data. | |
2823 | */ | |
ac95190e | 2824 | as->root = root; |
374f2981 PB |
2825 | call_rcu(as, do_address_space_destroy, rcu); |
2826 | } | |
2827 | ||
4e831901 PX |
2828 | static const char *memory_region_type(MemoryRegion *mr) |
2829 | { | |
2830 | if (memory_region_is_ram_device(mr)) { | |
2831 | return "ramd"; | |
2832 | } else if (memory_region_is_romd(mr)) { | |
2833 | return "romd"; | |
2834 | } else if (memory_region_is_rom(mr)) { | |
2835 | return "rom"; | |
2836 | } else if (memory_region_is_ram(mr)) { | |
2837 | return "ram"; | |
2838 | } else { | |
2839 | return "i/o"; | |
2840 | } | |
2841 | } | |
2842 | ||
314e2987 BS |
2843 | typedef struct MemoryRegionList MemoryRegionList; |
2844 | ||
2845 | struct MemoryRegionList { | |
2846 | const MemoryRegion *mr; | |
a16878d2 | 2847 | QTAILQ_ENTRY(MemoryRegionList) mrqueue; |
314e2987 BS |
2848 | }; |
2849 | ||
b58deb34 | 2850 | typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead; |
314e2987 | 2851 | |
4e831901 PX |
2852 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ |
2853 | int128_sub((size), int128_one())) : 0) | |
2854 | #define MTREE_INDENT " " | |
2855 | ||
b6b71cb5 | 2856 | static void mtree_expand_owner(const char *label, Object *obj) |
fc051ae6 AK |
2857 | { |
2858 | DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE); | |
2859 | ||
b6b71cb5 | 2860 | qemu_printf(" %s:{%s", label, dev ? "dev" : "obj"); |
fc051ae6 | 2861 | if (dev && dev->id) { |
b6b71cb5 | 2862 | qemu_printf(" id=%s", dev->id); |
fc051ae6 AK |
2863 | } else { |
2864 | gchar *canonical_path = object_get_canonical_path(obj); | |
2865 | if (canonical_path) { | |
b6b71cb5 | 2866 | qemu_printf(" path=%s", canonical_path); |
fc051ae6 AK |
2867 | g_free(canonical_path); |
2868 | } else { | |
b6b71cb5 | 2869 | qemu_printf(" type=%s", object_get_typename(obj)); |
fc051ae6 AK |
2870 | } |
2871 | } | |
b6b71cb5 | 2872 | qemu_printf("}"); |
fc051ae6 AK |
2873 | } |
2874 | ||
b6b71cb5 | 2875 | static void mtree_print_mr_owner(const MemoryRegion *mr) |
fc051ae6 AK |
2876 | { |
2877 | Object *owner = mr->owner; | |
2878 | Object *parent = memory_region_owner((MemoryRegion *)mr); | |
2879 | ||
2880 | if (!owner && !parent) { | |
b6b71cb5 | 2881 | qemu_printf(" orphan"); |
fc051ae6 AK |
2882 | return; |
2883 | } | |
2884 | if (owner) { | |
b6b71cb5 | 2885 | mtree_expand_owner("owner", owner); |
fc051ae6 AK |
2886 | } |
2887 | if (parent && parent != owner) { | |
b6b71cb5 | 2888 | mtree_expand_owner("parent", parent); |
fc051ae6 AK |
2889 | } |
2890 | } | |
2891 | ||
b6b71cb5 | 2892 | static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, |
a8170e5e | 2893 | hwaddr base, |
fc051ae6 AK |
2894 | MemoryRegionListHead *alias_print_queue, |
2895 | bool owner) | |
314e2987 | 2896 | { |
9479c57a JK |
2897 | MemoryRegionList *new_ml, *ml, *next_ml; |
2898 | MemoryRegionListHead submr_print_queue; | |
314e2987 BS |
2899 | const MemoryRegion *submr; |
2900 | unsigned int i; | |
b31f8412 | 2901 | hwaddr cur_start, cur_end; |
314e2987 | 2902 | |
f8a9f720 | 2903 | if (!mr) { |
314e2987 BS |
2904 | return; |
2905 | } | |
2906 | ||
2907 | for (i = 0; i < level; i++) { | |
b6b71cb5 | 2908 | qemu_printf(MTREE_INDENT); |
314e2987 BS |
2909 | } |
2910 | ||
b31f8412 PX |
2911 | cur_start = base + mr->addr; |
2912 | cur_end = cur_start + MR_SIZE(mr->size); | |
2913 | ||
2914 | /* | |
2915 | * Try to detect overflow of memory region. This should never | |
2916 | * happen normally. When it happens, we dump something to warn the | |
2917 | * user who is observing this. | |
2918 | */ | |
2919 | if (cur_start < base || cur_end < cur_start) { | |
b6b71cb5 | 2920 | qemu_printf("[DETECTED OVERFLOW!] "); |
b31f8412 PX |
2921 | } |
2922 | ||
314e2987 BS |
2923 | if (mr->alias) { |
2924 | MemoryRegionList *ml; | |
2925 | bool found = false; | |
2926 | ||
2927 | /* check if the alias is already in the queue */ | |
a16878d2 | 2928 | QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) { |
f54bb15f | 2929 | if (ml->mr == mr->alias) { |
314e2987 BS |
2930 | found = true; |
2931 | } | |
2932 | } | |
2933 | ||
2934 | if (!found) { | |
2935 | ml = g_new(MemoryRegionList, 1); | |
2936 | ml->mr = mr->alias; | |
a16878d2 | 2937 | QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue); |
314e2987 | 2938 | } |
b6b71cb5 MA |
2939 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2940 | " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx | |
2941 | "-" TARGET_FMT_plx "%s", | |
2942 | cur_start, cur_end, | |
2943 | mr->priority, | |
2944 | mr->nonvolatile ? "nv-" : "", | |
2945 | memory_region_type((MemoryRegion *)mr), | |
2946 | memory_region_name(mr), | |
2947 | memory_region_name(mr->alias), | |
2948 | mr->alias_offset, | |
2949 | mr->alias_offset + MR_SIZE(mr->size), | |
2950 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2951 | if (owner) { |
b6b71cb5 | 2952 | mtree_print_mr_owner(mr); |
fc051ae6 | 2953 | } |
314e2987 | 2954 | } else { |
b6b71cb5 MA |
2955 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2956 | " (prio %d, %s%s): %s%s", | |
2957 | cur_start, cur_end, | |
2958 | mr->priority, | |
2959 | mr->nonvolatile ? "nv-" : "", | |
2960 | memory_region_type((MemoryRegion *)mr), | |
2961 | memory_region_name(mr), | |
2962 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2963 | if (owner) { |
b6b71cb5 | 2964 | mtree_print_mr_owner(mr); |
fc051ae6 | 2965 | } |
314e2987 | 2966 | } |
b6b71cb5 | 2967 | qemu_printf("\n"); |
9479c57a JK |
2968 | |
2969 | QTAILQ_INIT(&submr_print_queue); | |
2970 | ||
314e2987 | 2971 | QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) { |
9479c57a JK |
2972 | new_ml = g_new(MemoryRegionList, 1); |
2973 | new_ml->mr = submr; | |
a16878d2 | 2974 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
9479c57a JK |
2975 | if (new_ml->mr->addr < ml->mr->addr || |
2976 | (new_ml->mr->addr == ml->mr->addr && | |
2977 | new_ml->mr->priority > ml->mr->priority)) { | |
a16878d2 | 2978 | QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue); |
9479c57a JK |
2979 | new_ml = NULL; |
2980 | break; | |
2981 | } | |
2982 | } | |
2983 | if (new_ml) { | |
a16878d2 | 2984 | QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue); |
9479c57a JK |
2985 | } |
2986 | } | |
2987 | ||
a16878d2 | 2988 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
b6b71cb5 | 2989 | mtree_print_mr(ml->mr, level + 1, cur_start, |
fc051ae6 | 2990 | alias_print_queue, owner); |
9479c57a JK |
2991 | } |
2992 | ||
a16878d2 | 2993 | QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) { |
9479c57a | 2994 | g_free(ml); |
314e2987 BS |
2995 | } |
2996 | } | |
2997 | ||
5e8fd947 | 2998 | struct FlatViewInfo { |
5e8fd947 AK |
2999 | int counter; |
3000 | bool dispatch_tree; | |
fc051ae6 | 3001 | bool owner; |
5e8fd947 AK |
3002 | }; |
3003 | ||
3004 | static void mtree_print_flatview(gpointer key, gpointer value, | |
3005 | gpointer user_data) | |
57bb40c9 | 3006 | { |
5e8fd947 AK |
3007 | FlatView *view = key; |
3008 | GArray *fv_address_spaces = value; | |
3009 | struct FlatViewInfo *fvi = user_data; | |
57bb40c9 PX |
3010 | FlatRange *range = &view->ranges[0]; |
3011 | MemoryRegion *mr; | |
3012 | int n = view->nr; | |
5e8fd947 AK |
3013 | int i; |
3014 | AddressSpace *as; | |
3015 | ||
b6b71cb5 | 3016 | qemu_printf("FlatView #%d\n", fvi->counter); |
5e8fd947 AK |
3017 | ++fvi->counter; |
3018 | ||
3019 | for (i = 0; i < fv_address_spaces->len; ++i) { | |
3020 | as = g_array_index(fv_address_spaces, AddressSpace*, i); | |
b6b71cb5 MA |
3021 | qemu_printf(" AS \"%s\", root: %s", |
3022 | as->name, memory_region_name(as->root)); | |
5e8fd947 | 3023 | if (as->root->alias) { |
b6b71cb5 | 3024 | qemu_printf(", alias %s", memory_region_name(as->root->alias)); |
5e8fd947 | 3025 | } |
b6b71cb5 | 3026 | qemu_printf("\n"); |
5e8fd947 AK |
3027 | } |
3028 | ||
b6b71cb5 | 3029 | qemu_printf(" Root memory region: %s\n", |
5e8fd947 | 3030 | view->root ? memory_region_name(view->root) : "(none)"); |
57bb40c9 PX |
3031 | |
3032 | if (n <= 0) { | |
b6b71cb5 | 3033 | qemu_printf(MTREE_INDENT "No rendered FlatView\n\n"); |
57bb40c9 PX |
3034 | return; |
3035 | } | |
3036 | ||
3037 | while (n--) { | |
3038 | mr = range->mr; | |
377a07aa | 3039 | if (range->offset_in_region) { |
b6b71cb5 MA |
3040 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3041 | " (prio %d, %s%s): %s @" TARGET_FMT_plx, | |
3042 | int128_get64(range->addr.start), | |
3043 | int128_get64(range->addr.start) | |
3044 | + MR_SIZE(range->addr.size), | |
3045 | mr->priority, | |
3046 | range->nonvolatile ? "nv-" : "", | |
3047 | range->readonly ? "rom" : memory_region_type(mr), | |
3048 | memory_region_name(mr), | |
3049 | range->offset_in_region); | |
377a07aa | 3050 | } else { |
b6b71cb5 MA |
3051 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3052 | " (prio %d, %s%s): %s", | |
3053 | int128_get64(range->addr.start), | |
3054 | int128_get64(range->addr.start) | |
3055 | + MR_SIZE(range->addr.size), | |
3056 | mr->priority, | |
3057 | range->nonvolatile ? "nv-" : "", | |
3058 | range->readonly ? "rom" : memory_region_type(mr), | |
3059 | memory_region_name(mr)); | |
377a07aa | 3060 | } |
fc051ae6 | 3061 | if (fvi->owner) { |
b6b71cb5 | 3062 | mtree_print_mr_owner(mr); |
fc051ae6 | 3063 | } |
b6b71cb5 | 3064 | qemu_printf("\n"); |
57bb40c9 PX |
3065 | range++; |
3066 | } | |
3067 | ||
5e8fd947 AK |
3068 | #if !defined(CONFIG_USER_ONLY) |
3069 | if (fvi->dispatch_tree && view->root) { | |
b6b71cb5 | 3070 | mtree_print_dispatch(view->dispatch, view->root); |
5e8fd947 AK |
3071 | } |
3072 | #endif | |
3073 | ||
b6b71cb5 | 3074 | qemu_printf("\n"); |
5e8fd947 AK |
3075 | } |
3076 | ||
3077 | static gboolean mtree_info_flatview_free(gpointer key, gpointer value, | |
3078 | gpointer user_data) | |
3079 | { | |
3080 | FlatView *view = key; | |
3081 | GArray *fv_address_spaces = value; | |
3082 | ||
3083 | g_array_unref(fv_address_spaces); | |
57bb40c9 | 3084 | flatview_unref(view); |
5e8fd947 AK |
3085 | |
3086 | return true; | |
57bb40c9 PX |
3087 | } |
3088 | ||
b6b71cb5 | 3089 | void mtree_info(bool flatview, bool dispatch_tree, bool owner) |
314e2987 BS |
3090 | { |
3091 | MemoryRegionListHead ml_head; | |
3092 | MemoryRegionList *ml, *ml2; | |
0d673e36 | 3093 | AddressSpace *as; |
314e2987 | 3094 | |
57bb40c9 | 3095 | if (flatview) { |
5e8fd947 AK |
3096 | FlatView *view; |
3097 | struct FlatViewInfo fvi = { | |
5e8fd947 | 3098 | .counter = 0, |
fc051ae6 AK |
3099 | .dispatch_tree = dispatch_tree, |
3100 | .owner = owner, | |
5e8fd947 AK |
3101 | }; |
3102 | GArray *fv_address_spaces; | |
3103 | GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal); | |
3104 | ||
3105 | /* Gather all FVs in one table */ | |
57bb40c9 | 3106 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
5e8fd947 AK |
3107 | view = address_space_get_flatview(as); |
3108 | ||
3109 | fv_address_spaces = g_hash_table_lookup(views, view); | |
3110 | if (!fv_address_spaces) { | |
3111 | fv_address_spaces = g_array_new(false, false, sizeof(as)); | |
3112 | g_hash_table_insert(views, view, fv_address_spaces); | |
3113 | } | |
3114 | ||
3115 | g_array_append_val(fv_address_spaces, as); | |
57bb40c9 | 3116 | } |
5e8fd947 AK |
3117 | |
3118 | /* Print */ | |
3119 | g_hash_table_foreach(views, mtree_print_flatview, &fvi); | |
3120 | ||
3121 | /* Free */ | |
3122 | g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0); | |
3123 | g_hash_table_unref(views); | |
3124 | ||
57bb40c9 PX |
3125 | return; |
3126 | } | |
3127 | ||
314e2987 BS |
3128 | QTAILQ_INIT(&ml_head); |
3129 | ||
0d673e36 | 3130 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
b6b71cb5 MA |
3131 | qemu_printf("address-space: %s\n", as->name); |
3132 | mtree_print_mr(as->root, 1, 0, &ml_head, owner); | |
3133 | qemu_printf("\n"); | |
b9f9be88 BS |
3134 | } |
3135 | ||
314e2987 | 3136 | /* print aliased regions */ |
a16878d2 | 3137 | QTAILQ_FOREACH(ml, &ml_head, mrqueue) { |
b6b71cb5 MA |
3138 | qemu_printf("memory-region: %s\n", memory_region_name(ml->mr)); |
3139 | mtree_print_mr(ml->mr, 1, 0, &ml_head, owner); | |
3140 | qemu_printf("\n"); | |
314e2987 BS |
3141 | } |
3142 | ||
a16878d2 | 3143 | QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) { |
88365e47 | 3144 | g_free(ml); |
314e2987 | 3145 | } |
314e2987 | 3146 | } |
b4fefef9 | 3147 | |
b08199c6 PM |
3148 | void memory_region_init_ram(MemoryRegion *mr, |
3149 | struct Object *owner, | |
3150 | const char *name, | |
3151 | uint64_t size, | |
3152 | Error **errp) | |
3153 | { | |
3154 | DeviceState *owner_dev; | |
3155 | Error *err = NULL; | |
3156 | ||
3157 | memory_region_init_ram_nomigrate(mr, owner, name, size, &err); | |
3158 | if (err) { | |
3159 | error_propagate(errp, err); | |
3160 | return; | |
3161 | } | |
3162 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3163 | * We only want the owner here for the purposes of defining a | |
3164 | * unique name for migration. TODO: Ideally we should implement | |
3165 | * a naming scheme for Objects which are not DeviceStates, in | |
3166 | * which case we can relax this restriction. | |
3167 | */ | |
3168 | owner_dev = DEVICE(owner); | |
3169 | vmstate_register_ram(mr, owner_dev); | |
3170 | } | |
3171 | ||
3172 | void memory_region_init_rom(MemoryRegion *mr, | |
3173 | struct Object *owner, | |
3174 | const char *name, | |
3175 | uint64_t size, | |
3176 | Error **errp) | |
3177 | { | |
3178 | DeviceState *owner_dev; | |
3179 | Error *err = NULL; | |
3180 | ||
3181 | memory_region_init_rom_nomigrate(mr, owner, name, size, &err); | |
3182 | if (err) { | |
3183 | error_propagate(errp, err); | |
3184 | return; | |
3185 | } | |
3186 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3187 | * We only want the owner here for the purposes of defining a | |
3188 | * unique name for migration. TODO: Ideally we should implement | |
3189 | * a naming scheme for Objects which are not DeviceStates, in | |
3190 | * which case we can relax this restriction. | |
3191 | */ | |
3192 | owner_dev = DEVICE(owner); | |
3193 | vmstate_register_ram(mr, owner_dev); | |
3194 | } | |
3195 | ||
3196 | void memory_region_init_rom_device(MemoryRegion *mr, | |
3197 | struct Object *owner, | |
3198 | const MemoryRegionOps *ops, | |
3199 | void *opaque, | |
3200 | const char *name, | |
3201 | uint64_t size, | |
3202 | Error **errp) | |
3203 | { | |
3204 | DeviceState *owner_dev; | |
3205 | Error *err = NULL; | |
3206 | ||
3207 | memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque, | |
3208 | name, size, &err); | |
3209 | if (err) { | |
3210 | error_propagate(errp, err); | |
3211 | return; | |
3212 | } | |
3213 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3214 | * We only want the owner here for the purposes of defining a | |
3215 | * unique name for migration. TODO: Ideally we should implement | |
3216 | * a naming scheme for Objects which are not DeviceStates, in | |
3217 | * which case we can relax this restriction. | |
3218 | */ | |
3219 | owner_dev = DEVICE(owner); | |
3220 | vmstate_register_ram(mr, owner_dev); | |
3221 | } | |
3222 | ||
b4fefef9 PC |
3223 | static const TypeInfo memory_region_info = { |
3224 | .parent = TYPE_OBJECT, | |
3225 | .name = TYPE_MEMORY_REGION, | |
3226 | .instance_size = sizeof(MemoryRegion), | |
3227 | .instance_init = memory_region_initfn, | |
3228 | .instance_finalize = memory_region_finalize, | |
3229 | }; | |
3230 | ||
3df9d748 AK |
3231 | static const TypeInfo iommu_memory_region_info = { |
3232 | .parent = TYPE_MEMORY_REGION, | |
3233 | .name = TYPE_IOMMU_MEMORY_REGION, | |
1221a474 | 3234 | .class_size = sizeof(IOMMUMemoryRegionClass), |
3df9d748 AK |
3235 | .instance_size = sizeof(IOMMUMemoryRegion), |
3236 | .instance_init = iommu_memory_region_initfn, | |
1221a474 | 3237 | .abstract = true, |
3df9d748 AK |
3238 | }; |
3239 | ||
b4fefef9 PC |
3240 | static void memory_register_types(void) |
3241 | { | |
3242 | type_register_static(&memory_region_info); | |
3df9d748 | 3243 | type_register_static(&iommu_memory_region_info); |
b4fefef9 PC |
3244 | } |
3245 | ||
3246 | type_init(memory_register_types) |