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c6dc6f63 AP |
1 | /* |
2 | * i386 CPUID helper functions | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdlib.h> | |
20 | #include <stdio.h> | |
21 | #include <string.h> | |
22 | #include <inttypes.h> | |
23 | ||
24 | #include "cpu.h" | |
25 | #include "kvm.h" | |
26 | ||
27 | #include "qemu-option.h" | |
28 | #include "qemu-config.h" | |
29 | ||
28f52cc0 VR |
30 | #include "hyperv.h" |
31 | ||
c6dc6f63 AP |
32 | /* feature flags taken from "Intel Processor Identification and the CPUID |
33 | * Instruction" and AMD's "CPUID Specification". In cases of disagreement | |
34 | * between feature naming conventions, aliases may be added. | |
35 | */ | |
36 | static const char *feature_name[] = { | |
37 | "fpu", "vme", "de", "pse", | |
38 | "tsc", "msr", "pae", "mce", | |
39 | "cx8", "apic", NULL, "sep", | |
40 | "mtrr", "pge", "mca", "cmov", | |
41 | "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, | |
42 | NULL, "ds" /* Intel dts */, "acpi", "mmx", | |
43 | "fxsr", "sse", "sse2", "ss", | |
44 | "ht" /* Intel htt */, "tm", "ia64", "pbe", | |
45 | }; | |
46 | static const char *ext_feature_name[] = { | |
f370be3c | 47 | "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor", |
e117f772 | 48 | "ds_cpl", "vmx", "smx", "est", |
c6dc6f63 | 49 | "tm2", "ssse3", "cid", NULL, |
e117f772 | 50 | "fma", "cx16", "xtpr", "pdcm", |
c6dc6f63 | 51 | NULL, NULL, "dca", "sse4.1|sse4_1", |
e117f772 | 52 | "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", |
eaf3f097 | 53 | "tsc-deadline", "aes", "xsave", "osxsave", |
e117f772 | 54 | "avx", NULL, NULL, "hypervisor", |
c6dc6f63 AP |
55 | }; |
56 | static const char *ext2_feature_name[] = { | |
57 | "fpu", "vme", "de", "pse", | |
58 | "tsc", "msr", "pae", "mce", | |
59 | "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", | |
60 | "mtrr", "pge", "mca", "cmov", | |
61 | "pat", "pse36", NULL, NULL /* Linux mp */, | |
3ac8ebfe | 62 | "nx|xd", NULL, "mmxext", "mmx", |
f370be3c | 63 | "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp", |
3ac8ebfe | 64 | NULL, "lm|i64", "3dnowext", "3dnow", |
c6dc6f63 AP |
65 | }; |
66 | static const char *ext3_feature_name[] = { | |
67 | "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, | |
68 | "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", | |
e117f772 | 69 | "3dnowprefetch", "osvw", "ibs", "xop", |
c6dc6f63 | 70 | "skinit", "wdt", NULL, NULL, |
e117f772 | 71 | "fma4", NULL, "cvt16", "nodeid_msr", |
c6dc6f63 AP |
72 | NULL, NULL, NULL, NULL, |
73 | NULL, NULL, NULL, NULL, | |
74 | NULL, NULL, NULL, NULL, | |
75 | }; | |
76 | ||
77 | static const char *kvm_feature_name[] = { | |
642258c6 | 78 | "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL, |
c6dc6f63 AP |
79 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
80 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
81 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
82 | }; | |
83 | ||
296acb64 JR |
84 | static const char *svm_feature_name[] = { |
85 | "npt", "lbrv", "svm_lock", "nrip_save", | |
86 | "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", | |
87 | NULL, NULL, "pause_filter", NULL, | |
88 | "pfthreshold", NULL, NULL, NULL, | |
89 | NULL, NULL, NULL, NULL, | |
90 | NULL, NULL, NULL, NULL, | |
91 | NULL, NULL, NULL, NULL, | |
92 | NULL, NULL, NULL, NULL, | |
93 | }; | |
94 | ||
c6dc6f63 AP |
95 | /* collects per-function cpuid data |
96 | */ | |
97 | typedef struct model_features_t { | |
98 | uint32_t *guest_feat; | |
99 | uint32_t *host_feat; | |
100 | uint32_t check_feat; | |
101 | const char **flag_names; | |
102 | uint32_t cpuid; | |
103 | } model_features_t; | |
104 | ||
105 | int check_cpuid = 0; | |
106 | int enforce_cpuid = 0; | |
107 | ||
bb44e0d1 JK |
108 | void host_cpuid(uint32_t function, uint32_t count, |
109 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) | |
bdde476a AP |
110 | { |
111 | #if defined(CONFIG_KVM) | |
a1fd24af AL |
112 | uint32_t vec[4]; |
113 | ||
114 | #ifdef __x86_64__ | |
115 | asm volatile("cpuid" | |
116 | : "=a"(vec[0]), "=b"(vec[1]), | |
117 | "=c"(vec[2]), "=d"(vec[3]) | |
118 | : "0"(function), "c"(count) : "cc"); | |
119 | #else | |
120 | asm volatile("pusha \n\t" | |
121 | "cpuid \n\t" | |
122 | "mov %%eax, 0(%2) \n\t" | |
123 | "mov %%ebx, 4(%2) \n\t" | |
124 | "mov %%ecx, 8(%2) \n\t" | |
125 | "mov %%edx, 12(%2) \n\t" | |
126 | "popa" | |
127 | : : "a"(function), "c"(count), "S"(vec) | |
128 | : "memory", "cc"); | |
129 | #endif | |
130 | ||
bdde476a | 131 | if (eax) |
a1fd24af | 132 | *eax = vec[0]; |
bdde476a | 133 | if (ebx) |
a1fd24af | 134 | *ebx = vec[1]; |
bdde476a | 135 | if (ecx) |
a1fd24af | 136 | *ecx = vec[2]; |
bdde476a | 137 | if (edx) |
a1fd24af | 138 | *edx = vec[3]; |
bdde476a AP |
139 | #endif |
140 | } | |
c6dc6f63 AP |
141 | |
142 | #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) | |
143 | ||
144 | /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of | |
145 | * a substring. ex if !NULL points to the first char after a substring, | |
146 | * otherwise the string is assumed to sized by a terminating nul. | |
147 | * Return lexical ordering of *s1:*s2. | |
148 | */ | |
149 | static int sstrcmp(const char *s1, const char *e1, const char *s2, | |
150 | const char *e2) | |
151 | { | |
152 | for (;;) { | |
153 | if (!*s1 || !*s2 || *s1 != *s2) | |
154 | return (*s1 - *s2); | |
155 | ++s1, ++s2; | |
156 | if (s1 == e1 && s2 == e2) | |
157 | return (0); | |
158 | else if (s1 == e1) | |
159 | return (*s2); | |
160 | else if (s2 == e2) | |
161 | return (*s1); | |
162 | } | |
163 | } | |
164 | ||
165 | /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple | |
166 | * '|' delimited (possibly empty) strings in which case search for a match | |
167 | * within the alternatives proceeds left to right. Return 0 for success, | |
168 | * non-zero otherwise. | |
169 | */ | |
170 | static int altcmp(const char *s, const char *e, const char *altstr) | |
171 | { | |
172 | const char *p, *q; | |
173 | ||
174 | for (q = p = altstr; ; ) { | |
175 | while (*p && *p != '|') | |
176 | ++p; | |
177 | if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p))) | |
178 | return (0); | |
179 | if (!*p) | |
180 | return (1); | |
181 | else | |
182 | q = ++p; | |
183 | } | |
184 | } | |
185 | ||
186 | /* search featureset for flag *[s..e), if found set corresponding bit in | |
e41e0fc6 | 187 | * *pval and return true, otherwise return false |
c6dc6f63 | 188 | */ |
e41e0fc6 JK |
189 | static bool lookup_feature(uint32_t *pval, const char *s, const char *e, |
190 | const char **featureset) | |
c6dc6f63 AP |
191 | { |
192 | uint32_t mask; | |
193 | const char **ppc; | |
e41e0fc6 | 194 | bool found = false; |
c6dc6f63 | 195 | |
e41e0fc6 | 196 | for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { |
c6dc6f63 AP |
197 | if (*ppc && !altcmp(s, e, *ppc)) { |
198 | *pval |= mask; | |
e41e0fc6 | 199 | found = true; |
c6dc6f63 | 200 | } |
e41e0fc6 JK |
201 | } |
202 | return found; | |
c6dc6f63 AP |
203 | } |
204 | ||
205 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, | |
206 | uint32_t *ext_features, | |
207 | uint32_t *ext2_features, | |
208 | uint32_t *ext3_features, | |
296acb64 JR |
209 | uint32_t *kvm_features, |
210 | uint32_t *svm_features) | |
c6dc6f63 AP |
211 | { |
212 | if (!lookup_feature(features, flagname, NULL, feature_name) && | |
213 | !lookup_feature(ext_features, flagname, NULL, ext_feature_name) && | |
214 | !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) && | |
215 | !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) && | |
296acb64 JR |
216 | !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) && |
217 | !lookup_feature(svm_features, flagname, NULL, svm_feature_name)) | |
c6dc6f63 AP |
218 | fprintf(stderr, "CPU feature %s not found\n", flagname); |
219 | } | |
220 | ||
221 | typedef struct x86_def_t { | |
222 | struct x86_def_t *next; | |
223 | const char *name; | |
224 | uint32_t level; | |
225 | uint32_t vendor1, vendor2, vendor3; | |
226 | int family; | |
227 | int model; | |
228 | int stepping; | |
b862d1fe | 229 | int tsc_khz; |
296acb64 JR |
230 | uint32_t features, ext_features, ext2_features, ext3_features; |
231 | uint32_t kvm_features, svm_features; | |
c6dc6f63 AP |
232 | uint32_t xlevel; |
233 | char model_id[48]; | |
234 | int vendor_override; | |
235 | uint32_t flags; | |
b3baa152 BW |
236 | /* Store the results of Centaur's CPUID instructions */ |
237 | uint32_t ext4_features; | |
238 | uint32_t xlevel2; | |
c6dc6f63 AP |
239 | } x86_def_t; |
240 | ||
241 | #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) | |
242 | #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ | |
243 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) | |
244 | #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ | |
245 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
246 | CPUID_PSE36 | CPUID_FXSR) | |
247 | #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) | |
248 | #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ | |
249 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ | |
250 | CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ | |
251 | CPUID_PAE | CPUID_SEP | CPUID_APIC) | |
42673936 | 252 | #define EXT2_FEATURE_MASK 0x0183F3FF |
c6dc6f63 | 253 | |
551a2dec AP |
254 | #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ |
255 | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ | |
256 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
257 | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ | |
258 | CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) | |
8560efed AJ |
259 | /* partly implemented: |
260 | CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) | |
261 | CPUID_PSE36 (needed for Solaris) */ | |
262 | /* missing: | |
263 | CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ | |
551a2dec | 264 | #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ |
8713f8ff | 265 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ |
551a2dec | 266 | CPUID_EXT_HYPERVISOR) |
8560efed AJ |
267 | /* missing: |
268 | CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST, | |
8713f8ff | 269 | CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */ |
551a2dec AP |
270 | #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \ |
271 | CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ | |
272 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) | |
8560efed AJ |
273 | /* missing: |
274 | CPUID_EXT2_PDPE1GB */ | |
551a2dec AP |
275 | #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ |
276 | CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) | |
296acb64 | 277 | #define TCG_SVM_FEATURES 0 |
551a2dec | 278 | |
c6dc6f63 AP |
279 | /* maintains list of cpu model definitions |
280 | */ | |
281 | static x86_def_t *x86_defs = {NULL}; | |
282 | ||
283 | /* built-in cpu model definitions (deprecated) | |
284 | */ | |
285 | static x86_def_t builtin_x86_defs[] = { | |
c6dc6f63 AP |
286 | { |
287 | .name = "qemu64", | |
288 | .level = 4, | |
289 | .vendor1 = CPUID_VENDOR_AMD_1, | |
290 | .vendor2 = CPUID_VENDOR_AMD_2, | |
291 | .vendor3 = CPUID_VENDOR_AMD_3, | |
292 | .family = 6, | |
293 | .model = 2, | |
294 | .stepping = 3, | |
295 | .features = PPRO_FEATURES | | |
c6dc6f63 | 296 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
c6dc6f63 AP |
297 | CPUID_PSE36, |
298 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, | |
42673936 | 299 | .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
c6dc6f63 AP |
300 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
301 | .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | | |
302 | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, | |
303 | .xlevel = 0x8000000A, | |
304 | .model_id = "QEMU Virtual CPU version " QEMU_VERSION, | |
305 | }, | |
306 | { | |
307 | .name = "phenom", | |
308 | .level = 5, | |
309 | .vendor1 = CPUID_VENDOR_AMD_1, | |
310 | .vendor2 = CPUID_VENDOR_AMD_2, | |
311 | .vendor3 = CPUID_VENDOR_AMD_3, | |
312 | .family = 16, | |
313 | .model = 2, | |
314 | .stepping = 3, | |
c6dc6f63 AP |
315 | .features = PPRO_FEATURES | |
316 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
8560efed | 317 | CPUID_PSE36 | CPUID_VME | CPUID_HT, |
c6dc6f63 AP |
318 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
319 | CPUID_EXT_POPCNT, | |
42673936 | 320 | .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
c6dc6f63 AP |
321 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
322 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | | |
8560efed | 323 | CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, |
c6dc6f63 AP |
324 | /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, |
325 | CPUID_EXT3_CR8LEG, | |
326 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
327 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ | |
328 | .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | | |
329 | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, | |
296acb64 | 330 | .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV, |
c6dc6f63 AP |
331 | .xlevel = 0x8000001A, |
332 | .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" | |
333 | }, | |
334 | { | |
335 | .name = "core2duo", | |
336 | .level = 10, | |
337 | .family = 6, | |
338 | .model = 15, | |
339 | .stepping = 11, | |
c6dc6f63 AP |
340 | .features = PPRO_FEATURES | |
341 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
8560efed AJ |
342 | CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | |
343 | CPUID_HT | CPUID_TM | CPUID_PBE, | |
344 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | | |
345 | CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | | |
346 | CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, | |
c6dc6f63 AP |
347 | .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
348 | .ext3_features = CPUID_EXT3_LAHF_LM, | |
349 | .xlevel = 0x80000008, | |
350 | .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", | |
351 | }, | |
352 | { | |
353 | .name = "kvm64", | |
354 | .level = 5, | |
355 | .vendor1 = CPUID_VENDOR_INTEL_1, | |
356 | .vendor2 = CPUID_VENDOR_INTEL_2, | |
357 | .vendor3 = CPUID_VENDOR_INTEL_3, | |
358 | .family = 15, | |
359 | .model = 6, | |
360 | .stepping = 1, | |
361 | /* Missing: CPUID_VME, CPUID_HT */ | |
362 | .features = PPRO_FEATURES | | |
363 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
364 | CPUID_PSE36, | |
365 | /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ | |
366 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, | |
367 | /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ | |
42673936 | 368 | .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
c6dc6f63 AP |
369 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
370 | /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, | |
371 | CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, | |
372 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
373 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ | |
374 | .ext3_features = 0, | |
375 | .xlevel = 0x80000008, | |
376 | .model_id = "Common KVM processor" | |
377 | }, | |
c6dc6f63 AP |
378 | { |
379 | .name = "qemu32", | |
380 | .level = 4, | |
381 | .family = 6, | |
382 | .model = 3, | |
383 | .stepping = 3, | |
384 | .features = PPRO_FEATURES, | |
385 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, | |
58012d66 | 386 | .xlevel = 0x80000004, |
c6dc6f63 AP |
387 | .model_id = "QEMU Virtual CPU version " QEMU_VERSION, |
388 | }, | |
eafaf1e5 AP |
389 | { |
390 | .name = "kvm32", | |
391 | .level = 5, | |
392 | .family = 15, | |
393 | .model = 6, | |
394 | .stepping = 1, | |
395 | .features = PPRO_FEATURES | | |
396 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, | |
397 | .ext_features = CPUID_EXT_SSE3, | |
398 | .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK, | |
399 | .ext3_features = 0, | |
400 | .xlevel = 0x80000008, | |
401 | .model_id = "Common 32-bit KVM processor" | |
402 | }, | |
c6dc6f63 AP |
403 | { |
404 | .name = "coreduo", | |
405 | .level = 10, | |
406 | .family = 6, | |
407 | .model = 14, | |
408 | .stepping = 8, | |
c6dc6f63 | 409 | .features = PPRO_FEATURES | CPUID_VME | |
8560efed AJ |
410 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | |
411 | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, | |
412 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | | |
413 | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, | |
c6dc6f63 AP |
414 | .ext2_features = CPUID_EXT2_NX, |
415 | .xlevel = 0x80000008, | |
416 | .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", | |
417 | }, | |
418 | { | |
419 | .name = "486", | |
58012d66 | 420 | .level = 1, |
c6dc6f63 AP |
421 | .family = 4, |
422 | .model = 0, | |
423 | .stepping = 0, | |
424 | .features = I486_FEATURES, | |
425 | .xlevel = 0, | |
426 | }, | |
427 | { | |
428 | .name = "pentium", | |
429 | .level = 1, | |
430 | .family = 5, | |
431 | .model = 4, | |
432 | .stepping = 3, | |
433 | .features = PENTIUM_FEATURES, | |
434 | .xlevel = 0, | |
435 | }, | |
436 | { | |
437 | .name = "pentium2", | |
438 | .level = 2, | |
439 | .family = 6, | |
440 | .model = 5, | |
441 | .stepping = 2, | |
442 | .features = PENTIUM2_FEATURES, | |
443 | .xlevel = 0, | |
444 | }, | |
445 | { | |
446 | .name = "pentium3", | |
447 | .level = 2, | |
448 | .family = 6, | |
449 | .model = 7, | |
450 | .stepping = 3, | |
451 | .features = PENTIUM3_FEATURES, | |
452 | .xlevel = 0, | |
453 | }, | |
454 | { | |
455 | .name = "athlon", | |
456 | .level = 2, | |
457 | .vendor1 = CPUID_VENDOR_AMD_1, | |
458 | .vendor2 = CPUID_VENDOR_AMD_2, | |
459 | .vendor3 = CPUID_VENDOR_AMD_3, | |
460 | .family = 6, | |
461 | .model = 2, | |
462 | .stepping = 3, | |
463 | .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, | |
42673936 | 464 | .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
c6dc6f63 AP |
465 | .xlevel = 0x80000008, |
466 | /* XXX: put another string ? */ | |
467 | .model_id = "QEMU Virtual CPU version " QEMU_VERSION, | |
468 | }, | |
469 | { | |
470 | .name = "n270", | |
471 | /* original is on level 10 */ | |
472 | .level = 5, | |
473 | .family = 6, | |
474 | .model = 28, | |
475 | .stepping = 2, | |
476 | .features = PPRO_FEATURES | | |
8560efed AJ |
477 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | |
478 | CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, | |
c6dc6f63 | 479 | /* Some CPUs got no CPUID_SEP */ |
8560efed AJ |
480 | .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
481 | CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR, | |
42673936 | 482 | .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX, |
8560efed | 483 | .ext3_features = CPUID_EXT3_LAHF_LM, |
c6dc6f63 AP |
484 | .xlevel = 0x8000000A, |
485 | .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", | |
486 | }, | |
487 | }; | |
488 | ||
489 | static int cpu_x86_fill_model_id(char *str) | |
490 | { | |
491 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; | |
492 | int i; | |
493 | ||
494 | for (i = 0; i < 3; i++) { | |
495 | host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); | |
496 | memcpy(str + i * 16 + 0, &eax, 4); | |
497 | memcpy(str + i * 16 + 4, &ebx, 4); | |
498 | memcpy(str + i * 16 + 8, &ecx, 4); | |
499 | memcpy(str + i * 16 + 12, &edx, 4); | |
500 | } | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) | |
505 | { | |
506 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; | |
507 | ||
508 | x86_cpu_def->name = "host"; | |
509 | host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); | |
510 | x86_cpu_def->level = eax; | |
511 | x86_cpu_def->vendor1 = ebx; | |
512 | x86_cpu_def->vendor2 = edx; | |
513 | x86_cpu_def->vendor3 = ecx; | |
514 | ||
515 | host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); | |
516 | x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); | |
517 | x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); | |
518 | x86_cpu_def->stepping = eax & 0x0F; | |
519 | x86_cpu_def->ext_features = ecx; | |
520 | x86_cpu_def->features = edx; | |
521 | ||
522 | host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); | |
523 | x86_cpu_def->xlevel = eax; | |
524 | ||
525 | host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); | |
526 | x86_cpu_def->ext2_features = edx; | |
527 | x86_cpu_def->ext3_features = ecx; | |
528 | cpu_x86_fill_model_id(x86_cpu_def->model_id); | |
529 | x86_cpu_def->vendor_override = 0; | |
530 | ||
b3baa152 BW |
531 | /* Call Centaur's CPUID instruction. */ |
532 | if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 && | |
533 | x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && | |
534 | x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { | |
535 | host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); | |
536 | if (eax >= 0xC0000001) { | |
537 | /* Support VIA max extended level */ | |
538 | x86_cpu_def->xlevel2 = eax; | |
539 | host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); | |
540 | x86_cpu_def->ext4_features = edx; | |
541 | } | |
542 | } | |
296acb64 JR |
543 | |
544 | /* | |
545 | * Every SVM feature requires emulation support in KVM - so we can't just | |
546 | * read the host features here. KVM might even support SVM features not | |
547 | * available on the host hardware. Just set all bits and mask out the | |
548 | * unsupported ones later. | |
549 | */ | |
550 | x86_cpu_def->svm_features = -1; | |
551 | ||
c6dc6f63 AP |
552 | return 0; |
553 | } | |
554 | ||
555 | static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) | |
556 | { | |
557 | int i; | |
558 | ||
559 | for (i = 0; i < 32; ++i) | |
560 | if (1 << i & mask) { | |
561 | fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested" | |
562 | " flag '%s' [0x%08x]\n", | |
563 | f->cpuid >> 16, f->cpuid & 0xffff, | |
564 | f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask); | |
565 | break; | |
566 | } | |
567 | return 0; | |
568 | } | |
569 | ||
570 | /* best effort attempt to inform user requested cpu flags aren't making | |
571 | * their way to the guest. Note: ft[].check_feat ideally should be | |
572 | * specified via a guest_def field to suppress report of extraneous flags. | |
573 | */ | |
574 | static int check_features_against_host(x86_def_t *guest_def) | |
575 | { | |
576 | x86_def_t host_def; | |
577 | uint32_t mask; | |
578 | int rv, i; | |
579 | struct model_features_t ft[] = { | |
580 | {&guest_def->features, &host_def.features, | |
581 | ~0, feature_name, 0x00000000}, | |
582 | {&guest_def->ext_features, &host_def.ext_features, | |
583 | ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001}, | |
584 | {&guest_def->ext2_features, &host_def.ext2_features, | |
585 | ~PPRO_FEATURES, ext2_feature_name, 0x80000000}, | |
586 | {&guest_def->ext3_features, &host_def.ext3_features, | |
587 | ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}}; | |
588 | ||
589 | cpu_x86_fill_host(&host_def); | |
66fe09ee | 590 | for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) |
c6dc6f63 AP |
591 | for (mask = 1; mask; mask <<= 1) |
592 | if (ft[i].check_feat & mask && *ft[i].guest_feat & mask && | |
593 | !(*ft[i].host_feat & mask)) { | |
594 | unavailable_host_feature(&ft[i], mask); | |
595 | rv = 1; | |
596 | } | |
597 | return rv; | |
598 | } | |
599 | ||
ed5e1ec3 AF |
600 | static void x86_cpuid_version_set_family(CPUX86State *env, int family) |
601 | { | |
602 | env->cpuid_version &= ~0xff00f00; | |
603 | if (family > 0x0f) { | |
604 | env->cpuid_version |= 0xf00 | ((family - 0x0f) << 20); | |
605 | } else { | |
606 | env->cpuid_version |= family << 8; | |
607 | } | |
608 | } | |
609 | ||
b0704cbd AF |
610 | static void x86_cpuid_version_set_model(CPUX86State *env, int model) |
611 | { | |
612 | env->cpuid_version &= ~0xf00f0; | |
613 | env->cpuid_version |= ((model & 0xf) << 4) | ((model >> 4) << 16); | |
614 | } | |
615 | ||
38c3dc46 AF |
616 | static void x86_cpuid_version_set_stepping(CPUX86State *env, int stepping) |
617 | { | |
618 | env->cpuid_version &= ~0xf; | |
619 | env->cpuid_version |= stepping & 0xf; | |
620 | } | |
621 | ||
dcce6675 AF |
622 | static void x86_cpuid_set_model_id(CPUX86State *env, const char *model_id) |
623 | { | |
624 | int c, len, i; | |
625 | ||
626 | if (model_id == NULL) { | |
627 | model_id = ""; | |
628 | } | |
629 | len = strlen(model_id); | |
d0a6acf4 | 630 | memset(env->cpuid_model, 0, 48); |
dcce6675 AF |
631 | for (i = 0; i < 48; i++) { |
632 | if (i >= len) { | |
633 | c = '\0'; | |
634 | } else { | |
635 | c = (uint8_t)model_id[i]; | |
636 | } | |
637 | env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); | |
638 | } | |
639 | } | |
640 | ||
c6dc6f63 AP |
641 | static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) |
642 | { | |
643 | unsigned int i; | |
644 | x86_def_t *def; | |
645 | ||
d3c481b3 | 646 | char *s = g_strdup(cpu_model); |
c6dc6f63 | 647 | char *featurestr, *name = strtok(s, ","); |
296acb64 JR |
648 | /* Features to be added*/ |
649 | uint32_t plus_features = 0, plus_ext_features = 0; | |
650 | uint32_t plus_ext2_features = 0, plus_ext3_features = 0; | |
651 | uint32_t plus_kvm_features = 0, plus_svm_features = 0; | |
652 | /* Features to be removed */ | |
653 | uint32_t minus_features = 0, minus_ext_features = 0; | |
654 | uint32_t minus_ext2_features = 0, minus_ext3_features = 0; | |
655 | uint32_t minus_kvm_features = 0, minus_svm_features = 0; | |
c6dc6f63 AP |
656 | uint32_t numvalue; |
657 | ||
658 | for (def = x86_defs; def; def = def->next) | |
04c5b17a | 659 | if (name && !strcmp(name, def->name)) |
c6dc6f63 | 660 | break; |
04c5b17a | 661 | if (kvm_enabled() && name && strcmp(name, "host") == 0) { |
c6dc6f63 AP |
662 | cpu_x86_fill_host(x86_cpu_def); |
663 | } else if (!def) { | |
664 | goto error; | |
665 | } else { | |
666 | memcpy(x86_cpu_def, def, sizeof(*def)); | |
667 | } | |
668 | ||
669 | plus_kvm_features = ~0; /* not supported bits will be filtered out later */ | |
670 | ||
671 | add_flagname_to_bitmaps("hypervisor", &plus_features, | |
672 | &plus_ext_features, &plus_ext2_features, &plus_ext3_features, | |
296acb64 | 673 | &plus_kvm_features, &plus_svm_features); |
c6dc6f63 AP |
674 | |
675 | featurestr = strtok(NULL, ","); | |
676 | ||
677 | while (featurestr) { | |
678 | char *val; | |
679 | if (featurestr[0] == '+') { | |
296acb64 JR |
680 | add_flagname_to_bitmaps(featurestr + 1, &plus_features, |
681 | &plus_ext_features, &plus_ext2_features, | |
682 | &plus_ext3_features, &plus_kvm_features, | |
683 | &plus_svm_features); | |
c6dc6f63 | 684 | } else if (featurestr[0] == '-') { |
296acb64 JR |
685 | add_flagname_to_bitmaps(featurestr + 1, &minus_features, |
686 | &minus_ext_features, &minus_ext2_features, | |
687 | &minus_ext3_features, &minus_kvm_features, | |
688 | &minus_svm_features); | |
c6dc6f63 AP |
689 | } else if ((val = strchr(featurestr, '='))) { |
690 | *val = 0; val++; | |
691 | if (!strcmp(featurestr, "family")) { | |
692 | char *err; | |
693 | numvalue = strtoul(val, &err, 0); | |
a88a677f | 694 | if (!*val || *err || numvalue > 0xff + 0xf) { |
c6dc6f63 AP |
695 | fprintf(stderr, "bad numerical value %s\n", val); |
696 | goto error; | |
697 | } | |
698 | x86_cpu_def->family = numvalue; | |
699 | } else if (!strcmp(featurestr, "model")) { | |
700 | char *err; | |
701 | numvalue = strtoul(val, &err, 0); | |
702 | if (!*val || *err || numvalue > 0xff) { | |
703 | fprintf(stderr, "bad numerical value %s\n", val); | |
704 | goto error; | |
705 | } | |
706 | x86_cpu_def->model = numvalue; | |
707 | } else if (!strcmp(featurestr, "stepping")) { | |
708 | char *err; | |
709 | numvalue = strtoul(val, &err, 0); | |
710 | if (!*val || *err || numvalue > 0xf) { | |
711 | fprintf(stderr, "bad numerical value %s\n", val); | |
712 | goto error; | |
713 | } | |
714 | x86_cpu_def->stepping = numvalue ; | |
715 | } else if (!strcmp(featurestr, "level")) { | |
716 | char *err; | |
717 | numvalue = strtoul(val, &err, 0); | |
718 | if (!*val || *err) { | |
719 | fprintf(stderr, "bad numerical value %s\n", val); | |
720 | goto error; | |
721 | } | |
722 | x86_cpu_def->level = numvalue; | |
723 | } else if (!strcmp(featurestr, "xlevel")) { | |
724 | char *err; | |
725 | numvalue = strtoul(val, &err, 0); | |
726 | if (!*val || *err) { | |
727 | fprintf(stderr, "bad numerical value %s\n", val); | |
728 | goto error; | |
729 | } | |
730 | if (numvalue < 0x80000000) { | |
2f7a21c4 | 731 | numvalue += 0x80000000; |
c6dc6f63 AP |
732 | } |
733 | x86_cpu_def->xlevel = numvalue; | |
734 | } else if (!strcmp(featurestr, "vendor")) { | |
735 | if (strlen(val) != 12) { | |
736 | fprintf(stderr, "vendor string must be 12 chars long\n"); | |
737 | goto error; | |
738 | } | |
739 | x86_cpu_def->vendor1 = 0; | |
740 | x86_cpu_def->vendor2 = 0; | |
741 | x86_cpu_def->vendor3 = 0; | |
742 | for(i = 0; i < 4; i++) { | |
743 | x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i); | |
744 | x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i); | |
745 | x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i); | |
746 | } | |
747 | x86_cpu_def->vendor_override = 1; | |
748 | } else if (!strcmp(featurestr, "model_id")) { | |
749 | pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id), | |
750 | val); | |
b862d1fe JR |
751 | } else if (!strcmp(featurestr, "tsc_freq")) { |
752 | int64_t tsc_freq; | |
753 | char *err; | |
754 | ||
755 | tsc_freq = strtosz_suffix_unit(val, &err, | |
756 | STRTOSZ_DEFSUFFIX_B, 1000); | |
45009a30 | 757 | if (tsc_freq < 0 || *err) { |
b862d1fe JR |
758 | fprintf(stderr, "bad numerical value %s\n", val); |
759 | goto error; | |
760 | } | |
761 | x86_cpu_def->tsc_khz = tsc_freq / 1000; | |
28f52cc0 VR |
762 | } else if (!strcmp(featurestr, "hv_spinlocks")) { |
763 | char *err; | |
764 | numvalue = strtoul(val, &err, 0); | |
765 | if (!*val || *err) { | |
766 | fprintf(stderr, "bad numerical value %s\n", val); | |
767 | goto error; | |
768 | } | |
769 | hyperv_set_spinlock_retries(numvalue); | |
c6dc6f63 AP |
770 | } else { |
771 | fprintf(stderr, "unrecognized feature %s\n", featurestr); | |
772 | goto error; | |
773 | } | |
774 | } else if (!strcmp(featurestr, "check")) { | |
775 | check_cpuid = 1; | |
776 | } else if (!strcmp(featurestr, "enforce")) { | |
777 | check_cpuid = enforce_cpuid = 1; | |
28f52cc0 VR |
778 | } else if (!strcmp(featurestr, "hv_relaxed")) { |
779 | hyperv_enable_relaxed_timing(true); | |
780 | } else if (!strcmp(featurestr, "hv_vapic")) { | |
781 | hyperv_enable_vapic_recommended(true); | |
c6dc6f63 AP |
782 | } else { |
783 | fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr); | |
784 | goto error; | |
785 | } | |
786 | featurestr = strtok(NULL, ","); | |
787 | } | |
788 | x86_cpu_def->features |= plus_features; | |
789 | x86_cpu_def->ext_features |= plus_ext_features; | |
790 | x86_cpu_def->ext2_features |= plus_ext2_features; | |
791 | x86_cpu_def->ext3_features |= plus_ext3_features; | |
792 | x86_cpu_def->kvm_features |= plus_kvm_features; | |
296acb64 | 793 | x86_cpu_def->svm_features |= plus_svm_features; |
c6dc6f63 AP |
794 | x86_cpu_def->features &= ~minus_features; |
795 | x86_cpu_def->ext_features &= ~minus_ext_features; | |
796 | x86_cpu_def->ext2_features &= ~minus_ext2_features; | |
797 | x86_cpu_def->ext3_features &= ~minus_ext3_features; | |
798 | x86_cpu_def->kvm_features &= ~minus_kvm_features; | |
296acb64 | 799 | x86_cpu_def->svm_features &= ~minus_svm_features; |
c6dc6f63 AP |
800 | if (check_cpuid) { |
801 | if (check_features_against_host(x86_cpu_def) && enforce_cpuid) | |
802 | goto error; | |
803 | } | |
d3c481b3 | 804 | g_free(s); |
c6dc6f63 AP |
805 | return 0; |
806 | ||
807 | error: | |
d3c481b3 | 808 | g_free(s); |
c6dc6f63 AP |
809 | return -1; |
810 | } | |
811 | ||
812 | /* generate a composite string into buf of all cpuid names in featureset | |
813 | * selected by fbits. indicate truncation at bufsize in the event of overflow. | |
814 | * if flags, suppress names undefined in featureset. | |
815 | */ | |
816 | static void listflags(char *buf, int bufsize, uint32_t fbits, | |
817 | const char **featureset, uint32_t flags) | |
818 | { | |
819 | const char **p = &featureset[31]; | |
820 | char *q, *b, bit; | |
821 | int nc; | |
822 | ||
823 | b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; | |
824 | *buf = '\0'; | |
825 | for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) | |
826 | if (fbits & 1 << bit && (*p || !flags)) { | |
827 | if (*p) | |
828 | nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); | |
829 | else | |
830 | nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); | |
831 | if (bufsize <= nc) { | |
832 | if (b) { | |
833 | memcpy(b, "...", sizeof("...")); | |
834 | } | |
835 | return; | |
836 | } | |
837 | q += nc; | |
838 | bufsize -= nc; | |
839 | } | |
840 | } | |
841 | ||
842 | /* generate CPU information: | |
843 | * -? list model names | |
844 | * -?model list model names/IDs | |
845 | * -?dump output all model (x86_def_t) data | |
846 | * -?cpuid list all recognized cpuid flag names | |
847 | */ | |
9a78eead | 848 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg) |
c6dc6f63 AP |
849 | { |
850 | unsigned char model = !strcmp("?model", optarg); | |
851 | unsigned char dump = !strcmp("?dump", optarg); | |
852 | unsigned char cpuid = !strcmp("?cpuid", optarg); | |
853 | x86_def_t *def; | |
854 | char buf[256]; | |
855 | ||
856 | if (cpuid) { | |
857 | (*cpu_fprintf)(f, "Recognized CPUID flags:\n"); | |
858 | listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1); | |
859 | (*cpu_fprintf)(f, " f_edx: %s\n", buf); | |
860 | listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1); | |
861 | (*cpu_fprintf)(f, " f_ecx: %s\n", buf); | |
862 | listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1); | |
863 | (*cpu_fprintf)(f, " extf_edx: %s\n", buf); | |
864 | listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1); | |
865 | (*cpu_fprintf)(f, " extf_ecx: %s\n", buf); | |
866 | return; | |
867 | } | |
868 | for (def = x86_defs; def; def = def->next) { | |
869 | snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name); | |
870 | if (model || dump) { | |
871 | (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id); | |
872 | } else { | |
873 | (*cpu_fprintf)(f, "x86 %16s\n", buf); | |
874 | } | |
875 | if (dump) { | |
876 | memcpy(buf, &def->vendor1, sizeof (def->vendor1)); | |
877 | memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2)); | |
878 | memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3)); | |
879 | buf[12] = '\0'; | |
880 | (*cpu_fprintf)(f, | |
881 | " family %d model %d stepping %d level %d xlevel 0x%x" | |
882 | " vendor \"%s\"\n", | |
883 | def->family, def->model, def->stepping, def->level, | |
884 | def->xlevel, buf); | |
885 | listflags(buf, sizeof (buf), def->features, feature_name, 0); | |
886 | (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features, | |
887 | buf); | |
888 | listflags(buf, sizeof (buf), def->ext_features, ext_feature_name, | |
889 | 0); | |
890 | (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features, | |
891 | buf); | |
892 | listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name, | |
893 | 0); | |
894 | (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n", | |
895 | def->ext2_features, buf); | |
896 | listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name, | |
897 | 0); | |
898 | (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n", | |
899 | def->ext3_features, buf); | |
900 | (*cpu_fprintf)(f, "\n"); | |
901 | } | |
902 | } | |
ed2c54d4 AP |
903 | if (kvm_enabled()) { |
904 | (*cpu_fprintf)(f, "x86 %16s\n", "[host]"); | |
905 | } | |
c6dc6f63 AP |
906 | } |
907 | ||
61dcd775 | 908 | int cpu_x86_register(X86CPU *cpu, const char *cpu_model) |
c6dc6f63 | 909 | { |
61dcd775 | 910 | CPUX86State *env = &cpu->env; |
c6dc6f63 AP |
911 | x86_def_t def1, *def = &def1; |
912 | ||
db0ad1ba JR |
913 | memset(def, 0, sizeof(*def)); |
914 | ||
c6dc6f63 AP |
915 | if (cpu_x86_find_by_name(def, cpu_model) < 0) |
916 | return -1; | |
917 | if (def->vendor1) { | |
918 | env->cpuid_vendor1 = def->vendor1; | |
919 | env->cpuid_vendor2 = def->vendor2; | |
920 | env->cpuid_vendor3 = def->vendor3; | |
921 | } else { | |
922 | env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; | |
923 | env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; | |
924 | env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; | |
925 | } | |
926 | env->cpuid_vendor_override = def->vendor_override; | |
927 | env->cpuid_level = def->level; | |
ed5e1ec3 | 928 | x86_cpuid_version_set_family(env, def->family); |
b0704cbd | 929 | x86_cpuid_version_set_model(env, def->model); |
38c3dc46 | 930 | x86_cpuid_version_set_stepping(env, def->stepping); |
c6dc6f63 | 931 | env->cpuid_features = def->features; |
c6dc6f63 AP |
932 | env->cpuid_ext_features = def->ext_features; |
933 | env->cpuid_ext2_features = def->ext2_features; | |
4d067ed7 | 934 | env->cpuid_ext3_features = def->ext3_features; |
c6dc6f63 AP |
935 | env->cpuid_xlevel = def->xlevel; |
936 | env->cpuid_kvm_features = def->kvm_features; | |
296acb64 | 937 | env->cpuid_svm_features = def->svm_features; |
b3baa152 BW |
938 | env->cpuid_ext4_features = def->ext4_features; |
939 | env->cpuid_xlevel2 = def->xlevel2; | |
b862d1fe | 940 | env->tsc_khz = def->tsc_khz; |
551a2dec AP |
941 | if (!kvm_enabled()) { |
942 | env->cpuid_features &= TCG_FEATURES; | |
943 | env->cpuid_ext_features &= TCG_EXT_FEATURES; | |
944 | env->cpuid_ext2_features &= (TCG_EXT2_FEATURES | |
945 | #ifdef TARGET_X86_64 | |
946 | | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM | |
947 | #endif | |
948 | ); | |
949 | env->cpuid_ext3_features &= TCG_EXT3_FEATURES; | |
296acb64 | 950 | env->cpuid_svm_features &= TCG_SVM_FEATURES; |
551a2dec | 951 | } |
dcce6675 | 952 | x86_cpuid_set_model_id(env, def->model_id); |
c6dc6f63 AP |
953 | return 0; |
954 | } | |
955 | ||
956 | #if !defined(CONFIG_USER_ONLY) | |
957 | /* copy vendor id string to 32 bit register, nul pad as needed | |
958 | */ | |
959 | static void cpyid(const char *s, uint32_t *id) | |
960 | { | |
961 | char *d = (char *)id; | |
962 | char i; | |
963 | ||
964 | for (i = sizeof (*id); i--; ) | |
965 | *d++ = *s ? *s++ : '\0'; | |
966 | } | |
967 | ||
968 | /* interpret radix and convert from string to arbitrary scalar, | |
969 | * otherwise flag failure | |
970 | */ | |
971 | #define setscalar(pval, str, perr) \ | |
972 | { \ | |
973 | char *pend; \ | |
974 | unsigned long ul; \ | |
975 | \ | |
976 | ul = strtoul(str, &pend, 0); \ | |
977 | *str && !*pend ? (*pval = ul) : (*perr = 1); \ | |
978 | } | |
979 | ||
980 | /* map cpuid options to feature bits, otherwise return failure | |
981 | * (option tags in *str are delimited by whitespace) | |
982 | */ | |
983 | static void setfeatures(uint32_t *pval, const char *str, | |
984 | const char **featureset, int *perr) | |
985 | { | |
986 | const char *p, *q; | |
987 | ||
988 | for (q = p = str; *p || *q; q = p) { | |
989 | while (iswhite(*p)) | |
990 | q = ++p; | |
991 | while (*p && !iswhite(*p)) | |
992 | ++p; | |
993 | if (!*q && !*p) | |
994 | return; | |
995 | if (!lookup_feature(pval, q, p, featureset)) { | |
996 | fprintf(stderr, "error: feature \"%.*s\" not available in set\n", | |
997 | (int)(p - q), q); | |
998 | *perr = 1; | |
999 | return; | |
1000 | } | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /* map config file options to x86_def_t form | |
1005 | */ | |
1006 | static int cpudef_setfield(const char *name, const char *str, void *opaque) | |
1007 | { | |
1008 | x86_def_t *def = opaque; | |
1009 | int err = 0; | |
1010 | ||
1011 | if (!strcmp(name, "name")) { | |
99e1dec0 | 1012 | g_free((void *)def->name); |
d3c481b3 | 1013 | def->name = g_strdup(str); |
c6dc6f63 AP |
1014 | } else if (!strcmp(name, "model_id")) { |
1015 | strncpy(def->model_id, str, sizeof (def->model_id)); | |
1016 | } else if (!strcmp(name, "level")) { | |
1017 | setscalar(&def->level, str, &err) | |
1018 | } else if (!strcmp(name, "vendor")) { | |
1019 | cpyid(&str[0], &def->vendor1); | |
1020 | cpyid(&str[4], &def->vendor2); | |
1021 | cpyid(&str[8], &def->vendor3); | |
1022 | } else if (!strcmp(name, "family")) { | |
1023 | setscalar(&def->family, str, &err) | |
1024 | } else if (!strcmp(name, "model")) { | |
1025 | setscalar(&def->model, str, &err) | |
1026 | } else if (!strcmp(name, "stepping")) { | |
1027 | setscalar(&def->stepping, str, &err) | |
1028 | } else if (!strcmp(name, "feature_edx")) { | |
1029 | setfeatures(&def->features, str, feature_name, &err); | |
1030 | } else if (!strcmp(name, "feature_ecx")) { | |
1031 | setfeatures(&def->ext_features, str, ext_feature_name, &err); | |
1032 | } else if (!strcmp(name, "extfeature_edx")) { | |
1033 | setfeatures(&def->ext2_features, str, ext2_feature_name, &err); | |
1034 | } else if (!strcmp(name, "extfeature_ecx")) { | |
1035 | setfeatures(&def->ext3_features, str, ext3_feature_name, &err); | |
1036 | } else if (!strcmp(name, "xlevel")) { | |
1037 | setscalar(&def->xlevel, str, &err) | |
1038 | } else { | |
1039 | fprintf(stderr, "error: unknown option [%s = %s]\n", name, str); | |
1040 | return (1); | |
1041 | } | |
1042 | if (err) { | |
1043 | fprintf(stderr, "error: bad option value [%s = %s]\n", name, str); | |
1044 | return (1); | |
1045 | } | |
1046 | return (0); | |
1047 | } | |
1048 | ||
1049 | /* register config file entry as x86_def_t | |
1050 | */ | |
1051 | static int cpudef_register(QemuOpts *opts, void *opaque) | |
1052 | { | |
7267c094 | 1053 | x86_def_t *def = g_malloc0(sizeof (x86_def_t)); |
c6dc6f63 AP |
1054 | |
1055 | qemu_opt_foreach(opts, cpudef_setfield, def, 1); | |
1056 | def->next = x86_defs; | |
1057 | x86_defs = def; | |
1058 | return (0); | |
1059 | } | |
0e26b7b8 BS |
1060 | |
1061 | void cpu_clear_apic_feature(CPUX86State *env) | |
1062 | { | |
1063 | env->cpuid_features &= ~CPUID_APIC; | |
1064 | } | |
1065 | ||
c6dc6f63 AP |
1066 | #endif /* !CONFIG_USER_ONLY */ |
1067 | ||
1068 | /* register "cpudef" models defined in configuration file. Here we first | |
1069 | * preload any built-in definitions | |
1070 | */ | |
1071 | void x86_cpudef_setup(void) | |
1072 | { | |
1073 | int i; | |
1074 | ||
1075 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { | |
1076 | builtin_x86_defs[i].next = x86_defs; | |
1077 | builtin_x86_defs[i].flags = 1; | |
1078 | x86_defs = &builtin_x86_defs[i]; | |
1079 | } | |
1080 | #if !defined(CONFIG_USER_ONLY) | |
3329f07b | 1081 | qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0); |
c6dc6f63 AP |
1082 | #endif |
1083 | } | |
1084 | ||
c6dc6f63 AP |
1085 | static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, |
1086 | uint32_t *ecx, uint32_t *edx) | |
1087 | { | |
1088 | *ebx = env->cpuid_vendor1; | |
1089 | *edx = env->cpuid_vendor2; | |
1090 | *ecx = env->cpuid_vendor3; | |
1091 | ||
1092 | /* sysenter isn't supported on compatibility mode on AMD, syscall | |
1093 | * isn't supported in compatibility mode on Intel. | |
1094 | * Normally we advertise the actual cpu vendor, but you can override | |
1095 | * this if you want to use KVM's sysenter/syscall emulation | |
1096 | * in compatibility mode and when doing cross vendor migration | |
1097 | */ | |
89354998 | 1098 | if (kvm_enabled() && ! env->cpuid_vendor_override) { |
c6dc6f63 AP |
1099 | host_cpuid(0, 0, NULL, ebx, ecx, edx); |
1100 | } | |
1101 | } | |
1102 | ||
1103 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
1104 | uint32_t *eax, uint32_t *ebx, | |
1105 | uint32_t *ecx, uint32_t *edx) | |
1106 | { | |
1107 | /* test if maximum index reached */ | |
1108 | if (index & 0x80000000) { | |
b3baa152 BW |
1109 | if (index > env->cpuid_xlevel) { |
1110 | if (env->cpuid_xlevel2 > 0) { | |
1111 | /* Handle the Centaur's CPUID instruction. */ | |
1112 | if (index > env->cpuid_xlevel2) { | |
1113 | index = env->cpuid_xlevel2; | |
1114 | } else if (index < 0xC0000000) { | |
1115 | index = env->cpuid_xlevel; | |
1116 | } | |
1117 | } else { | |
1118 | index = env->cpuid_xlevel; | |
1119 | } | |
1120 | } | |
c6dc6f63 AP |
1121 | } else { |
1122 | if (index > env->cpuid_level) | |
1123 | index = env->cpuid_level; | |
1124 | } | |
1125 | ||
1126 | switch(index) { | |
1127 | case 0: | |
1128 | *eax = env->cpuid_level; | |
1129 | get_cpuid_vendor(env, ebx, ecx, edx); | |
1130 | break; | |
1131 | case 1: | |
1132 | *eax = env->cpuid_version; | |
1133 | *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ | |
1134 | *ecx = env->cpuid_ext_features; | |
1135 | *edx = env->cpuid_features; | |
1136 | if (env->nr_cores * env->nr_threads > 1) { | |
1137 | *ebx |= (env->nr_cores * env->nr_threads) << 16; | |
1138 | *edx |= 1 << 28; /* HTT bit */ | |
1139 | } | |
1140 | break; | |
1141 | case 2: | |
1142 | /* cache info: needed for Pentium Pro compatibility */ | |
1143 | *eax = 1; | |
1144 | *ebx = 0; | |
1145 | *ecx = 0; | |
1146 | *edx = 0x2c307d; | |
1147 | break; | |
1148 | case 4: | |
1149 | /* cache info: needed for Core compatibility */ | |
1150 | if (env->nr_cores > 1) { | |
2f7a21c4 | 1151 | *eax = (env->nr_cores - 1) << 26; |
c6dc6f63 | 1152 | } else { |
2f7a21c4 | 1153 | *eax = 0; |
c6dc6f63 AP |
1154 | } |
1155 | switch (count) { | |
1156 | case 0: /* L1 dcache info */ | |
1157 | *eax |= 0x0000121; | |
1158 | *ebx = 0x1c0003f; | |
1159 | *ecx = 0x000003f; | |
1160 | *edx = 0x0000001; | |
1161 | break; | |
1162 | case 1: /* L1 icache info */ | |
1163 | *eax |= 0x0000122; | |
1164 | *ebx = 0x1c0003f; | |
1165 | *ecx = 0x000003f; | |
1166 | *edx = 0x0000001; | |
1167 | break; | |
1168 | case 2: /* L2 cache info */ | |
1169 | *eax |= 0x0000143; | |
1170 | if (env->nr_threads > 1) { | |
1171 | *eax |= (env->nr_threads - 1) << 14; | |
1172 | } | |
1173 | *ebx = 0x3c0003f; | |
1174 | *ecx = 0x0000fff; | |
1175 | *edx = 0x0000001; | |
1176 | break; | |
1177 | default: /* end of info */ | |
1178 | *eax = 0; | |
1179 | *ebx = 0; | |
1180 | *ecx = 0; | |
1181 | *edx = 0; | |
1182 | break; | |
1183 | } | |
1184 | break; | |
1185 | case 5: | |
1186 | /* mwait info: needed for Core compatibility */ | |
1187 | *eax = 0; /* Smallest monitor-line size in bytes */ | |
1188 | *ebx = 0; /* Largest monitor-line size in bytes */ | |
1189 | *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; | |
1190 | *edx = 0; | |
1191 | break; | |
1192 | case 6: | |
1193 | /* Thermal and Power Leaf */ | |
1194 | *eax = 0; | |
1195 | *ebx = 0; | |
1196 | *ecx = 0; | |
1197 | *edx = 0; | |
1198 | break; | |
f7911686 YW |
1199 | case 7: |
1200 | if (kvm_enabled()) { | |
ba9bc59e JK |
1201 | KVMState *s = env->kvm_state; |
1202 | ||
1203 | *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX); | |
1204 | *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX); | |
1205 | *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX); | |
1206 | *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX); | |
f7911686 YW |
1207 | } else { |
1208 | *eax = 0; | |
1209 | *ebx = 0; | |
1210 | *ecx = 0; | |
1211 | *edx = 0; | |
1212 | } | |
1213 | break; | |
c6dc6f63 AP |
1214 | case 9: |
1215 | /* Direct Cache Access Information Leaf */ | |
1216 | *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ | |
1217 | *ebx = 0; | |
1218 | *ecx = 0; | |
1219 | *edx = 0; | |
1220 | break; | |
1221 | case 0xA: | |
1222 | /* Architectural Performance Monitoring Leaf */ | |
a0fa8208 GN |
1223 | if (kvm_enabled()) { |
1224 | KVMState *s = env->kvm_state; | |
1225 | ||
1226 | *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); | |
1227 | *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); | |
1228 | *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); | |
1229 | *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); | |
1230 | } else { | |
1231 | *eax = 0; | |
1232 | *ebx = 0; | |
1233 | *ecx = 0; | |
1234 | *edx = 0; | |
1235 | } | |
c6dc6f63 | 1236 | break; |
51e49430 SY |
1237 | case 0xD: |
1238 | /* Processor Extended State */ | |
1239 | if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) { | |
1240 | *eax = 0; | |
1241 | *ebx = 0; | |
1242 | *ecx = 0; | |
1243 | *edx = 0; | |
1244 | break; | |
1245 | } | |
1246 | if (kvm_enabled()) { | |
ba9bc59e JK |
1247 | KVMState *s = env->kvm_state; |
1248 | ||
1249 | *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX); | |
1250 | *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX); | |
1251 | *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX); | |
1252 | *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX); | |
51e49430 SY |
1253 | } else { |
1254 | *eax = 0; | |
1255 | *ebx = 0; | |
1256 | *ecx = 0; | |
1257 | *edx = 0; | |
1258 | } | |
1259 | break; | |
c6dc6f63 AP |
1260 | case 0x80000000: |
1261 | *eax = env->cpuid_xlevel; | |
1262 | *ebx = env->cpuid_vendor1; | |
1263 | *edx = env->cpuid_vendor2; | |
1264 | *ecx = env->cpuid_vendor3; | |
1265 | break; | |
1266 | case 0x80000001: | |
1267 | *eax = env->cpuid_version; | |
1268 | *ebx = 0; | |
1269 | *ecx = env->cpuid_ext3_features; | |
1270 | *edx = env->cpuid_ext2_features; | |
1271 | ||
1272 | /* The Linux kernel checks for the CMPLegacy bit and | |
1273 | * discards multiple thread information if it is set. | |
1274 | * So dont set it here for Intel to make Linux guests happy. | |
1275 | */ | |
1276 | if (env->nr_cores * env->nr_threads > 1) { | |
1277 | uint32_t tebx, tecx, tedx; | |
1278 | get_cpuid_vendor(env, &tebx, &tecx, &tedx); | |
1279 | if (tebx != CPUID_VENDOR_INTEL_1 || | |
1280 | tedx != CPUID_VENDOR_INTEL_2 || | |
1281 | tecx != CPUID_VENDOR_INTEL_3) { | |
1282 | *ecx |= 1 << 1; /* CmpLegacy bit */ | |
1283 | } | |
1284 | } | |
c6dc6f63 AP |
1285 | break; |
1286 | case 0x80000002: | |
1287 | case 0x80000003: | |
1288 | case 0x80000004: | |
1289 | *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; | |
1290 | *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; | |
1291 | *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; | |
1292 | *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; | |
1293 | break; | |
1294 | case 0x80000005: | |
1295 | /* cache info (L1 cache) */ | |
1296 | *eax = 0x01ff01ff; | |
1297 | *ebx = 0x01ff01ff; | |
1298 | *ecx = 0x40020140; | |
1299 | *edx = 0x40020140; | |
1300 | break; | |
1301 | case 0x80000006: | |
1302 | /* cache info (L2 cache) */ | |
1303 | *eax = 0; | |
1304 | *ebx = 0x42004200; | |
1305 | *ecx = 0x02008140; | |
1306 | *edx = 0; | |
1307 | break; | |
1308 | case 0x80000008: | |
1309 | /* virtual & phys address size in low 2 bytes. */ | |
1310 | /* XXX: This value must match the one used in the MMU code. */ | |
1311 | if (env->cpuid_ext2_features & CPUID_EXT2_LM) { | |
1312 | /* 64 bit processor */ | |
1313 | /* XXX: The physical address space is limited to 42 bits in exec.c. */ | |
1314 | *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ | |
1315 | } else { | |
1316 | if (env->cpuid_features & CPUID_PSE36) | |
1317 | *eax = 0x00000024; /* 36 bits physical */ | |
1318 | else | |
1319 | *eax = 0x00000020; /* 32 bits physical */ | |
1320 | } | |
1321 | *ebx = 0; | |
1322 | *ecx = 0; | |
1323 | *edx = 0; | |
1324 | if (env->nr_cores * env->nr_threads > 1) { | |
1325 | *ecx |= (env->nr_cores * env->nr_threads) - 1; | |
1326 | } | |
1327 | break; | |
1328 | case 0x8000000A: | |
296acb64 JR |
1329 | if (env->cpuid_ext3_features & CPUID_EXT3_SVM) { |
1330 | *eax = 0x00000001; /* SVM Revision */ | |
1331 | *ebx = 0x00000010; /* nr of ASIDs */ | |
1332 | *ecx = 0; | |
1333 | *edx = env->cpuid_svm_features; /* optional features */ | |
1334 | } else { | |
1335 | *eax = 0; | |
1336 | *ebx = 0; | |
1337 | *ecx = 0; | |
1338 | *edx = 0; | |
1339 | } | |
c6dc6f63 | 1340 | break; |
b3baa152 BW |
1341 | case 0xC0000000: |
1342 | *eax = env->cpuid_xlevel2; | |
1343 | *ebx = 0; | |
1344 | *ecx = 0; | |
1345 | *edx = 0; | |
1346 | break; | |
1347 | case 0xC0000001: | |
1348 | /* Support for VIA CPU's CPUID instruction */ | |
1349 | *eax = env->cpuid_version; | |
1350 | *ebx = 0; | |
1351 | *ecx = 0; | |
1352 | *edx = env->cpuid_ext4_features; | |
1353 | break; | |
1354 | case 0xC0000002: | |
1355 | case 0xC0000003: | |
1356 | case 0xC0000004: | |
1357 | /* Reserved for the future, and now filled with zero */ | |
1358 | *eax = 0; | |
1359 | *ebx = 0; | |
1360 | *ecx = 0; | |
1361 | *edx = 0; | |
1362 | break; | |
c6dc6f63 AP |
1363 | default: |
1364 | /* reserved values: zero */ | |
1365 | *eax = 0; | |
1366 | *ebx = 0; | |
1367 | *ecx = 0; | |
1368 | *edx = 0; | |
1369 | break; | |
1370 | } | |
1371 | } | |
5fd2087a AF |
1372 | |
1373 | /* CPUClass::reset() */ | |
1374 | static void x86_cpu_reset(CPUState *s) | |
1375 | { | |
1376 | X86CPU *cpu = X86_CPU(s); | |
1377 | X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); | |
1378 | CPUX86State *env = &cpu->env; | |
c1958aea AF |
1379 | int i; |
1380 | ||
1381 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
1382 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
1383 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); | |
1384 | } | |
5fd2087a AF |
1385 | |
1386 | xcc->parent_reset(s); | |
1387 | ||
c1958aea AF |
1388 | |
1389 | memset(env, 0, offsetof(CPUX86State, breakpoints)); | |
1390 | ||
1391 | tlb_flush(env, 1); | |
1392 | ||
1393 | env->old_exception = -1; | |
1394 | ||
1395 | /* init to reset state */ | |
1396 | ||
1397 | #ifdef CONFIG_SOFTMMU | |
1398 | env->hflags |= HF_SOFTMMU_MASK; | |
1399 | #endif | |
1400 | env->hflags2 |= HF2_GIF_MASK; | |
1401 | ||
1402 | cpu_x86_update_cr0(env, 0x60000010); | |
1403 | env->a20_mask = ~0x0; | |
1404 | env->smbase = 0x30000; | |
1405 | ||
1406 | env->idt.limit = 0xffff; | |
1407 | env->gdt.limit = 0xffff; | |
1408 | env->ldt.limit = 0xffff; | |
1409 | env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); | |
1410 | env->tr.limit = 0xffff; | |
1411 | env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); | |
1412 | ||
1413 | cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, | |
1414 | DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | | |
1415 | DESC_R_MASK | DESC_A_MASK); | |
1416 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, | |
1417 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
1418 | DESC_A_MASK); | |
1419 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, | |
1420 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
1421 | DESC_A_MASK); | |
1422 | cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, | |
1423 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
1424 | DESC_A_MASK); | |
1425 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, | |
1426 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
1427 | DESC_A_MASK); | |
1428 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, | |
1429 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
1430 | DESC_A_MASK); | |
1431 | ||
1432 | env->eip = 0xfff0; | |
1433 | env->regs[R_EDX] = env->cpuid_version; | |
1434 | ||
1435 | env->eflags = 0x2; | |
1436 | ||
1437 | /* FPU init */ | |
1438 | for (i = 0; i < 8; i++) { | |
1439 | env->fptags[i] = 1; | |
1440 | } | |
1441 | env->fpuc = 0x37f; | |
1442 | ||
1443 | env->mxcsr = 0x1f80; | |
1444 | ||
1445 | env->pat = 0x0007040600070406ULL; | |
1446 | env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; | |
1447 | ||
1448 | memset(env->dr, 0, sizeof(env->dr)); | |
1449 | env->dr[6] = DR6_FIXED_1; | |
1450 | env->dr[7] = DR7_FIXED_1; | |
1451 | cpu_breakpoint_remove_all(env, BP_CPU); | |
1452 | cpu_watchpoint_remove_all(env, BP_CPU); | |
5fd2087a AF |
1453 | } |
1454 | ||
de024815 AF |
1455 | static void mce_init(X86CPU *cpu) |
1456 | { | |
1457 | CPUX86State *cenv = &cpu->env; | |
1458 | unsigned int bank; | |
1459 | ||
1460 | if (((cenv->cpuid_version >> 8) & 0xf) >= 6 | |
1461 | && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) == | |
1462 | (CPUID_MCE | CPUID_MCA)) { | |
1463 | cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF; | |
1464 | cenv->mcg_ctl = ~(uint64_t)0; | |
1465 | for (bank = 0; bank < MCE_BANKS_DEF; bank++) { | |
1466 | cenv->mce_banks[bank * 4] = ~(uint64_t)0; | |
1467 | } | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | static void x86_cpu_initfn(Object *obj) | |
1472 | { | |
1473 | X86CPU *cpu = X86_CPU(obj); | |
1474 | CPUX86State *env = &cpu->env; | |
1475 | ||
1476 | cpu_exec_init(env); | |
1477 | env->cpuid_apic_id = env->cpu_index; | |
1478 | mce_init(cpu); | |
1479 | } | |
1480 | ||
5fd2087a AF |
1481 | static void x86_cpu_common_class_init(ObjectClass *oc, void *data) |
1482 | { | |
1483 | X86CPUClass *xcc = X86_CPU_CLASS(oc); | |
1484 | CPUClass *cc = CPU_CLASS(oc); | |
1485 | ||
1486 | xcc->parent_reset = cc->reset; | |
1487 | cc->reset = x86_cpu_reset; | |
1488 | } | |
1489 | ||
1490 | static const TypeInfo x86_cpu_type_info = { | |
1491 | .name = TYPE_X86_CPU, | |
1492 | .parent = TYPE_CPU, | |
1493 | .instance_size = sizeof(X86CPU), | |
de024815 | 1494 | .instance_init = x86_cpu_initfn, |
5fd2087a AF |
1495 | .abstract = false, |
1496 | .class_size = sizeof(X86CPUClass), | |
1497 | .class_init = x86_cpu_common_class_init, | |
1498 | }; | |
1499 | ||
1500 | static void x86_cpu_register_types(void) | |
1501 | { | |
1502 | type_register_static(&x86_cpu_type_info); | |
1503 | } | |
1504 | ||
1505 | type_init(x86_cpu_register_types) |